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* OpenSPARC T2 Processor File: n2_err_ncu_esr_3.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define MAIN_PAGE_HV_ALSO
#define SOC_ESR_REG 0x8000003000
#define SOC_ELE_REG 0x8000003008
#define SOC_EIE_REG 0x8000003010
#define SOC_EJR_REG 0x8000003018
#define SOC_FEE_REG 0x8000003020
#define SOC_PER_REG 0x8000003028
#define SOC_SII_SYN_REG 0x8000003030
#define SOC_NCU_SYN_REG 0x8000003038
.global My_Corrected_ECC_error_trap
setx SOC_ESR_REG, %l7, %g5
setx SOC_EIE_REG, %l7, %g5
mov TT_Corrected_ECC, %l0
My_Corrected_ECC_error_trap:
setx SOC_PER_REG, %l7, %g6
setx 0x8000000000000004, %l7, %i2
setx 0xff00000000000000, %l1, %g3 ! mask <63:56>
setx 0x8b00000000000000, %l1, %g2 ! <63>=F; <62>=Me; <61>=S -> 1 for sw_recov_err; 0 for hw_corr_err
! <60:56>=Err_type; SOCC=11=0xb
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