* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt_MAC.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
/************************************************************************
************************************************************************/
/* Initialize the NCU for the interrupt. */
xor %g7, 0x2, %g7 ! Reset interrupt enable
! Initially set all the Interrupt Management Registers
! Later will set all those not used to have a different vector number
setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
set 1, %g5 ! %g5 = value to write to INT_MAN reg.
add %g2, INT_MAN_STEP, %g2
or %g7, 0x2, %g7 ! Set interrupt enable
#include "niu_init_rx.h" ! Temporary added this initialization. Need to merg with niu_init.h
nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> RxGenConfig()
nop ! $EV trig_pc_d(1, @VA(.MAIN.rx_begin)) -> printf("Configuration for Rx port",*,1)
nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> Rxpktgen(0,10)
setx Rx_loop_count, %g1, %g4
! Have the 2 interrupts occured?
setx user_data_start, %g1, %g2
/**********************************************************************
**********************************************************************/
setx user_data_start, %l2, %l6
ldxa [%g0]ASI_SWVR_INTR_R, %l3
! Re-enable the interrupt in the NIU
setx 0x8100800018, %g1, %g2 ! LDGIMGN
setx 0x80000001, %g1, %g3
stxa %g3, [%g2]ASI_PRIMARY_LITTLE
/************************************************************************
************************************************************************/
SECTION descriptor data_va=0x100000200
/************************************************************************/