* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: interrupt_dmu_intr_reloc.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define ENABLE_PCIE_LINK_TRAINING
#define SYNC_THREADS 0xff
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
/************************************************************************
************************************************************************/
! Initialize the global registers.
be main_t0 ! branch if tread 0
ba main_t1_to_t63 ! branch if not thread 0
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
/* Initialize the NCU for the interrupt. */
xor %g5, 0x2, %g5 ! Reset interrupt enable
! Initialize Mondo Interrupt Vector Register
setx MONDO_INT_VEC, %g2, %g3
! Clear Mondo Interrupt Busy registers.
setx MONDO_INT_BUSY, %g1, %g2
setx MONDO_INT_BUSY_STEP, %g1, %g3
setx MONDO_INT_BUSY_COUNT, %g1, %g4
ncu_mondo_int_busy_loop_top:
bne ncu_mondo_int_busy_loop_top
! Initialize for MSI interrupt in PIU
! First clear MSI in case one pending.
setx PCI_E_MSI_CLEAR_ADDR, %g1, %g2
setx 0x4000000000000000, %g1, %g3
! Also clear in Interrupt Clear reg.
setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
set PCI_E_INT_CLEAR_STEP, %g1
! Setup all the event queues.
! First the Event Queue Base Address reg.
! Formatted for a bypass address.
setx PCI_E_EV_QUE_BASE_ADDRESS_ADDR, %g1, %g2
setx user_data_start+0x80000, %g1, %g3
setx 0x7ffff80000, %g1, %g5
setx 0xfffc000000000000, %g1, %g6
! Event Queue Control Set reg.s
setx PCI_E_EV_QUE_CTL_SET_ADDR, %g1, %g2
setx 0x100000000000, %g1, %g3 ! EN = 1
setx PCI_E_EV_QUE_CTL_SET_COUNT, %g1, %g4
setx PCI_E_EV_QUE_CTL_SET_STEP, %g1, %g5
! Now enable MSI interrupt
! First MSI addressing register
setx PCI_E_MSI_32_ADDRESS_ADDR, %g1, %g2
setx PCI_E_MSI_64_ADDRESS_ADDR, %g1, %g2
! MSI Mapping register, only init. the first, the trap handler does the rest
setx PCI_E_MSI_MAP_ADDR, %g1, %g2
setx 0x8000000000000000, %g1, %g3 ! V = 1, EQNUM = 0
! Now enable Mondo in PIU and set destination thread
! Interrupt Mapping register
setx PCI_E_INT_MAP_ADDR, %g1, %g5
set PCI_E_INT_MAP_STEP, %g1
setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
stx %g6, [%g5] ! interrupt controller = 1
or %g5, 0x2, %g5 ! Set interrupt enable
/* Sync up all the treads. */
SYNC_THREAD_MAIN( local_test_failed, %g1, %g2, %g3 )
/* Loop to kick off the MSI's */
/* Note that the interrupt trap handler will take care of doing the relocation */
setx PCI_E_EV_QUE_CTL_SET_COUNT, %g1, %g7
sllx %g7, 1, %g7 ! two interrupts per event queue
#ifdef DMU_INTR_RELOC_VEC
srlx %g7, 2, %g7 ! only do 1/4 of them for test vectors.
setx interrupt_flag, %g1, %g2
st %g0, [%g2] ! clear interrupt occured flag
! user event to generate MSI msg.
nop ! $EV trig_pc_d(1, @VA(.MAIN.gen_msi_user_event)) -> EnablePCIeIgCmd ("MSI32", 0, 0, 4, 1, *, 1 )
/* Wait for interrupt to occur. */
setx 0x2000, %g1, %g3 ! DTM timeout count
setx 0x800, %g1, %g3 ! timeout count
/* Have all the needed MSI's been generated? */
/* Did each thread get the correct number of interrupts */
setx interrupt_counts, %g1, %g2
/* Tell the other threads we're done. */
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! All Threads Except 0 Start Here
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
SYNC_THREAD_OTHER( %g6,%g1,%g2 )
/* Wait thread 0 to indicate we're done. */
setx 0x10000, %g1, %g2 ! DTM timeout count
setx 0x4000, %g1, %g2 ! timeout count
t1_t63_intr_wait_loop_top:
bne t1_t63_intr_wait_loop_top
/**********************************************************************
**********************************************************************/
ta T_RD_THID ! %o1 = thread id
! Check Mondo Interrupt Busy reg. for this thread
setx MONDO_INT_BUSY, %l1, %l2
setx MONDO_INT_BUSY_STEP, %l1, %l3
and %l4, 0x40, %l5 ! Is busy bit set?
! Check Mondo Interrupt Alias Busy reg.
setx MONDO_INT_ABUSY, %l1, %l2
cmp %l3, %l4 ! ABUSY = BUSY ?
! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1
setx MONDO_INT_DATA0, %l1, %l2
setx MONDO_INT_DATA0_STEP, %l1, %l3
ldx [%l2], %l0 ! %l0 = mondo_int_busy0
setx MONDO_INT_ADATA0, %l1, %l4 ! %l6 = mondo_int_abusy0, inc. INO
setx MONDO_INT_DATA1, %l1, %l2
setx MONDO_INT_DATA1_STEP, %l1, %l3
ldx [%l2], %l0 ! %l0 = mondo_int_busy1
setx MONDO_INT_ADATA1, %l1, %l4 ! %l5 = mondo_int_abusy1
! Is this the INO expected?
and %l6, 0x3f, %l6 ! %l6 = INO
sub %l6, 24, %l6 ! %l6 = event queue number
setx eq_num, %l1, %l2 ! Do NOT change %l6 until trap_inc_queue!
! Was the correct event queue used?
setx PCI_E_MSI_MAP_ADDR, %l1, %l2
! Check Mondo status in PIU
setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
set PCI_E_INT_CLEAR_STEP, %l3
cmp %l0, 3 ! Should be in pending state
setx PCI_E_MSI_MAP_ADDR, %l1, %l2
setx 0xc000000000000000, %l1, %l4 ! V = 1, EQWR_N = %l6
! Clear the Mondo interrupt in the PIU
setx PCI_E_MSI_CLEAR_ADDR, %l1, %l2
setx 0x4000000000000000, %l1, %l3
stx %l3, [%l2] ! clear EQWR in MSI map reg.
! Disable Event Queue via Control Clear reg.
setx PCI_E_EV_QUE_CTL_CLEAR_ADDR, %l1, %l2
set PCI_E_EV_QUE_CTL_CLEAR_STEP, %l4
setx 0x100000000000, %l1, %l3 ! DIS = 1
! Set Event Queue Head = Event Queue Tail
! Also check that they are not equal.
setx PCI_E_EV_QUE_TAIL_ADDR, %l1, %l2
set PCI_E_EV_QUE_TAIL_STEP, %l4
setx PCI_E_EV_QUE_HEAD_ADDR, %l1, %l2
set PCI_E_EV_QUE_HEAD_STEP, %l4
setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
set PCI_E_INT_CLEAR_STEP, %l3
! Clear the mondo interrupt in the NCU
setx MONDO_INT_ABUSY, %l0, %l1
cmp %l2, 0 ! Busy should be cleared
! Clear the interrupt in the core
ldxa [%g0]ASI_SWVR_INTR_R, %l5
cmp %l5, 63 ! check for correct vector number
! Set up to do relocation
! First are we done with the current event queue?
! Keep same event queue, but do the relocation,
! i.e. change thread interrupt is sent to.
! Go to the next event queue
! Initialize for the new event queue
setx PCI_E_MSI_MAP_ADDR, %l1, %l2
setx 0x8000000000000000, %l1, %l3 ! V = 1
or %l3, %l6, %l3 ! or in new event queue number
! Increment the thread to send the next interrupt to
setx PCI_E_INT_MAP_ADDR, %l1, %l5
set PCI_E_INT_MAP_STEP, %l1
add %l6, 4, %l7 ! index = event queue # + 4
setx 0x80000040, %l1, %l2 ! valid = 1, intr. controller #1
or %l2, %l4, %l2 ! or in destination thread id
setx PCI_E_EV_QUE_CTL_SET_ADDR, %l1, %l2
setx PCI_E_EV_QUE_CTL_SET_STEP, %l1, %l4
setx 0x100000000000, %l1, %l3 ! EN = 1
! Increment thread's interrupt count.
setx interrupt_counts, %l1, %l3
add %l7, %l3, %l7 ! %l7 = pointer to thread's interrupt count
! Flag that an interrupt occured
setx interrupt_flag, %l0, %l1
/************************************************************************
************************************************************************/
/* 1 word per thread to count number of interrupts taken */
/************************************************************************/