* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: tso_n2_ncrdwr3.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define ENABLE_PCIE_LINK_TRAINING
wr %g0, 0x4, %fprs /* make sure fef is 1 */
setx 0xc100beef00, %g1, %g3 ! MEM32 address space
setx user_data_start, %l0, %o0 ! user_data_start
! Now some NC writes and reads mixed with cacheable writes and reads
stx %g2, [%g3 + %g4] ! NonCacheable
stx %g2, [%o0 + %g4] ! Cacheable
ldx [%o0 + %g4], %g1 ! Cacheable
ldx [%g3 + %g4], %g1 ! NonCacheable
!================================
stda %f16, [%o0]ASI_BLK_P
!================================
!================================
stda %f0, [%o0]ASI_BLK_PL
stda %f0, [%o0]ASI_BLK_PL
stda %f0, [%o0]ASI_BLK_PL
!================================
stxa %l0, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
stxa %l1, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
!================================
stxa %l0, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE
stxa %l1, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE
!================================
stxa %l0, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
stxa %l1, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
/******************************************************************/