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* OpenSPARC T2 Processor File: interrupt0x60_sys_init.s.pal
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# $Id: interrupt0x60_sys_init.s.pal,v 1.9 2006/12/01 19:22:18 granvold Exp $
$hw_num_ivs = 64; $hw_max_ivn = $hw_num_ivs - 1;
$hw_num_threads = 64; $hw_max_thread_num = $hw_num_threads - 1;
# interrupt0x60 constraints:
$max_cc_ivns = 48; $max_cc_ivns_m1 = $max_cc_ivns - 1;
$max_niu_ivns = 16; $max_niu_ivns_m1 = $max_niu_ivns - 1;
$max_msi_idx = 8; $max_msi_idx_m1 = $max_msi_idx - 1;
/* Initialize system-wide interrupt-related registers (TT=0x60) */
/*>>>>>> ONLY EDIT THE .pal VERSION OF THIS FILE <<<<<<<<*/
* This is tightly linked with interrupt0x60_defines.h and
* interrupt0x60_handler.s
* The primary goal of this file is to take the -midas_args=-DINTR0x60_<xx>
* options (or #defines) and do the corresponding initialization
* of N2 registers. These macros are defined in interrupt0x60_defines.h
/* We need some cpp macros for NCU register addresses */
#if defined(INTR0x60_NIU_RX_IV_0) || defined(INTR0x60_NIU_TX_IV_0)
#endif /*defined(INTR0x60_NIU_RX_IV_0) || defined(INTR0x60_NIU_TX_IV_0)*/
ldxa [%g0] ASI_INTR_ID, %l7
and %l7, 0x38, %l7 ! %l7 = core ID, not thread ID
#if defined(INTR0x60_INITIALIZE_INT_MAN) || (INTR0x60_SSI_ERR_IV != INTR0x60_BAD_IV) || (INTR0x60_SSI_INT_IV != INTR0x60_BAD_IV)
! Initialize the Interrupt Management Registers
intr0x60_sys_init_int_man:
best_set_reg(INT_MAN, %l1, %l2) ! %l2 = INT_MAN reg. addr.
intr0x60_sys_init_int_man_0:
best_set_reg(mpeval((INTR0x60_BAD_THREAD<<8)+INTR0x60_BAD_IV), %l0, %l1)
or %l1, %l6, %l1 ! Use core ID of core running on
intr0x60_sys_init_int_man_ssi_err:
add %l2, INT_MAN_STEP, %l2
best_set_reg(mpeval((INTR0x60_SSI_ERR_THREAD<<8)+INTR0x60_SSI_ERR_IV),
or %l1, %l6, %l1 ! Use core ID of core running on
intr0x60_sys_init_enable_ssi_error_interrupts:
best_set_reg(SSI_TIMEOUT_ADDR, %l0, %l3)
best_set_reg(SSI_TIMEOUT_ERREN_MASK, %l0, %l1)
intr0x60_sys_init_int_man_ssi_int:
add %l2, INT_MAN_STEP, %l2
best_set_reg(mpeval((INTR0x60_SSI_INT_THREAD<<8)+INTR0x60_SSI_INT_IV),
or %l1, %l6, %l1 ! Use core ID of core running on
#endif /* INTR0x60_INITIALIZE_INT_MAN or SSI_ERR or SSI_INT */
>for ($ivn = 0; $ivn < $max_niu_ivns; $ivn++) {
#ifdef INTR0x60_NIU_RX_IV_${ivn}
intr0x60_sys_init_int_man_niu_rx_${ivn}:
best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_RX_IV_${ivn})*INT_MAN_STEP), %l1, %l2)
best_set_reg(mpeval((INTR0x60_NIU_RX_THREAD_${ivn}<<8)+INTR0x60_NIU_RX_IV_${ivn}),
#ifndef INTR0x60_NIU_RX_NO_SYS_INIT
! Initialize the NIU for RX DMA interrupt.
NIU_RX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_RX_DMA_${ivn},
INTR0x60_NIU_RX_IV_${ivn},
eval(64 + INTR0x60_NIU_RX_IV_${ivn}), %l5 )
#endif /* INTR0x60_NIU_RX_IV_${ivn} */
>for ($ivn = 0; $ivn < $max_niu_ivns; $ivn++) {
#ifdef INTR0x60_NIU_TX_IV_${ivn}
intr0x60_sys_init_int_man_niu_tx_${ivn}:
best_set_reg(mpeval(INT_MAN+(64+INTR0x60_NIU_TX_IV_${ivn})*INT_MAN_STEP), %l1, %l2)
best_set_reg(mpeval((INTR0x60_NIU_TX_THREAD_${ivn}<<8)+INTR0x60_NIU_TX_IV_${ivn}),
#ifndef INTR0x60_NIU_TX_NO_SYS_INIT
! Initialize the NIU for TX DMA interrupt.
NIU_TX_LD_IM0_INTR_ON_MARK( INTR0x60_NIU_TX_DMA_${ivn},
INTR0x60_NIU_TX_IV_${ivn},
eval(64 + INTR0x60_NIU_TX_IV_${ivn}) )
#endif /* INTR0x60_NIU_TX_NO_SYS_INIT */
#endif /* INTR0x60_NIU_TX_IV_${ivn} */
! Initialize Mondo Interrupt Vector Register
intr0x60_sys_init_mondo_int_vec:
best_set_reg(INTR0x60_MONDO_IV, %l2, %l1)
best_set_reg(INTR0x60_BAD_IV, %l2, %l1)
#endif /* INTR0x60_MONDO_IV */
best_set_reg(MONDO_INT_VEC, %l2, %l3)
/* Mondos come from PIU, so do the appropriate initialization */
/* Need some cpp macros for PIU registers */
intr0x60_sys_init_clear_intx:
>for $intx ("A", "B", "C", "D") {
best_set_reg(PCI_E_INT_${intx}_CLEAR_ADDR, %l1, %l2)
/* Clear the MSI registers, if any MSIs are being used */
#ifdef INTR0x60_MSI_0_NUM
intr0x60_sys_init_clear_msi:
sllx %l3, 62, %l3 ! EQWR_N is bit 62
best_set_reg(PCI_E_MSI_CLEAR_ADDR, %l1, %l2)
>for $idx (0 .. $max_msi_idx_m1) {
#ifdef INTR0x60_MSI_${idx}_NUM
intr0x60_sys_init_clear_msi_${idx}:
best_set_reg(mpeval(PCI_E_MSI_CLEAR_STEP*INTR0x60_MSI_${idx}_NUM),
#endif /* INTR0x60_MSI_${idx}_NUM */
#endif /* INTR0x60_MSI_0_NUM */
! Also clear in Interrupt Clear reg.
intr0x60_sys_init_piu_intr_clear:
best_set_reg(PCI_E_INT_CLEAR_ADDR, %l1, %l2)
mov PCI_E_INT_CLEAR_COUNT, %l3
intr0x60_sys_init_piu_intr_clear_loop_top:
brnz %l3,intr0x60_sys_init_piu_intr_clear_loop_top
add PCI_E_INT_CLEAR_STEP, %l2, %l2
/* WIP: Clear INO 62 and 63 */
/* Set up the Event Queues in PIU, if any are being used */
#ifdef INTR0x60_EVENT_QUEUE_BASE
intr0x60_sys_init_piu_eq_base_addr:
! First the Event Queue Base Address reg.
! Formatted for a bypass address.
best_set_reg(PCI_E_EV_QUE_BASE_ADDRESS_ADDR, %l1, %l2)
setx @PA(INTR0x60_EVENT_QUEUE_BASE), %l1, %l3
best_set_reg(0xfffc000000000000, %l1, %l6)
! Event Queue Control Set reg.
intr0x60_sys_init_piu_eq_ctl_set_en:
sllx %l3, 44, %l3 ! EN is bit 44
best_set_reg(PCI_E_EV_QUE_CTL_SET_ADDR, %l1, %l2)
>for $idx (0 .. $max_msi_idx_m1) {
#ifdef INTR0x60_MSI_${idx}_NUM
intr0x60_sys_init_piu_eq_ctl_set_en_${idx}:
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_MSI_${idx}_EQN),
#endif /* INTR0x60_MSI_${idx}_NUM */
#ifdef INTR0x60_PM_PME_EQN
intr0x60_sys_init_piu_eq_ctl_set_en_pm_pme:
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PM_PME_EQN),
#endif /* INTR0x60_PM_PME_EQN */
#ifdef INTR0x60_PME_TO_ACK_EQN
intr0x60_sys_init_piu_eq_ctl_set_en_pme_to_ack:
best_set_reg(mpeval(PCI_E_EV_QUE_CTL_SET_STEP*INTR0x60_PME_TO_ACK_EQN),
#endif /* INTR0x60_PME_TO_ACK_EQN */
#endif /* INTR0x60_EVENT_QUEUE_BASE */
#ifdef INTR0x60_MSI_START_ADDRESS
intr0x60_sys_init_piu_msi_addr:
best_set_reg(INTR0x60_MSI_START_ADDRESS, %l1, %l3)
best_set_reg(PCI_E_MSI_32_ADDRESS_ADDR, %l1, %l2)
best_set_reg(PCI_E_MSI_64_ADDRESS_ADDR, %l1, %l2)
! MSI-to-Event Queue Mapping registers
intr0x60_sys_init_piu_msi_mapping:
sllx %l3, 63, %l3 ! V is bit 63
best_set_reg(PCI_E_MSI_MAP_ADDR, %l1, %l2)
>for $idx (0 .. $max_msi_idx_m1) {
#ifdef INTR0x60_MSI_${idx}_NUM
intr0x60_sys_init_piu_msi_mapping_${idx}:
best_set_reg(mpeval(PCI_E_MSI_MAP_STEP*INTR0x60_MSI_${idx}_NUM),
best_set_reg(INTR0x60_MSI_${idx}_EQN, %l1, %l5)
#endif /* INTR0x60_MSI_${idx}_NUM */
#endif /* INTR0x60_MSI_START_ADDRESS */
#ifdef INTR0x60_PM_PME_EQN
! PM_PME-to-Event Queue Mapping registers
intr0x60_sys_init_piu_pm_pme_mapping:
sllx %l3, 63, %l3 ! V is bit 63
best_set_reg(PCI_E_PM_PME_MAP_ADDR, %l1, %l2)
best_set_reg(INTR0x60_PM_PME_EQN, %l1, %l5)
#endif /* INTR0x60_PM_PME_EQN */
#ifdef INTR0x60_PME_TO_ACK_EQN
! PME_TO_ACK-to-Event Queue Mapping registers
intr0x60_sys_init_piu_pme_to_ack_mapping:
sllx %l3, 63, %l3 ! V is bit 63
best_set_reg(PCI_E_PME_ACK_MAP_ADDR, %l1, %l2)
best_set_reg(INTR0x60_PME_TO_ACK_EQN, %l1, %l5)
#endif /* INTR0x60_PME_TO_ACK_EQN */
>for $mondo_num (20 .. 59, 62, 63) {
#if INTR0x60_MONDO_${mondo_num}_V || INTR0x60_INIT_ALL_PIU_INT_MAP
intr0x60_sys_init_piu_int_map_mondo_${mondo_num}:
best_set_reg(mpeval(PCI_E_INT_MAP_ADDR+PCI_E_INT_MAP_STEP*(${mondo_num}-20)),
best_set_reg(mpeval((INTR0x60_MONDO_${mondo_num}_MODE << PCI_E_INT_MAP_MDO_MODE_SHIFT)+
(INTR0x60_MONDO_${mondo_num}_V << PCI_E_INT_MAP_V_SHIFT)+
(INTR0x60_MONDO_${mondo_num}_THREAD << PCI_E_INT_MAP_THREADID_SHIFT)+
(1 << (INTR0x60_MONDO_${mondo_num}_CNTRL+PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT))),
sllx %l1, PCI_E_INT_MAP_THREADID_SHIFT, %l1
sllx %l7, PCI_E_INT_MAP_THREADID_SHIFT, %l1
or %l1, %l2, %l2 ! Use core ID of core running on
#endif /* INTR0x60_MONDO_${mondo_num}_V || INTR0x60_INIT_ALL_PIU_INT_MAP */
#endif /* INTR0x60_MONDO_IV */