* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: peu_init.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
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* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* choice is available it will apply instead, Sun elects to use only
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* ========== Copyright Header End ============================================
#define PEU_DEVICE_CNTRL_REG_ADDR FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR
#define PEU_DEVICE_CNTRL__MPS_128 0x00
#define PEU_DEVICE_CNTRL__MPS_256 0x20
#define PEU_DEVICE_CNTRL__MPS_512 0x40
! NonPosted Header Credit
- hw
default 0x10
#define PEU_NPH_CREDIT 0x10
#define PEU_SET_CREDITS 0
! Posted Header Credit
- hw
default 0x20. Changes must
satisfy (PEU_PH_CREDIT
+PEU_NPH_CREDIT
) <= 0x30
#define PEU_PH_CREDIT 0x20
#define PEU_SET_CREDITS 0
! Posted Data Credit
- hw
default 0xc0. Changes must be less than
0xc0
#define PEU_PD_CREDIT 0xc0
#define PEU_SET_CREDITS 0
! $EV
trig_pc_d(1, @
VA(.RED_EXT_SEC
.PEU_LINK_TRAINING_START
)) -> printf("\n\nIn peu_init.h\n")
! before doing link training
, set the Ingress Initial Credits
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_ADDR
, %g2
, %g3
setx
mpeval((PEU_NPH_CREDIT
<<32)|(PEU_PH_CREDIT
<<12)|(PEU_PD_CREDIT
)), %g2
, %g4
#ifdef ENABLE_PCIE_MPS_512
! before doing link training
, set the MPS to
512
setx PEU_DEVICE_CNTRL_REG_ADDR
, %g2
, %g3
mov PEU_DEVICE_CNTRL__MPS_512
, %g4
#ifdef ENABLE_PCIE_MPS_256
! before doing link training
, set the MPS to
256
setx PEU_DEVICE_CNTRL_REG_ADDR
, %g2
, %g3
mov PEU_DEVICE_CNTRL__MPS_256
, %g4
! before doing link training
, set the ACK_FREQ
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_ADDR
, %g2
, %g3
mov SET_PCIE_ACK_FREQ
, %g4
or %g4
, 1, %g4
! bit
0 defaults to
1 == data link layer enable
! The following registers must be initialized in the PEU to start Link Training.
! * FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL Reg to reset Detect.QuietilupeuScenario
! Following registers are optional.
! * FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL Reg to set FTS (Fast Training Sequence) to a smaller value
! * FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_RW1S_ALIAS_ADDR Set FTS (Fast Training Sequence) to a smaller value
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR
, %g2
, %g3
#ifdef PCI_NORMAL_LINK_INIT
mov
0x0000, %g5
! Mission
mode (normal
)
mov
0x0010, %g5
! FAST LINK MODE
, for simulation
.
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR
, %g2
, %g3
#ifndef PCIE_NPWR_EN_DISABLE
setx
mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_DATA
+0x00100000), %g2
, %g4
mov FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_DATA
, %g4
nop
! $EV
trig_pc_d(1, @
VA(.RED_EXT_SEC
.TrigPEUStart
)) -> set_StartPEUTest()
! Set up the Base
and Mask registers in the NCU to enable PIO reads
and writes
setx MEM32_OFFSET_BASE_REG_ADDR
, %g2
, %g3
! 0x8000002000
setx MEM32_OFFSET_BASE_REG_DATA
, %g2
, %g4
!setx MEM32_OFFSET_MASK_REG_ADDR
, %g2
, %g3
! 0x8000002008
setx MEM32_OFFSET_MASK_REG_DATA
, %g2
, %g4
!setx MEM64_OFFSET_BASE_REG_ADDR
, %g2
, %g3
! 0x8000002010
setx MEM64_OFFSET_BASE_REG_DATA
, %g2
, %g4
!setx MEM64_OFFSET_MASK_REG_ADDR
, %g2
, %g3
! 0x8000002018
setx MEM64_OFFSET_MASK_REG_DATA
, %g2
, %g4
!setx IOCFG_OFFSET_BASE_REG_ADDR
, %g2
, %g3
! 0x8000002020
setx IOCFG_OFFSET_BASE_REG_DATA
, %g2
, %g4
!setx IOCFG_OFFSET_MASK_REG_ADDR
, %g2
, %g3
! 0x8000002028
setx IOCFG_OFFSET_MASK_REG_DATA
, %g2
, %g4
! Load the PCIE MEM64 OFFSET
Register (and pio deadlock mode bits
)
setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR
, %g2
, %g3
#define PCIE_MEM64_OFFSET_PLUS_PIO_MODE PCIE_MEM64_OFFSET
#define PCIE_MEM64_OFFSET_PLUS_PIO_MODE mpeval(PCIE_MEM64_OFFSET | (PEU_PIO_MODE & 3))
setx PCIE_MEM64_OFFSET_PLUS_PIO_MODE
, %g2
, %g4
setx FIRE_DLC_MMU_CSR_A_CTL_ADDR
, %g2
, %g3
mov FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN
, %g4