* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: tlu_fcrand05_ind_14.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#define IMMU_SKIP_IF_NO_TTE
#define DMMU_SKIP_IF_NO_TTE
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define MAIN_PAGE_VA_IS_RA_ALSO
#define DISABLE_PART_LIMIT_CHECK
#define MAIN_PAGE_USE_CONFIG 3
#define PART0_Z_TSB_SIZE_3 10
#define PART0_Z_PAGE_SIZE_3 1
#define PART0_NZ_TSB_SIZE_3 10
#define PART0_NZ_PAGE_SIZE_3 1
#define PART0_Z_TSB_SIZE_1 3
#define PART0_NZ_TSB_SIZE_1 3
#define USER_PAGE_CUSTOM_MAP
#define MAIN_BASE_TEXT_VA 0x333000000
#define MAIN_BASE_TEXT_RA 0x033000000
#define MAIN_BASE_DATA_VA 0x379400000
#define MAIN_BASE_DATA_RA 0x079400000
#define H_HT0_Instruction_Access_MMU_Error_0x71 inst_access_mmu_error_handler
#define H_HT0_Instruction_access_error_0x0a inst_access_error_handler
#define H_HT0_Internal_Processor_Error_0x29 int_proc_err_handler
#define H_HT0_Data_Access_MMU_Error_0x72 data_access_mmu_error_handler
#define H_HT0_Data_access_error_0x32 data_access_error_handler
#define H_HT0_Hw_Corrected_Error_0x63 hw_corrected_error_handler
#define H_HT0_Sw_Recoverable_Error_0x40 sw_recoverable_error_handler
#define H_HT0_Store_Error_0x07 store_error_handler
#define DAE_SKIP_IF_SOCU_ERROR
# 5 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#ifndef T_HANDLER_RAND4_1
#define T_HANDLER_RAND4_1 b .+16;\
sdiv %r1, %r0, %l4;nop;nop
#ifndef T_HANDLER_RAND7_1
#define T_HANDLER_RAND7_1 b .+28;\
nop; nop ; nop; nop; illtrap
#ifndef T_HANDLER_RAND4_2
#define T_HANDLER_RAND4_2 save %i7, %g0, %i7; \
#ifndef T_HANDLER_RAND7_2
#define T_HANDLER_RAND7_2 b .+8 ;\
wrpr %l3, %r0, %tstate; nop
#ifndef T_HANDLER_RAND4_3
#define T_HANDLER_RAND4_3 save %i7, %g0, %i7;\
#ifndef T_HANDLER_RAND7_3
#define T_HANDLER_RAND7_3 b .+8 ;\
stda %f16,[%l2]ASI_BLOCK_AS_IF_USER_PRIMARY ;\
stda %f0,[%l2]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE ;
#ifndef T_HANDLER_RAND4_4
#define T_HANDLER_RAND4_4 b .+4 ; b .+4; b .+4; b .+4
#ifndef T_HANDLER_RAND7_4
#define T_HANDLER_RAND7_4 b .+8;\
#ifndef T_HANDLER_RAND4_5
#define T_HANDLER_RAND4_5 ldda [%r31]ASI_NUCLEUS_QUAD_LDD, %l4;\
stda %l4, [%l5]ASI_BLOCK_PRIMARY_LITTLE;
#ifndef T_HANDLER_RAND7_5
#define T_HANDLER_RAND7_5 save %i7, %g0, %i7;\
#ifndef T_HANDLER_RAND4_6
#define T_HANDLER_RAND4_6 ldda [%r31]ASI_BLOCK_AS_IF_USER_PRIMARY, %l2;\
stda %f0,[%l2]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE;
#ifndef T_HANDLER_RAND7_6
#define T_HANDLER_RAND7_6 umul %o4, 2, %o5;\
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#ifndef HT_HANDLER_RAND4_1
#define HT_HANDLER_RAND4_1 mov 0x80, %l3;\
#ifndef HT_HANDLER_RAND7_1
#define HT_HANDLER_RAND7_1 b .+28;\
nop; nop ; nop; nop; illtrap
#ifndef HT_HANDLER_RAND4_2
#define HT_HANDLER_RAND4_2 save %i7, %g0, %i7; \
#ifndef HT_HANDLER_RAND7_2
#define HT_HANDLER_RAND7_2 b .+8 ;\
wrhpr %l3, %r0, %htstate; nop
#ifndef HT_HANDLER_RAND4_3
#define HT_HANDLER_RAND4_3 stxa %l4, [%r31]ASI_AS_IF_USER_PRIMARY;\
ldxa [%r31]ASI_AS_IF_USER_PRIMARY, %l4;
#ifndef HT_HANDLER_RAND7_3
#define HT_HANDLER_RAND7_3 b .+8 ;\
stda %f16,[%l2]ASI_BLOCK_AS_IF_USER_PRIMARY ;\
stda %f0,[%l2]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE ;
#ifndef HT_HANDLER_RAND4_4
#define HT_HANDLER_RAND4_4 ldda [%i7]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE, %l3;\
stxa %l3, [%g0]ASI_LSU_CONTROL; nop
#ifndef HT_HANDLER_RAND7_4
#define HT_HANDLER_RAND7_4 rdpr %tnpc, %l3;\
mov ASI_DMMU_VA_WATCHPOINT_VAL, %l4 ;\
stxa %l3, [%l4]ASI_DMMU_VA_WATCHPOINT ;\
stxa %l3, [%g0]ASI_LSU_CONTROL;
#ifndef HT_HANDLER_RAND4_5
#define HT_HANDLER_RAND4_5 ldda [%r31]ASI_NUCLEUS_QUAD_LDD, %l4;\
stda %f32, [%r31]ASI_BLOCK_PRIMARY_LITTLE;
#ifndef HT_HANDLER_RAND7_5
#define HT_HANDLER_RAND7_5 save %i7, %g0, %i7;\
#ifndef HT_HANDLER_RAND4_6
#define HT_HANDLER_RAND4_6 ld [%r31], %l2;\
stda %f0,[%l2]ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE;
#ifndef HT_HANDLER_RAND7_6
#define HT_HANDLER_RAND7_6 rdhpr %htstate, %o4;\
wrhpr %o4, %r0, %htstate;\
!!!!!!!!!!!!!!!!!!!!!!!!!
#define ENABLE_T1_Privileged_Opcode_0x11
#define ENABLE_T1_Fp_Disabled_0x20
#define ENABLE_HT0_Watchdog_Reset_0x02
#define My_RED_Mode_Other_Reset
#define My_RED_Mode_Other_Reset \
nop;retry;nop;nop;nop;nop;nop
#define H_HT0_Software_Initiated_Reset_0x04
#define SUN_H_HT0_Software_Initiated_Reset_0x04 \
setx Software_Reset_Handler, %g1, %g2 ;\
# 198 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_T1_Clean_Window_0x24
#define SUN_H_T1_Clean_Window_0x24 \
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
#define H_T1_Clean_Window_0x25
#define SUN_H_T1_Clean_Window_0x25 \
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
#define H_T1_Clean_Window_0x26
#define SUN_H_T1_Clean_Window_0x26 \
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
#define H_T1_Clean_Window_0x27
#define SUN_H_T1_Clean_Window_0x27 \
wrpr %l1, %g0, %cleanwin;\
retry; nop; nop; nop; nop
# 227 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_Tag_Overflow
#define My_HT0_Tag_Overflow \
#define H_T0_Tag_Overflow
#define My_T0_Tag_Overflow \
#define H_T1_Tag_Overflow_0x23
#define SUN_H_T1_Tag_Overflow_0x23 \
#define H_T0_Window_Spill_0_Normal_Trap
#define SUN_H_T0_Window_Spill_0_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_1_Normal_Trap
#define SUN_H_T0_Window_Spill_1_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_2_Normal_Trap
#define SUN_H_T0_Window_Spill_2_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_3_Normal_Trap
#define SUN_H_T0_Window_Spill_3_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_4_Normal_Trap
#define SUN_H_T0_Window_Spill_4_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_5_Normal_Trap
#define SUN_H_T0_Window_Spill_5_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_6_Normal_Trap
#define SUN_H_T0_Window_Spill_6_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_7_Normal_Trap
#define SUN_H_T0_Window_Spill_7_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_0_Other_Trap
#define SUN_H_T0_Window_Spill_0_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_1_Other_Trap
#define SUN_H_T0_Window_Spill_1_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_2_Other_Trap
#define SUN_H_T0_Window_Spill_2_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_3_Other_Trap
#define SUN_H_T0_Window_Spill_3_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_4_Other_Trap
#define SUN_H_T0_Window_Spill_4_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_5_Other_Trap
#define SUN_H_T0_Window_Spill_5_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_6_Other_Trap
#define SUN_H_T0_Window_Spill_6_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Spill_7_Other_Trap
#define SUN_H_T0_Window_Spill_7_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_0_Normal_Trap
#define SUN_H_T0_Window_Fill_0_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_1_Normal_Trap
#define SUN_H_T0_Window_Fill_1_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_2_Normal_Trap
#define SUN_H_T0_Window_Fill_2_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_3_Normal_Trap
#define SUN_H_T0_Window_Fill_3_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_4_Normal_Trap
#define SUN_H_T0_Window_Fill_4_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_5_Normal_Trap
#define SUN_H_T0_Window_Fill_5_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_6_Normal_Trap
#define SUN_H_T0_Window_Fill_6_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_7_Normal_Trap
#define SUN_H_T0_Window_Fill_7_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_0_Other_Trap
#define SUN_H_T0_Window_Fill_0_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_1_Other_Trap
#define SUN_H_T0_Window_Fill_1_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_2_Other_Trap
#define SUN_H_T0_Window_Fill_2_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_3_Other_Trap
#define SUN_H_T0_Window_Fill_3_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_4_Other_Trap
#define SUN_H_T0_Window_Fill_4_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_5_Other_Trap
#define SUN_H_T0_Window_Fill_5_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_6_Other_Trap
#define SUN_H_T0_Window_Fill_6_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Window_Fill_7_Other_Trap
#define SUN_H_T0_Window_Fill_7_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
# 339 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_T1_Window_Spill_0_Normal_Trap
#define SUN_H_T1_Window_Spill_0_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_1_Normal_Trap
#define SUN_H_T1_Window_Spill_1_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_2_Normal_Trap
#define SUN_H_T1_Window_Spill_2_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_3_Normal_Trap
#define SUN_H_T1_Window_Spill_3_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_4_Normal_Trap
#define SUN_H_T1_Window_Spill_4_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_5_Normal_Trap
#define SUN_H_T1_Window_Spill_5_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_6_Normal_Trap
#define SUN_H_T1_Window_Spill_6_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_7_Normal_Trap
#define SUN_H_T1_Window_Spill_7_Normal_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_0_Other_Trap
#define SUN_H_T1_Window_Spill_0_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_1_Other_Trap
#define SUN_H_T1_Window_Spill_1_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_2_Other_Trap
#define SUN_H_T1_Window_Spill_2_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_3_Other_Trap
#define SUN_H_T1_Window_Spill_3_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_4_Other_Trap
#define SUN_H_T1_Window_Spill_4_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_5_Other_Trap
#define SUN_H_T1_Window_Spill_5_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_6_Other_Trap
#define SUN_H_T1_Window_Spill_6_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Spill_7_Other_Trap
#define SUN_H_T1_Window_Spill_7_Other_Trap saved; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_0_Normal_Trap
#define SUN_H_T1_Window_Fill_0_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_1_Normal_Trap
#define SUN_H_T1_Window_Fill_1_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_2_Normal_Trap
#define SUN_H_T1_Window_Fill_2_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_3_Normal_Trap
#define SUN_H_T1_Window_Fill_3_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_4_Normal_Trap
#define SUN_H_T1_Window_Fill_4_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_5_Normal_Trap
#define SUN_H_T1_Window_Fill_5_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_6_Normal_Trap
#define SUN_H_T1_Window_Fill_6_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_7_Normal_Trap
#define SUN_H_T1_Window_Fill_7_Normal_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_0_Other_Trap
#define SUN_H_T1_Window_Fill_0_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_1_Other_Trap
#define SUN_H_T1_Window_Fill_1_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_2_Other_Trap
#define SUN_H_T1_Window_Fill_2_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_3_Other_Trap
#define SUN_H_T1_Window_Fill_3_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_4_Other_Trap
#define SUN_H_T1_Window_Fill_4_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_5_Other_Trap
#define SUN_H_T1_Window_Fill_5_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_6_Other_Trap
#define SUN_H_T1_Window_Fill_6_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T1_Window_Fill_7_Other_Trap
#define SUN_H_T1_Window_Fill_7_Other_Trap restored; retry; nop;nop;nop;nop;nop;nop;
#define H_T0_Trap_Instruction_0
#define My_T0_Trap_Instruction_0 \
#define H_T0_Trap_Instruction_1
#define My_T0_Trap_Instruction_1 \
#define H_T0_Trap_Instruction_2
#define My_T0_Trap_Instruction_2 \
#define H_T0_Trap_Instruction_3
#define My_T0_Trap_Instruction_3 \
#define H_T0_Trap_Instruction_4
#define My_T0_Trap_Instruction_4 \
#define H_T0_Trap_Instruction_5
#define My_T0_Trap_Instruction_5 \
#define H_T1_Trap_Instruction_0
#define My_T1_Trap_Instruction_0 \
#define H_T1_Trap_Instruction_1
#define My_T1_Trap_Instruction_1 \
#define H_T1_Trap_Instruction_2
#define My_T1_Trap_Instruction_2 \
#define H_T1_Trap_Instruction_3
#define My_T1_Trap_Instruction_3 \
#define H_T1_Trap_Instruction_4
#define My_T1_Trap_Instruction_4 \
#define H_T1_Trap_Instruction_5
#define My_T1_Trap_Instruction_5 \
#define H_HT0_Trap_Instruction_0
#define My_HT0_Trap_Instruction_0 \
#define H_HT0_Trap_Instruction_1
#define My_HT0_Trap_Instruction_1 \
#define H_HT0_Trap_Instruction_2
#define My_HT0_Trap_Instruction_2 \
#define H_HT0_Trap_Instruction_3
#define My_HT0_Trap_Instruction_3 \
#define H_HT0_Trap_Instruction_4
#define My_HT0_Trap_Instruction_4 \
#define H_HT0_Trap_Instruction_5
#define My_HT0_Trap_Instruction_5 \
#define H_HT0_Mem_Address_Not_Aligned_0x34
#define My_HT0_Mem_Address_Not_Aligned_0x34 \
#define H_HT0_Illegal_instruction_0x10
#define My_HT0_Illegal_instruction_0x10 \
#define H_HT0_DAE_so_page_0x30
#define My_HT0_DAE_so_page_0x30 \
#define H_HT0_DAE_invalid_asi_0x14
#define SUN_H_HT0_DAE_invalid_asi_0x14 \
#define H_HT0_DAE_privilege_violation_0x15
#define SUN_H_HT0_DAE_privilege_violation_0x15 \
#define H_HT0_Privileged_Action_0x37
#define My_HT0_Privileged_Action_0x37 \
#define H_HT0_Lddf_Mem_Address_Not_Aligned_0x35
#define My_HT0_Lddf_Mem_Address_Not_Aligned_0x35 \
#define H_HT0_Stdf_Mem_Address_Not_Aligned_0x36
#define My_HT0_Stdf_Mem_Address_Not_Aligned_0x36 \
#define H_HT0_Fp_exception_ieee_754_0x21
#define My_HT0_Fp_exception_ieee_754_0x21 \
#define H_HT0_Fp_exception_other_0x22
#define My_HT0_Fp_exception_other_0x22 \
#define H_HT0_Division_By_Zero
#define My_HT0_Division_By_Zero \
#define H_T0_Division_By_Zero
#define My_T0_Division_By_Zero \
#define H_T1_Division_By_Zero_0x28
#define My_H_T1_Division_By_Zero_0x28 \
#define H_T0_Division_By_Zero
#define My_T0_Division_By_Zero\
#define H_T0_Fp_exception_ieee_754_0x21
#define My_T0_Fp_exception_ieee_754_0x21 \
#define H_T1_Fp_Exception_Ieee_754_0x21
#define My_H_T1_Fp_Exception_Ieee_754_0x21 \
#define H_T1_Fp_Exception_Other_0x22
#define My_H_T1_Fp_Exception_Other_0x22 \
#define H_T1_Privileged_Opcode_0x11
#define SUN_H_T1_Privileged_Opcode_0x11 \
#define H_HT0_Privileged_opcode_0x11
#define My_HT0_Privileged_opcode_0x11 \
#define H_HT0_Fp_disabled_0x20
#define My_HT0_Fp_disabled_0x20 \
#define H_T0_Fp_disabled_0x20
#define My_T0_Fp_disabled_0x20 \
#define H_T1_Fp_Disabled_0x20
#define My_H_T1_Fp_Disabled_0x20 \
#define H_HT0_Watchdog_Reset_0x02
#define My_HT0_Watchdog_Reset_0x02 \
nop;retry;nop;nop;nop;nop;nop
#define H_T0_Privileged_opcode_0x11
#define My_T0_Privileged_opcode_0x11 \
#define H_T1_Fp_exception_other_0x22
#define My_T1_Fp_exception_other_0x22 \
#define H_T0_Fp_exception_other_0x22
#define My_T0_Fp_exception_other_0x22 \
#define H_HT0_Trap_Level_Zero_0x5f
#define My_HT0_Trap_Level_Zero_0x5f \
#define My_Watchdog_Reset
#define My_Watchdog_Reset \
nop;retry;nop;nop;nop;nop;nop
#define H_HT0_Control_Transfer_Instr_0x74
#define My_H_HT0_Control_Transfer_Instr_0x74 \
wrpr %l3, %l4, %tstate ;\
#define H_T0_Control_Transfer_Instr_0x74
#define My_H_T0_Control_Transfer_Instr_0x74 \
wrpr %l3, %l4, %tstate ;\
#define H_T1_Control_Transfer_Instr_0x74
#define My_H_T1_Control_Transfer_Instr_0x74 \
wrpr %l3, %l4, %tstate ;\
# 707 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_data_access_protection_0x6c
#define SUN_H_HT0_data_access_protection_0x6c ba daccess_prot_handler; nop
#define H_HT0_PA_Watchpoint_0x61
#define My_H_HT0_PA_Watchpoint_0x61 \
#define H_HT0_Data_access_error_0x32
#define SUN_H_HT0_Data_access_error_0x32 \
#define H_T0_VA_Watchpoint_0x62
#define My_T0_VA_Watchpoint_0x62 \
#define H_T1_VA_Watchpoint_0x62
#define SUN_H_T1_VA_Watchpoint_0x62 \
#define H_HT0_VA_Watchpoint_0x62
#define My_H_HT0_VA_Watchpoint_0x62 \
#define H_T0_Instruction_VA_Watchpoint_0x75
#define SUN_H_T0_Instruction_VA_Watchpoint_0x75 \
#define H_T1_Instruction_VA_Watchpoint_0x75
#define SUN_H_T1_Instruction_VA_Watchpoint_0x75 \
#define H_HT0_Instruction_VA_Watchpoint_0x75
#define SUN_H_HT0_Instruction_VA_Watchpoint_0x75 \
#define H_HT0_Instruction_Breakpoint_0x76
#define SUN_H_HT0_Instruction_Breakpoint_0x76 \
wrhpr %g1, 0x400, %htstate;\
# 756 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_Instruction_address_range_0x0d
#define SUN_H_HT0_Instruction_address_range_0x0d \
#define H_HT0_mem_real_range_0x2d
#define SUN_H_HT0_mem_real_range_0x2d \
# 767 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_mem_address_range_0x2e
#define SUN_H_HT0_mem_address_range_0x2e \
#define H_HT0_DAE_nc_page_0x16
#define SUN_H_HT0_DAE_nc_page_0x16 \
#define H_HT0_DAE_nfo_page_0x17
#define SUN_H_HT0_DAE_nfo_page_0x17 \
# 783 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_IAE_unauth_access_0x0b
#define SUN_H_HT0_IAE_unauth_access_0x0b \
# 789 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_IAE_nfo_page_0x0c
#define SUN_H_HT0_IAE_nfo_page_0x0c \
# 795 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_Reserved_0x3b
#define SUN_H_HT0_Reserved_0x3b \
# 805 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
#define H_HT0_IAE_privilege_violation_0x08
#define My_HT0_IAE_privilege_violation_0x08 \
#define H_HT0_Instruction_Access_MMU_Error_0x71
#define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \
#define H_HT0_Data_Access_MMU_Error_0x72
#define SUN_H_HT0_Data_Access_MMU_Error_0x72 \
# 825 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_handlers.s"
!!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!!
# 12 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!! START of Interrupt Handlers !!!!!!!!!!!!!!!!!
#ifndef INT_HANDLER_RAND4_1
#define INT_HANDLER_RAND4_1 retry; nop; nop; nop
#ifndef INT_HANDLER_RAND7_1
#define INT_HANDLER_RAND7_1 mov 0x20,%g1; mov 1, %g2;stxa %g2,[%g1]0x40
#ifndef INT_HANDLER_RAND4_2
#define INT_HANDLER_RAND4_2 retry; nop; nop; nop
#ifndef INT_HANDLER_RAND7_2
#define INT_HANDLER_RAND7_2 mov 0x80,%g1;stxa %g0,[%g1]0x40
#ifndef INT_HANDLER_RAND4_3
#define INT_HANDLER_RAND4_3 retry; nop; nop; nop
#ifndef INT_HANDLER_RAND7_3
#define INT_HANDLER_RAND7_3 retry; nop; nop; nop ; nop; nop; nop
#define H_HT0_Externally_Initiated_Reset_0x03
#define SUN_H_HT0_Externally_Initiated_Reset_0x03 \
ldxa [%g0] ASI_LSU_CTL_REG, %g1; \
set cregs_lsu_ctl_reg_r64, %g1; \
stxa %g1, [%g0] ASI_LSU_CTL_REG; \
#define My_External_Reset \
ldxa [%g0] ASI_LSU_CTL_REG, %l5; \
set cregs_lsu_ctl_reg_r64, %l5; \
stxa %l5, [%g0] ASI_LSU_CTL_REG; \
!!!!! SPU Interrupt Handlers
#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
#define H_HT0_Modular_Arithmetic_Interrupt_0x3d
#define My_H_HT0_Modular_Arithmetic_Interrupt_0x3d \
# 59 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
!!!!! HW interrupt handlers
#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g5 ;\
ldxa [%g0] ASI_SWVR_INTR_R, %g4 ;\
ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g3 ;\
!!!!! Queue interrupt handler
# 72 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
#define H_T0_Cpu_Mondo_Trap_0x7c
#define My_T0_Cpu_Mondo_Trap_0x7c \
#define H_T0_Dev_Mondo_Trap_0x7d
#define My_T0_Dev_Mondo_Trap_0x7d \
#define H_T0_Resumable_Error_0x7e
#define My_T0_Resumable_Error_0x7e \
#define H_T1_Cpu_Mondo_Trap_0x7c
#define My_T1_Cpu_Mondo_Trap_0x7c \
#define H_T1_Dev_Mondo_Trap_0x7d
#define My_T1_Dev_Mondo_Trap_0x7d \
#define H_T1_Resumable_Error_0x7e
#define My_T1_Resumable_Error_0x7e \
#define H_HT0_Reserved_0x7c
#define SUN_H_HT0_Reserved_0x7c \
#define H_HT0_Reserved_0x7d
#define SUN_H_HT0_Reserved_0x7d \
#define H_HT0_Reserved_0x7e
#define SUN_H_HT0_Reserved_0x7e \
# 172 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
!!!!! Hstick-match trap handler
# 175 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
#define H_T0_Reserved_0x5e
#define My_T0_Reserved_0x5e \
wrhpr %g3, %g3, %hintp; \
#define H_HT0_Hstick_Match_0x5e
#define My_HT0_Hstick_Match_0x5e \
wrhpr %g3, %g3, %hintp; \
#define H_T0_Reserved_0x5e
#define My_T0_Reserved_0x5e \
wrhpr %g3, %g3, %hintp; \
#define H_T1_Reserved_0x5e
#define My_T1_Reserved_0x5e \
wrhpr %g3, %g3, %hintp; \
# 220 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
!!!!! SW interuupt handlers
# 223 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
#define H_T0_Interrupt_Level_14_0x4e
#define My_T0_Interrupt_Level_14_0x4e \
sethi %hi(0x14000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_1_0x41
#define My_T0_Interrupt_Level_1_0x41 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_2_0x42
#define My_T0_Interrupt_Level_2_0x42 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_3_0x43
#define My_T0_Interrupt_Level_3_0x43 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_4_0x44
#define My_T0_Interrupt_Level_4_0x44 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_5_0x45
#define My_T0_Interrupt_Level_5_0x45 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_6_0x46
#define My_T0_Interrupt_Level_6_0x46 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_7_0x47
#define My_T0_Interrupt_Level_7_0x47 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_8_0x48
#define My_T0_Interrupt_Level_8_0x48 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_9_0x49
#define My_T0_Interrupt_Level_9_0x49 \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_10_0x4a
#define My_T0_Interrupt_Level_10_0x4a \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_11_0x4b
#define My_T0_Interrupt_Level_11_0x4b \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_12_0x4c
#define My_T0_Interrupt_Level_12_0x4c \
sethi %hi(0x1000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_13_0x4d
#define My_T0_Interrupt_Level_13_0x4d \
sethi %hi(0x2000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_T0_Interrupt_Level_15_0x4f
#define My_T0_Interrupt_Level_15_0x4f \
sethi %hi(0x8000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_14_0x4e
#define My_T1_Interrupt_Level_14_0x4e \
sethi %hi(0x14000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_1_0x41
#define My_T1_Interrupt_Level_1_0x41 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_2_0x42
#define My_T1_Interrupt_Level_2_0x42 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_3_0x43
#define My_T1_Interrupt_Level_3_0x43 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_4_0x44
#define My_T1_Interrupt_Level_4_0x44 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_5_0x45
#define My_T1_Interrupt_Level_5_0x45 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_6_0x46
#define My_T1_Interrupt_Level_6_0x46 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_7_0x47
#define My_T1_Interrupt_Level_7_0x47 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_8_0x48
#define My_T1_Interrupt_Level_8_0x48 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_9_0x49
#define My_T1_Interrupt_Level_9_0x49 \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_10_0x4a
#define My_T1_Interrupt_Level_10_0x4a \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_11_0x4b
#define My_T1_Interrupt_Level_11_0x4b \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_12_0x4c
#define My_T1_Interrupt_Level_12_0x4c \
sethi %hi(0x1000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_13_0x4d
#define My_T1_Interrupt_Level_13_0x4d \
sethi %hi(0x2000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_T1_Interrupt_Level_15_0x4f
#define My_T1_Interrupt_Level_15_0x4f \
sethi %hi(0x8000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_14_0x4e
#define My_HT0_Interrupt_Level_14_0x4e \
sethi %hi(0x14000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_1_0x41
#define My_HT0_Interrupt_Level_1_0x41 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_2_0x42
#define My_HT0_Interrupt_Level_2_0x42 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_3_0x43
#define My_HT0_Interrupt_Level_3_0x43 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_4_0x44
#define My_HT0_Interrupt_Level_4_0x44 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_5_0x45
#define My_HT0_Interrupt_Level_5_0x45 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_6_0x46
#define My_HT0_Interrupt_Level_6_0x46 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_7_0x47
#define My_HT0_Interrupt_Level_7_0x47 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_8_0x48
#define My_HT0_Interrupt_Level_8_0x48 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_9_0x49
#define My_HT0_Interrupt_Level_9_0x49 \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_10_0x4a
#define My_HT0_Interrupt_Level_10_0x4a \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_11_0x4b
#define My_HT0_Interrupt_Level_11_0x4b \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_12_0x4c
#define My_HT0_Interrupt_Level_12_0x4c \
sethi %hi(0x1000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_13_0x4d
#define My_HT0_Interrupt_Level_13_0x4d \
sethi %hi(0x2000), %g3; \
wr %g3, %g0, %clear_softint; \
#define H_HT0_Interrupt_Level_15_0x4f
#define My_HT0_Interrupt_Level_15_0x4f \
sethi %hi(0x8000), %g3; \
wr %g3, %g0, %clear_softint; \
# 713 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_intr_handlers.s"
!!!!!!!!!!!!!!!!!!!!!! END of all handlers !!!!!!!!!!!!!!!!!!!
!# Steer towards main TBA on these errors ..
!# These are redefines ...
#undef SUN_H_HT0_DAE_nc_page_0x16
#define SUN_H_HT0_DAE_nc_page_0x16 \
best_set_reg(0x120000, %r1, %r2);\
#undef SUN_H_HT0_DAE_nfo_page_0x17
#define SUN_H_HT0_DAE_nfo_page_0x17 \
best_set_reg(0x120000, %r1, %r2);\
#undef SUN_H_HT0_IAE_unauth_access_0x0b
#define SUN_H_HT0_IAE_unauth_access_0x0b \
set resolve_bad_tte, %g3;\
#undef My_HT0_IAE_privilege_violation_0x08
#define My_HT0_IAE_privilege_violation_0x08 \
set resolve_bad_tte, %g3;\
#define H_HT0_Instruction_address_range_0x0d
#define SUN_H_HT0_Instruction_address_range_0x0d \
#define H_HT0_Instruction_real_range_0x0e
#define SUN_H_HT0_Instruction_real_range_0x0e \
#undef SUN_H_HT0_IAE_nfo_page_0x0c
#define SUN_H_HT0_IAE_nfo_page_0x0c \
set resolve_bad_tte, %g3;\
#define H_HT0_Instruction_Invalid_TSB_Entry_0x2a
#define SUN_H_HT0_Instruction_Invalid_TSB_Entry_0x2a \
set restore_range_regs, %g3;\
#define H_HT0_Data_Invalid_TSB_Entry_0x2b
#define SUN_H_HT0_Data_Invalid_TSB_Entry_0x2b \
set restore_range_regs, %g3;\
#define LOMEIN_TEXT_VA [0x]mpeval(MAIN_BASE_TEXT_VA&0xffffffff,16)
#define LOMEIN_DATA_VA [0x]mpeval(MAIN_BASE_DATA_VA&0xffffffff,16)
SECTION .LOMEIN TEXT_VA=LOMEIN_TEXT_VA, DATA_VA=LOMEIN_DATA_VA
PA= ra2pa2(MAIN_BASE_TEXT_RA, 0),
part_0_ctx_nonzero_tsb_config_1,
part_0_ctx_zero_tsb_config_1,
TTE_G=1, TTE_Context=0x44, TTE_V=1,
TTE_Size=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=1,
PA= ra2pa2(MAIN_BASE_DATA_RA, 0),
part_0_ctx_nonzero_tsb_config_2,
part_0_ctx_zero_tsb_config_2
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
PA= ra2pa2(MAIN_BASE_DATA_RA, 0),
part_0_ctx_nonzero_tsb_config_3,
part_0_ctx_zero_tsb_config_3
TTE_G=1, TTE_Context=0x55, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
SECTION .MAIN TEXT_VA=MAIN_BASE_TEXT_VA, DATA_VA=MAIN_BASE_DATA_VA
part_0_ctx_nonzero_tsb_config_2,
part_0_ctx_zero_tsb_config_2,
TTE_G=1, TTE_Context=0x44, TTE_V=1,
TTE_Size=0, TTE_NFO=0, TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=1,
part_0_ctx_nonzero_tsb_config_1,
part_0_ctx_zero_tsb_config_1
TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
part_0_ctx_nonzero_tsb_config_3,
part_0_ctx_zero_tsb_config_3
TTE_G=1, TTE_Context=0x55, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1, TTE_X=0,
! Set up ld/st area per thread
set sync_thr_counter4, %r23
add %o2,%r23,%r23 !Core's sync counter
st %r10, [%r23] !lock sync_thr_counter4
st %r10, [%r23] !lock sync_thr_counter5
st %r10, [%r23] !lock sync_thr_counter6
setx user_data_start, %r1, %r3
!Initializing integer registers
!Initializing float registers
!! Set TPC/TNPC to diag-finish in case we get to a strange TL ..
setx diag_finish, %r29, %r28
wrhpr %g1, %g0, %hsys_tick_cmpr
wr %g1, %g0, %sys_tick_cmpr
lduw [%r27], %r12 ! load jmp dest into dcache - xinval
.word 0xe1e7c020 ! 1: CASA_I casa [%r31] 0x 1, %r0, %r16
! fork: source strm = 0xffffffff; target strm = 0x1
setx fork_lbl_0_1, %g2, %g3
! fork: source strm = 0xffffffff; target strm = 0x2
setx fork_lbl_0_2, %g2, %g3
! fork: source strm = 0xffffffff; target strm = 0x4
setx fork_lbl_0_3, %g2, %g3
! fork: source strm = 0xffffffff; target strm = 0x8
setx fork_lbl_0_4, %g2, %g3
! fork: source strm = 0xffffffff; target strm = 0x10
setx fork_lbl_0_5, %g2, %g3
! fork: source strm = 0xffffffff; target strm = 0x20
setx fork_lbl_0_6, %g2, %g3
! fork: source strm = 0xffffffff; target strm = 0x40
setx fork_lbl_0_7, %g2, %g3
! fork: source strm = 0xffffffff; target strm = 0x80
setx fork_lbl_0_8, %g2, %g3
setx join_lbl_0_0, %g1, %g2
setx join_lbl_0_0, %g1, %g2
setx 0xf13299d55c29e179, %r1, %r28
!# allocate control word queue (e.g., setup head/tail/first/last registers)
sllx %o2, 5, %o2 !(CID*256)
!# write base addr to first, head, and tail ptr
stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi !# first store to first
stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi !# then to head
stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi !# then to tail
setx CWQ_LAST, %g1, %l5 !# then end of CWQ region to LAST
stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
!# set CWQ control word ([38:36] is strand ID ..)
best_set_reg(0x20610080, %l1, %l2) !# Control Word
!# write CWQ entry (%l6 points to CWQ)
stx %l2, [%l6 + 0x8] !# source address
stx %g0, [%l6 + 0x10] !# Authentication Key Address (40-bit)
stx %g0, [%l6 + 0x18] !# Authentication IV Address (40-bit)
stx %g0, [%l6 + 0x20] !# Authentication FSAS Address (40-bit)
stx %g0, [%l6 + 0x28] !# Encryption Key Address (40-bit)
stx %g0, [%l6 + 0x30] !# Encryption Initialization Vector Address (40-bit)
stx %o3, [%l6 + 0x38] !# Destination Address (40-bit)
ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
!# Kick off the CWQ operation by writing to the CWQ_CSR
!# Set the enabled bit and reset the other bits
stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
set sync_thr_counter6, %r23
st %r0, [%r23] !unlock sync_thr_counter6
st %r0, [%r23] !unlock sync_thr_counter5
st %r0, [%r23] !unlock sync_thr_counter4
.word 0xe08008a0 ! 1: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0xc19fdb60 ! 2: LDDFA_R ldda [%r31, %r0], %f0
.word 0xe08008a0 ! 3: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
best_set_reg(0x08907a7c00148dad, %r16, %r17)
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802000 ! 5: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x3c800001 ! 1: BPOS bpos,a <label_0x1>
.word 0x8d903e69 ! 6: WRPR_PSTATE_I wrpr %r0, 0x1e69, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_2) + 56, 16, 16)) -> intp(1,0,3)
setx 0x432e45b2dc93ee70, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa7814014 ! 12: WR_GRAPHICS_STATUS_REG_R wr %r5, %r20, %-
setx fp_data_quads, %r19, %r20
.word 0x89a009c4 ! 13: FDIVd fdivd %f0, %f4, %f4
.word 0x91d0001e ! 14: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x879cc012 ! 15: WRHPR_HINTP_R wrhpr %r19, %r18, %hintp
.word 0xa57035a9 ! 16: POPC_I popc 0x15a9, %r18
.word 0x8780208b ! 17: WRASI_I wr %r0, 0x008b, %asi
.word 0x93b507d1 ! 18: PDIST pdistn %d20, %d48, %d40
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
sllx %r9, %r8, %r9 ! My core mask
xor %r9, 0x80, %r9 ! My core mask
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_80_7
ldxa [0x50]%asi, %r13 !Running_rw
brnz,a %r10, cmp_wait80_7
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
brz,a %r8, cmp_multi_core_80_7
best_set_reg(0x2f9dc727bdfca641, %r16, %r17)
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
st %g0, [%r23] !clear lock
.word 0x97a0016d ! 19: FABSq dis not found
.word 0xe49fe148 ! 20: LDDA_I ldda [%r31, + 0x0148] %asi, %r18
.word 0xe44fe0e8 ! 21: LDSB_I ldsb [%r31 + 0x00e8], %r18
.word 0x8584f0be ! 22: WRCCR_I wr %r19, 0x10be, %ccr
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x9b414000 ! 24: RDPC rd %pc, %r13
.word 0x8d903a57 ! 25: WRPR_PSTATE_I wrpr %r0, 0x1a57, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa1702070 ! 1: POPC_I popc 0x0070, %r16
.word 0x9f8026ea ! 26: SIR sir 0x06ea
setx 0x459b80f9c8d5f9e2, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xb3800011 ! 29: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7d1 ! 1: PDIST pdistn %d62, %d48, %d20
.word 0x9f80260a ! 30: SIR sir 0x060a
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_18
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_18
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_18
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x0000004032c000e5,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xd0bfc031 ! 33: STDA_R stda %r8, [%r31 + %r17] 0x01
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e148 ! 35: LDSWA_I ldswa [%r31, + 0x0148] %asi, %r8
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_19
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_19
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_19
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050a5c0e5b7,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xc32fc008 ! 36: STXFSR_R st-sfr %f1, [%r8, %r31]
.word 0xb3800011 ! 37: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xc19fe1a0 ! 38: LDDFA_I ldda [%r31, 0x01a0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610080, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa7414000 ! 39: RDPC rd %pc, %r19
.word 0xa5a4c9c1 ! 40: FDIVd fdivd %f50, %f32, %f18
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0x97508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe098 ! 43: LDXA_I ldxa [%r31, + 0x0098] %asi, %r19
.word 0xc3ec402a ! 44: PREFETCHA_R prefetcha [%r17, %r10] 0x01, #one_read
.word 0xc369f123 ! 45: PREFETCH_I prefetch [%r7 + 0xfffff123], #one_read
.word 0x9d902003 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0003, %wstate
setx 0xc5a46be0ed9682c5, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x87ad0a47 ! 48: FCMPd fcmpd %fcc<n>, %f20, %f38
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0x838f3165c7b52503, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r9, [%r0+0x3d0] %asi
.word 0x9d90400c ! 51: WRPR_WSTATE_R wrpr %r1, %r12, %wstate
.word 0xe63fe1db ! 52: STD_I std %r19, [%r31 + 0x01db]
.word 0xa781281f ! 53: WR_GRAPHICS_STATUS_REG_I wr %r4, 0x081f, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x36800001 ! 1: BGE bge,a <label_0x1>
.word 0x8d90305d ! 55: WRPR_PSTATE_I wrpr %r0, 0x105d, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xa9b0c486 ! 57: FCMPLE32 fcmple32 %d34, %d6, %r20
best_set_reg(0x5ca48d7c08c164dc, %r16, %r17)
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_35
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_35
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_35
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050a4e5b7c7,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xe8bfc030 ! 59: STDA_R stda %r20, [%r31 + %r16] 0x01
.word 0xe8cfe100 ! 60: LDSBA_I ldsba [%r31, + 0x0100] %asi, %r20
.word 0x91a489d2 ! 61: FDIVd fdivd %f18, %f18, %f8
.word 0xa9410000 ! 62: RDTICK rd %tick, %r20
.word 0xd31fe020 ! 63: LDDF_I ldd [%r31, 0x0020], %f9
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3d8] %asi
.word 0x9d924013 ! 64: WRPR_WSTATE_R wrpr %r9, %r19, %wstate
.word 0xc36fe1ce ! 65: PREFETCH_I prefetch [%r31 + 0x01ce], #one_read
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 66: FCMPd fcmpd %fcc<n>, %f0, %f4
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_80_42-donret_80_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00f9ec00 | (0x58 << 24)), %r13
wrhpr %g0, 0xf4c, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (80)
.word 0xd26fe031 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x0031]
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_43
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_43
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_43
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040acf7c7aa,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xa7a489b1 ! 68: FDIVs fdivs %f18, %f17, %f19
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe1e8 ! 71: LDXA_I ldxa [%r31, + 0x01e8] %asi, %r19
.word 0xe737e0bc ! 72: STQF_I - %f19, [0x00bc, %r31]
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x95b507c5 ! 74: PDIST pdistn %d20, %d36, %d10
.word 0xd22fe160 ! 75: STB_I stb %r9, [%r31 + 0x0160]
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
sllx %r9, %r8, %r9 ! My core mask
xor %r9, 0x80, %r9 ! My core mask
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_80_46
ldxa [0x50]%asi, %r13 !Running_rw
brnz,a %r10, cmp_wait80_46
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
brz,a %r8, cmp_multi_core_80_46
best_set_reg(0x4232431ecbb23edc, %r16, %r17)
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
st %g0, [%r23] !clear lock
.word 0x91944014 ! 77: WRPR_PIL_R wrpr %r17, %r20, %pil
.word 0xd297c032 ! 78: LDUHA_R lduha [%r31, %r18] 0x01, %r9
.word 0x83d020b5 ! 79: Tcc_I te icc_or_xcc, %r0 + 181
best_set_reg(0x9a622a9fd7397fad, %r16, %r17)
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0x33e31affa379bd8a, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e00a ! 84: STQF_I - %f9, [0x000a, %r31]
set user_data_start, %r31
.word 0x8580f41c ! 85: WRCCR_I wr %r3, 0x141c, %ccr
.word 0x91d0001e ! 86: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0x3fd1d7940d24a498, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffffffffffff3e1, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd2800c60 ! 92: LDUWA_R lduwa [%r0, %r0] 0x63, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa7414000 ! 93: RDPC rd %pc, %r19
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe0f0 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x00f0]
.word 0xe1e7e010 ! 94: CASA_R casa [%r31] %asi, %r16, %r16
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r8, [%r0+0x3e0] %asi
.word 0x9d90c012 ! 96: WRPR_WSTATE_R wrpr %r3, %r18, %wstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_60
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_60
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_60
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x000000401dc7aa0f,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xe19fe0a0 ! 97: LDDFA_I ldda [%r31, 0x00a0], %f16
.word 0xc19fde00 ! 98: LDDFA_R ldda [%r31, %r0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100f0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x93414000 ! 99: RDPC rd %pc, %r9
.word 0xdb37e007 ! 100: STQF_I - %f13, [0x0007, %r31]
.word 0xc3ec4031 ! 101: PREFETCHA_R prefetcha [%r17, %r17] 0x01, #one_read
best_set_reg(0x89ce993dd4e0bdba, %r16, %r17)
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902007 ! 103: WRPR_CWP_I wrpr %r0, 0x0007, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x8db00484 ! 106: FCMPLE32 fcmple32 %d0, %d4, %r6
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_68
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_68
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_68
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040c1ea0f7b,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0x93a489a8 ! 107: FDIVs fdivs %f18, %f8, %f9
best_set_reg(0xf5da2eecb26deb75, %r26, %r27)
sethi %hi(0x20008000), %r26 ! Set ITTM/DTTM
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0xcbaf51f9023ae5c8, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e011 ! 110: CASA_R casa [%r31] %asi, %r17, %r11
.word 0xe1bfe180 ! 111: STDFA_I stda %f16, [0x0180, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_80_72-donret_80_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x00ba7d00 | (0x83 << 24)), %r13
wrhpr %g0, 0x1455, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (80)
.word 0x35400001 ! 1: FBPUE fbue,a,pn %fcc0, <label_0x1>
.word 0x95a149c5 ! 112: FDIVd fdivd %f36, %f36, %f10
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_73
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_73
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_73
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x0000004083cf7b7e,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xd297c033 ! 113: LDUHA_R lduha [%r31, %r19] 0x01, %r9
.word 0xe1bfdc00 ! 114: STDFA_R stda %f16, [%r0, %r31]
.word 0x8d903103 ! 115: WRPR_PSTATE_I wrpr %r0, 0x1103, %pstate
.word 0x87802010 ! 116: WRASI_I wr %r0, 0x0010, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_76) + 0, 16, 16)) -> intp(6,0,9)
setx 0x5c4b5afdde9a152e, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_77
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_77
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_77
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040f0fb7e47,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xc3eb4022 ! 118: PREFETCHA_R prefetcha [%r13, %r2] 0x01, #one_read
.word 0x83d020b2 ! 119: Tcc_I te icc_or_xcc, %r0 + 178
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r17, [%r0+0x3e8] %asi
.word 0x9d918007 ! 120: WRPR_WSTATE_R wrpr %r6, %r7, %wstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_79
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_79
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_79
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040b3fe476c,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xe19fdf20 ! 121: LDDFA_R ldda [%r31, %r0], %f16
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_80
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_80
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_80
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050cbc76cd3,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xa7b40484 ! 122: FCMPLE32 fcmple32 %d16, %d4, %r19
.word 0x8d802000 ! 123: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x34800001 ! 1: BG bg,a <label_0x1>
.word 0x819821b4 ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x01b4, %hpstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_82
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_82
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_82
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x0000005010ecd3f6,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xd13fc009 ! 125: STDF_R std %f8, [%r9, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_80_83-donret_80_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x0040a300 | (22 << 24)), %r13
wrhpr %g0, 0x71f, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (80)
.word 0x22800001 ! 1: BE be,a <label_0x1>
.word 0x22800001 ! 126: BE be,a <label_0x1>
.word 0xd11fc008 ! 127: LDDF_R ldd [%r31, %r8], %f8
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x8581707f ! 130: WRCCR_I wr %r5, 0x107f, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_86
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_86
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_86
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x000000400ad3f62f,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xe19fdb60 ! 132: LDDFA_R ldda [%r31, %r0], %f16
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
sllx %r9, %r8, %r9 ! My core mask
xor %r9, 0x80, %r9 ! My core mask
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_80_87
ldxa [0x50]%asi, %r13 !Running_rw
brnz,a %r10, cmp_wait80_87
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
brz,a %r8, cmp_multi_core_80_87
best_set_reg(0x0eabbe140cc308f1, %r16, %r17)
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
st %g0, [%r23] !clear lock
.word 0x91a00171 ! 133: FABSq dis not found
.word 0xdad7e130 ! 134: LDSHA_I ldsha [%r31, + 0x0130] %asi, %r13
.word 0x9f80367a ! 135: SIR sir 0x167a
setx fp_data_quads, %r19, %r20
.word 0x89b00484 ! 136: FCMPLE32 fcmple32 %d0, %d4, %r4
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xa1b40307 ! 137: ALIGNADDRESS alignaddr %r16, %r7, %r16
.word 0xe137e192 ! 138: STQF_I - %f16, [0x0192, %r31]
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 139: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x3c800001 ! 1: BPOS bpos,a <label_0x1>
.word 0x8d903cf5 ! 140: WRPR_PSTATE_I wrpr %r0, 0x1cf5, %pstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_93
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_93
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_93
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040f9f62fdf,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xa7a449d2 ! 141: FDIVd fdivd %f48, %f18, %f50
.word 0x95a000cd ! 142: FNEGd fnegd %f44, %f10
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa3b4c7d0 ! 143: PDIST pdistn %d50, %d16, %d48
.word 0x91d0001e ! 144: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x858161b0 ! 146: WRCCR_I wr %r5, 0x01b0, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe69fe0a0 ! 147: LDDA_I ldda [%r31, + 0x00a0] %asi, %r19
.word 0xa7824014 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r9, %r20, %-
.word 0xe637e0d2 ! 149: STH_I sth %r19, [%r31 + 0x00d2]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_98) + 56, 16, 16)) -> intp(1,0,15)
setx 0x6e63ba1cd7798e42, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0xe7f26770c09d57a6, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe6800b80 ! 152: LDUWA_R lduwa [%r0, %r0] 0x5c, %r19
.word 0xe62fe0d9 ! 153: STB_I stb %r19, [%r31 + 0x00d9]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3e8] %asi
.word 0x9d944008 ! 154: WRPR_WSTATE_R wrpr %r17, %r8, %wstate
.word 0xa350c000 ! 155: RDPR_TT rdpr %tt, %r17
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0xd9144008 ! 1: LDQF_R - [%r17, %r8], %f12
.word 0xc19fe1a0 ! 157: LDDFA_I ldda [%r31, 0x01a0], %f0
tsubcctv %r18, 0x1e35, %r17
.word 0xd407e0ec ! 158: LDUW_I lduw [%r31 + 0x00ec], %r10
.word 0xaf800011 ! 159: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c033 ! 160: CASA_I casa [%r31] 0x 1, %r19, %r10
.word 0x23400001 ! 1: FBPNE fbne,a,pn %fcc0, <label_0x1>
.word 0x95b7c4d4 ! 161: FCMPNE32 fcmpne32 %d62, %d20, %r10
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100c0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa9414000 ! 162: RDPC rd %pc, %r20
.word 0x28800001 ! 1: BLEU bleu,a <label_0x1>
.word 0x81983eed ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x1eed, %hpstate
mov 0x28, %r1 ! (VA for ASI 0x5a)
.word 0xd4d04b40 ! 164: LDSHA_R ldsha [%r1, %r0] 0x5a, %r10
.word 0xc1bfe1c0 ! 165: STDFA_I stda %f0, [0x01c0, %r31]
.word 0x8198369e ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x169e, %hpstate
.word 0x91d0001e ! 167: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x8d802004 ! 168: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0xd43fe178 ! 169: STD_I std %r10, [%r31 + 0x0178]
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
.word 0xe1bfe0e0 ! 173: STDFA_I stda %f16, [0x00e0, %r31]
.word 0xd51fe080 ! 174: LDDF_I ldd [%r31, 0x0080], %f10
.word 0xd44fe0e0 ! 175: LDSB_I ldsb [%r31 + 0x00e0], %r10
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
sllx %r9, %r8, %r9 ! My core mask
xor %r9, 0x80, %r9 ! My core mask
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmp_80_112
ldxa [0x50]%asi, %r13 !Running_rw
brnz,a %r10, cmp_wait80_112
ldxa [0x58]%asi, %r14 !Running_status
xnor %r14, %r13, %r14 !Bits equal
brz,a %r8, cmp_multi_core_80_112
best_set_reg(0xef6e0c0effc24af4, %r16, %r17)
and %r14, %r17, %r14 !Apply set/clear mask to bits equal
and %r14, %r9, %r14 !Apply core-mask
st %g0, [%r23] !clear lock
.word 0x9193400b ! 176: WRPR_PIL_R wrpr %r13, %r11, %pil
mov 0x0, %r1 ! (VA for ASI 0x4c)
.word 0xd4d04980 ! 177: LDSHA_R ldsha [%r1, %r0] 0x4c, %r10
setx 0x65020c4bf953a4df, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_80_115
brnz %r16, ibp_wait80_115
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_80_115
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_80_115
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050bbefdf4b,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xc19fe160 ! 179: LDDFA_I ldda [%r31, 0x0160], %f0
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610080, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x99414000 ! 181: RDPC rd %pc, %r12
.word 0xaf800011 ! 182: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
setx 0xd65c149f772f8a9e, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe0e8 ! 184: LDXA_I ldxa [%r31, + 0x00e8] %asi, %r16
setx 0x5321dd69d1452d98, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_80_120) + 0, 16, 16)) -> intp(4,0,0)
setx 0x594fc42e6e72eaa2, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa3b447d3 ! 187: PDIST pdistn %d48, %d50, %d48
.word 0x91d0001e ! 188: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xa7808011 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r2, %r17, %-
.word 0xda97e058 ! 190: LDUHA_I lduha [%r31, + 0x0058] %asi, %r13
.word 0x879cf1b2 ! 191: WRHPR_HINTP_I wrhpr %r19, 0x11b2, %hintp
.word 0x91d02034 ! 192: Tcc_I ta icc_or_xcc, %r0 + 52
.word 0xa780c011 ! 193: WR_GRAPHICS_STATUS_REG_R wr %r3, %r17, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x99702a39 ! 194: POPC_I popc 0x0a39, %r12
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c02c ! 1: CASA_I casa [%r31] 0x 1, %r12, %r9
.word 0xd297c029 ! 195: LDUHA_R lduha [%r31, %r9] 0x01, %r9
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x91b18492 ! 197: FCMPLE32 fcmple32 %d6, %d18, %r8
set user_data_start, %r31
.word 0x8581a6c6 ! 198: WRCCR_I wr %r6, 0x06c6, %ccr
.word 0xc1bfe120 ! 199: STDFA_I stda %f0, [0x0120, %r31]
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0884e60 ! 200: LDUBA_R lduba [%r1, %r0] 0x73, %r16
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONHPRIV ! macro
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
sllx %r9, %r8, %r9 ! My core mask
mov 0xff, %r9 ! My core mask
cmpenall_startwait80_130:
cas [%r23],%g0,%r10 !lock
brz,a %r10, continue_cmpenall_80_130
brnz %r10, cmpenall_wait80_130
ba,a cmpenall_startwait80_130
continue_cmpenall_80_130:
ldxa [0x58]%asi, %r14 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_cmpstat_80_130
ldxa [0x58]%asi, %r14 !Running_status
ldxa [0x10]%asi, %r14 !Get enabled threads
and %r14, %r9, %r14 !My core mask
stxa %r14, [0x60]%asi !W1S
ldxa [0x58]%asi, %r16 !Running_status
wait_for_cmpstat2_80_130:
and %r16, %r9, %r16 !My core mask
bne,a %xcc, wait_for_cmpstat2_80_130
ldxa [0x58]%asi, %r16 !Running_status
st %g0, [%r23] !clear lock
setx join_lbl_0_0, %g1, %g2
.word 0xe08008a0 ! 1: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0xe19fc2c0 ! 2: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe0800c20 ! 3: LDUWA_R lduwa [%r0, %r0] 0x61, %r16
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802004 ! 5: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x38800001 ! 1: BGU bgu,a <label_0x1>
.word 0x8d90276d ! 6: WRPR_PSTATE_I wrpr %r0, 0x076d, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_2) + 40, 16, 16)) -> intp(5,0,27)
setx 0xf684cb5605a2a8d1, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa7850011 ! 12: WR_GRAPHICS_STATUS_REG_R wr %r20, %r17, %-
setx fp_data_quads, %r19, %r20
.word 0x89a009c4 ! 13: FDIVd fdivd %f0, %f4, %f4
.word 0x91d0001e ! 14: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x879c000c ! 15: WRHPR_HINTP_R wrhpr %r16, %r12, %hintp
.word 0x95703cae ! 16: POPC_I popc 0x1cae, %r10
.word 0x8780201c ! 17: WRASI_I wr %r0, 0x001c, %asi
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_6
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_6
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_6
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xc3eb4021 ! 18: PREFETCHA_R prefetcha [%r13, %r1] 0x01, #one_read
.word 0x9ba00165 ! 19: FABSq dis not found
.word 0xe49fe0e8 ! 20: LDDA_I ldda [%r31, + 0x00e8] %asi, %r18
.word 0xe44fe058 ! 21: LDSB_I ldsb [%r31 + 0x0058], %r18
.word 0x8582b50c ! 22: WRCCR_I wr %r10, 0x150c, %ccr
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100f0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa5414000 ! 24: RDPC rd %pc, %r18
.word 0x8d90350d ! 25: WRPR_PSTATE_I wrpr %r0, 0x150d, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa17021e0 ! 1: POPC_I popc 0x01e0, %r16
.word 0xa77026b4 ! 26: POPC_I popc 0x06b4, %r19
setx 0x1c18c1b8cc9c1bdb, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xaf800011 ! 29: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7d4 ! 1: PDIST pdistn %d62, %d20, %d20
.word 0x9970207a ! 30: POPC_I popc 0x007a, %r12
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xd11fc00d ! 33: LDDF_R ldd [%r31, %r13], %f8
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e188 ! 35: LDSWA_I ldswa [%r31, + 0x0188] %asi, %r8
.word 0xc32fc00b ! 36: STXFSR_R st-sfr %f1, [%r11, %r31]
.word 0xaf800011 ! 37: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xc19fe0e0 ! 38: LDDFA_I ldda [%r31, 0x00e0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100e0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x95414000 ! 39: RDPC rd %pc, %r10
.word 0x87a9ca53 ! 40: FCMPd fcmpd %fcc<n>, %f38, %f50
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0x93508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe158 ! 43: LDXA_I ldxa [%r31, + 0x0158] %asi, %r19
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_24
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_24
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_24
ldxa [0x50]%asi, %r14 !Running_rw
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0x91702a9e ! 44: POPC_I popc 0x0a9e, %r8
.word 0x24ccc001 ! 45: BRLEZ brlez,a,pt %r19,<label_0xcc001>
.word 0x9d902003 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0003, %wstate
setx 0xdf7a3f95675d5bc5, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x97a049d2 ! 48: FDIVd fdivd %f32, %f18, %f42
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0xc7179a7059bf4264, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r1, [%r0+0x3d0] %asi
.word 0x9d94c007 ! 51: WRPR_WSTATE_R wrpr %r19, %r7, %wstate
.word 0xe63fe090 ! 52: STD_I std %r19, [%r31 + 0x0090]
.word 0xa784251b ! 53: WR_GRAPHICS_STATUS_REG_I wr %r16, 0x051b, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x36800001 ! 1: BGE bge,a <label_0x1>
.word 0x8d903801 ! 55: WRPR_PSTATE_I wrpr %r0, 0x1801, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xc3ec4026 ! 57: PREFETCHA_R prefetcha [%r17, %r6] 0x01, #one_read
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
.word 0xe897c02a ! 59: LDUHA_R lduha [%r31, %r10] 0x01, %r20
.word 0xe8cfe1e8 ! 60: LDSBA_I ldsba [%r31, + 0x01e8] %asi, %r20
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_36
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_36
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_36
ldxa [0x50]%asi, %r14 !Running_rw
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0x9ba489d2 ! 61: FDIVd fdivd %f18, %f18, %f44
.word 0xa9410000 ! 62: RDTICK rd %tick, %r20
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_38
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_38
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_38
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xc32fc009 ! 63: STXFSR_R st-sfr %f1, [%r9, %r31]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r16, [%r0+0x3d0] %asi
.word 0x9d930012 ! 64: WRPR_WSTATE_R wrpr %r12, %r18, %wstate
.word 0xc32fc000 ! 65: STXFSR_R st-sfr %f1, [%r0, %r31]
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 66: FCMPd fcmpd %fcc<n>, %f0, %f4
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_40_42-donret_40_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x005bf800 | (32 << 24)), %r13
wrhpr %g0, 0x377, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (40)
.word 0xd26fe056 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x0056]
.word 0xc3e88027 ! 68: PREFETCHA_R prefetcha [%r2, %r7] 0x01, #one_read
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe168 ! 71: LDXA_I ldxa [%r31, + 0x0168] %asi, %r19
.word 0xe737e06a ! 72: STQF_I - %f19, [0x006a, %r31]
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa5b347ca ! 74: PDIST pdistn %d44, %d10, %d18
.word 0xd22fe103 ! 75: STB_I stb %r9, [%r31 + 0x0103]
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
.word 0x9194c005 ! 77: WRPR_PIL_R wrpr %r19, %r5, %pil
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_47
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_47
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_47
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xd23fe0c0 ! 78: STD_I std %r9, [%r31 + 0x00c0]
.word 0x91d020b3 ! 79: Tcc_I ta icc_or_xcc, %r0 + 179
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0x5dea91aaefafd4d0, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e014 ! 84: STQF_I - %f9, [0x0014, %r31]
set user_data_start, %r31
.word 0x8580acd3 ! 85: WRCCR_I wr %r2, 0x0cd3, %ccr
.word 0x83d0001e ! 86: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0xc633e1b6d0fcab6b, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffffe36fffffcbd, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd2800c20 ! 92: LDUWA_R lduwa [%r0, %r0] 0x61, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610060, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x9b414000 ! 93: RDPC rd %pc, %r13
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe000 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x0000]
.word 0xe09fe010 ! 94: LDDA_I ldda [%r31, + 0x0010] %asi, %r16
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r9, [%r0+0x3e8] %asi
.word 0x9d920005 ! 96: WRPR_WSTATE_R wrpr %r8, %r5, %wstate
.word 0xc19fdf20 ! 97: LDDFA_R ldda [%r31, %r0], %f0
.word 0xc19fda00 ! 98: LDDFA_R ldda [%r31, %r0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610070, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x99414000 ! 99: RDPC rd %pc, %r12
.word 0xdb37e0e1 ! 100: STQF_I - %f13, [0x00e1, %r31]
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_62
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_62
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_62
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xa1a109b2 ! 101: FDIVs fdivs %f4, %f18, %f16
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902002 ! 103: WRPR_CWP_I wrpr %r0, 0x0002, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x8da009a4 ! 106: FDIVs fdivs %f0, %f4, %f6
.word 0xa17025cc ! 107: POPC_I popc 0x05cc, %r16
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0xd902b1ccb60d0c9d, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e00b ! 110: CASA_R casa [%r31] %asi, %r11, %r11
.word 0xc1bfe000 ! 111: STDFA_I stda %f0, [0x0000, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_40_72-donret_40_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x00b7c100 | (28 << 24)), %r13
wrhpr %g0, 0xd17, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (40)
.word 0x38800001 ! 1: BGU bgu,a <label_0x1>
.word 0xa3a309cc ! 112: FDIVd fdivd %f12, %f12, %f48
.word 0xd297c034 ! 113: LDUHA_R lduha [%r31, %r20] 0x01, %r9
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_74
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_74
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_74
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000000e0a00000, %r20, %r19)
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xc1bfdf20 ! 114: STDFA_R stda %f0, [%r0, %r31]
.word 0x8d90225f ! 115: WRPR_PSTATE_I wrpr %r0, 0x025f, %pstate
.word 0x87802004 ! 116: WRASI_I wr %r0, 0x0004, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_76) + 8, 16, 16)) -> intp(0,0,16)
setx 0xcec1a4e4b65786f0, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x97a449c7 ! 118: FDIVd fdivd %f48, %f38, %f42
.word 0x91d02032 ! 119: Tcc_I ta icc_or_xcc, %r0 + 50
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r5, [%r0+0x3d0] %asi
.word 0x9d948011 ! 120: WRPR_WSTATE_R wrpr %r18, %r17, %wstate
.word 0xc19fdc00 ! 121: LDDFA_R ldda [%r31, %r0], %f0
.word 0xa1702b60 ! 122: POPC_I popc 0x0b60, %r16
.word 0x8d802000 ! 123: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1>
.word 0x8198261f ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x061f, %hpstate
.word 0xd11fe110 ! 125: LDDF_I ldd [%r31, 0x0110], %f8
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_40_83-donret_40_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00221a00 | (32 << 24)), %r13
wrhpr %g0, 0x14d4, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (40)
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x37400001 ! 126: FBPGE fbge,a,pn %fcc0, <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_84
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_84
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_84
ldxa [0x50]%asi, %r14 !Running_rw
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xd097c02a ! 127: LDUHA_R lduha [%r31, %r10] 0x01, %r8
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x85826459 ! 130: WRCCR_I wr %r9, 0x0459, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
.word 0xe19fdf20 ! 132: LDDFA_R ldda [%r31, %r0], %f16
.word 0xa9a00174 ! 133: FABSq dis not found
.word 0xdad7e100 ! 134: LDSHA_I ldsha [%r31, + 0x0100] %asi, %r13
.word 0xc36d2921 ! 135: PREFETCH_I prefetch [%r20 + 0x0921], #one_read
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 136: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0x95b40310 ! 137: ALIGNADDRESS alignaddr %r16, %r16, %r10
.word 0xe137e060 ! 138: STQF_I - %f16, [0x0060, %r31]
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 139: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x27400001 ! 1: FBPUL fbul,a,pn %fcc0, <label_0x1>
.word 0x8d90361a ! 140: WRPR_PSTATE_I wrpr %r0, 0x161a, %pstate
.word 0x95702e73 ! 141: POPC_I popc 0x0e73, %r10
.word 0x99a000cb ! 142: FNEGd fnegd %f42, %f12
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa7b087d1 ! 143: PDIST pdistn %d2, %d48, %d50
.word 0x93d0001e ! 144: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x8584a970 ! 146: WRCCR_I wr %r18, 0x0970, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe69fc02d ! 147: LDDA_R ldda [%r31, %r13] 0x01, %r19
.word 0xa7850001 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r20, %r1, %-
.word 0xe637e086 ! 149: STH_I sth %r19, [%r31 + 0x0086]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_98) + 24, 16, 16)) -> intp(7,0,21)
setx 0xdd083d62bf292d7d, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0xe49f4ccc99fd2716, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe6800c40 ! 152: LDUWA_R lduwa [%r0, %r0] 0x62, %r19
.word 0xe62fe109 ! 153: STB_I stb %r19, [%r31 + 0x0109]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3d8] %asi
.word 0x9d944007 ! 154: WRPR_WSTATE_R wrpr %r17, %r7, %wstate
.word 0x9950c000 ! 155: RDPR_TT <illegal instruction>
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0x91b7c711 ! 1: FMULD8SUx16 fmuld8ulx16 %f31, %f17, %d8
.word 0xc1bfe0a0 ! 157: STDFA_I stda %f0, [0x00a0, %r31]
tsubcctv %r16, 0x1402, %r17
.word 0xd407e1c2 ! 158: LDUW_I lduw [%r31 + 0x01c2], %r10
.word 0xb3800011 ! 159: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c032 ! 160: CASA_I casa [%r31] 0x 1, %r18, %r10
.word 0x34800001 ! 1: BG bg,a <label_0x1>
.word 0x87afca52 ! 161: FCMPd fcmpd %fcc<n>, %f62, %f18
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100a0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa5414000 ! 162: RDPC rd %pc, %r18
.word 0x3e800001 ! 1: BVC bvc,a <label_0x1>
.word 0x81983fc7 ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x1fc7, %hpstate
mov 0x20, %r1 ! (VA for ASI 0x5a)
.word 0xd4904b40 ! 164: LDUHA_R lduha [%r1, %r0] 0x5a, %r10
.word 0xe1bfe160 ! 165: STDFA_I stda %f16, [0x0160, %r31]
.word 0x81982ec7 ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x0ec7, %hpstate
.word 0x83d0001e ! 167: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0x8d802000 ! 168: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xd43fe078 ! 169: STD_I std %r10, [%r31 + 0x0078]
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_111
brnz %r16, iaw_wait40_111
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_111
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_111
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xc19fe160 ! 173: LDDFA_I ldda [%r31, 0x0160], %f0
.word 0xd51fe138 ! 174: LDDF_I ldd [%r31, 0x0138], %f10
.word 0xd44fe048 ! 175: LDSB_I ldsb [%r31 + 0x0048], %r10
.word 0x91940010 ! 176: WRPR_PIL_R wrpr %r16, %r16, %pil
mov 0x0, %r1 ! (VA for ASI 0x4c)
.word 0xd4c84980 ! 177: LDSBA_R ldsba [%r1, %r0] 0x4c, %r10
setx 0x4f33151ca4a75faf, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xc1bfe180 ! 179: STDFA_I stda %f0, [0x0180, %r31]
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610020, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x99414000 ! 181: RDPC rd %pc, %r12
.word 0xb3800011 ! 182: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx 0xd002c562da68a75a, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe038 ! 184: LDXA_I ldxa [%r31, + 0x0038] %asi, %r16
setx 0x4a6561a2fb78120b, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_40_120) + 40, 16, 16)) -> intp(5,0,7)
setx 0x41a5092e9cbc85d8, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x95b087cb ! 187: PDIST pdistn %d2, %d42, %d10
.word 0x91d0001e ! 188: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xa7840005 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r16, %r5, %-
.word 0xda97e048 ! 190: LDUHA_I lduha [%r31, + 0x0048] %asi, %r13
.word 0x879c6060 ! 191: WRHPR_HINTP_I wrhpr %r17, 0x0060, %hintp
.word 0x83d020b3 ! 192: Tcc_I te icc_or_xcc, %r0 + 179
.word 0xa7850003 ! 193: WR_GRAPHICS_STATUS_REG_R wr %r20, %r3, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x95b50492 ! 194: FCMPLE32 fcmple32 %d20, %d18, %r10
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c031 ! 1: CASA_I casa [%r31] 0x 1, %r17, %r9
.word 0xd2dfc02d ! 195: LDXA_R ldxa [%r31, %r13] 0x01, %r9
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xc3ec0025 ! 197: PREFETCHA_R prefetcha [%r16, %r5] 0x01, #one_read
set user_data_start, %r31
.word 0x8584a8b7 ! 198: WRCCR_I wr %r18, 0x08b7, %ccr
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_40_127
brnz %r16, iaw_wait40_127
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_40_127
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_40_127
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xe19fe020 ! 199: LDDFA_I ldda [%r31, 0x0020], %f16
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0884e60 ! 200: LDUBA_R lduba [%r1, %r0] 0x73, %r16
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
ta T_CHANGE_NONHPRIV ! macro
setx join_lbl_0_0, %g1, %g2
.word 0xe0800b00 ! 1: LDUWA_R lduwa [%r0, %r0] 0x58, %r16
.word 0xe19fd960 ! 2: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe08008a0 ! 3: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802004 ! 5: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x29400001 ! 1: FBPL fbl,a,pn %fcc0, <label_0x1>
.word 0x8d9033c8 ! 6: WRPR_PSTATE_I wrpr %r0, 0x13c8, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_2) + 40, 16, 16)) -> intp(6,0,10)
setx 0xe0af905dd5df8bcf, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa7844003 ! 12: WR_GRAPHICS_STATUS_REG_R wr %r17, %r3, %-
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 13: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x91d0001e ! 14: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x87998002 ! 15: WRHPR_HINTP_R wrhpr %r6, %r2, %hintp
.word 0xa770321e ! 16: POPC_I popc 0x121e, %r19
.word 0x87802089 ! 17: WRASI_I wr %r0, 0x0089, %asi
.word 0x97a049c4 ! 18: FDIVd fdivd %f32, %f4, %f42
.word 0xa3a00170 ! 19: FABSq dis not found
.word 0xe49fe010 ! 20: LDDA_I ldda [%r31, + 0x0010] %asi, %r18
.word 0xe44fe018 ! 21: LDSB_I ldsb [%r31 + 0x0018], %r18
.word 0x858429b4 ! 22: WRCCR_I wr %r16, 0x09b4, %ccr
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610070, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa3414000 ! 24: RDPC rd %pc, %r17
.word 0x8d903862 ! 25: WRPR_PSTATE_I wrpr %r0, 0x1862, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa1702010 ! 1: POPC_I popc 0x0010, %r16
.word 0xc3ea0024 ! 26: PREFETCHA_R prefetcha [%r8, %r4] 0x01, #one_read
setx 0x69614f46d6d905ac, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xb3800011 ! 29: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7c8 ! 1: PDIST pdistn %d62, %d8, %d20
.word 0xc3eac030 ! 30: PREFETCHA_R prefetcha [%r11, %r16] 0x01, #one_read
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xd1e7e011 ! 33: CASA_R casa [%r31] %asi, %r17, %r8
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e168 ! 35: LDSWA_I ldswa [%r31, + 0x0168] %asi, %r8
.word 0xd13fc011 ! 36: STDF_R std %f8, [%r17, %r31]
.word 0xb3800011 ! 37: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xc19fe080 ! 38: LDDFA_I ldda [%r31, 0x0080], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610070, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x9b414000 ! 39: RDPC rd %pc, %r13
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0x91a349d2 ! 40: FDIVd fdivd %f44, %f18, %f8
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0x97508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe0a0 ! 43: LDXA_I ldxa [%r31, + 0x00a0] %asi, %r19
.word 0xa9703b46 ! 44: POPC_I popc 0x1b46, %r20
fbne,a,pn %fcc0, skip_20_25
.word 0x9f803c11 ! 45: SIR sir 0x1c11
.word 0x9d902005 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0005, %wstate
setx 0x652c86ffe3fecb95, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0x87aaca4a ! 48: FCMPd fcmpd %fcc<n>, %f42, %f10
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0xdf903d4772088b49, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r16, [%r0+0x3d0] %asi
.word 0x9d90c006 ! 51: WRPR_WSTATE_R wrpr %r3, %r6, %wstate
.word 0xe63fe0c6 ! 52: STD_I std %r19, [%r31 + 0x00c6]
.word 0xa784fac8 ! 53: WR_GRAPHICS_STATUS_REG_I wr %r19, 0x1ac8, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0x8d903bd1 ! 55: WRPR_PSTATE_I wrpr %r0, 0x1bd1, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
stxa %r20, [%g0]0x54 ! I unsupported page size ..
.word 0xa3a489a1 ! 57: FDIVs fdivs %f18, %f1, %f17
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
.word 0xe89fc029 ! 59: LDDA_R ldda [%r31, %r9] 0x01, %r20
.word 0xe8cfe1b8 ! 60: LDSBA_I ldsba [%r31, + 0x01b8] %asi, %r20
.word 0xa3703972 ! 61: POPC_I popc 0x1972, %r17
.word 0x95410000 ! 62: RDTICK rd %tick, %r10
.word 0xd31fe030 ! 63: LDDF_I ldd [%r31, 0x0030], %f9
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r10, [%r0+0x3d0] %asi
.word 0x9d94400d ! 64: WRPR_WSTATE_R wrpr %r17, %r13, %wstate
.word 0xc30fc000 ! 65: LDXFSR_R ld-fsr [%r31, %r0], %f1
setx fp_data_quads, %r19, %r20
.word 0x89a009a4 ! 66: FDIVs fdivs %f0, %f4, %f4
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_20_42-donret_20_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00c5d700 | (0x4f << 24)), %r13
wrhpr %g0, 0xfc9, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (20)
.word 0xd26fe080 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x0080]
.word 0xa7a4c9b0 ! 68: FDIVs fdivs %f19, %f16, %f19
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe180 ! 71: LDXA_I ldxa [%r31, + 0x0180] %asi, %r19
.word 0xe737e0c1 ! 72: STQF_I - %f19, [0x00c1, %r31]
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa1b4c7c3 ! 74: PDIST pdistn %d50, %d34, %d16
.word 0xd22fe174 ! 75: STB_I stb %r9, [%r31 + 0x0174]
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
.word 0x9194c013 ! 77: WRPR_PIL_R wrpr %r19, %r19, %pil
.word 0xd29fe050 ! 78: LDDA_I ldda [%r31, + 0x0050] %asi, %r9
.word 0x83d02033 ! 79: Tcc_I te icc_or_xcc, %r0 + 51
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0x32f6c0d2643b6bae, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e192 ! 84: STQF_I - %f9, [0x0192, %r31]
set user_data_start, %r31
.word 0x85843954 ! 85: WRCCR_I wr %r16, 0x1954, %ccr
.word 0x91d0001e ! 86: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0xb83f66312b07aaa2, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffff0e3fffffead, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd28008a0 ! 92: LDUWA_R lduwa [%r0, %r0] 0x45, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100c0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa5414000 ! 93: RDPC rd %pc, %r18
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe1f0 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x01f0]
.word 0xe09fc032 ! 94: LDDA_R ldda [%r31, %r18] 0x01, %r16
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r19, [%r0+0x3d8] %asi
.word 0x9d950014 ! 96: WRPR_WSTATE_R wrpr %r20, %r20, %wstate
.word 0xc1bfdb60 ! 97: STDFA_R stda %f0, [%r0, %r31]
.word 0xe19fdc00 ! 98: LDDFA_R ldda [%r31, %r0], %f16
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610000, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa5414000 ! 99: RDPC rd %pc, %r18
.word 0xdb37e124 ! 100: STQF_I - %f13, [0x0124, %r31]
.word 0xc3ec0032 ! 101: PREFETCHA_R prefetcha [%r16, %r18] 0x01, #one_read
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902003 ! 103: WRPR_CWP_I wrpr %r0, 0x0003, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0xc3e82fe8 ! 106: PREFETCHA_I prefetcha [%r0, + 0x0fe8] %asi, #one_read
.word 0xc3ec002a ! 107: PREFETCHA_R prefetcha [%r16, %r10] 0x01, #one_read
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0x06f3ff2907523cda, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e012 ! 110: CASA_R casa [%r31] %asi, %r18, %r11
.word 0xe1bfe060 ! 111: STDFA_I stda %f16, [0x0060, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_20_72-donret_20_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x000fa900 | (32 << 24)), %r13
wrhpr %g0, 0x897, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (20)
.word 0x23400001 ! 1: FBPNE fbne,a,pn %fcc0, <label_0x1>
.word 0x9ba409cb ! 112: FDIVd fdivd %f16, %f42, %f44
.word 0xc32fc011 ! 113: STXFSR_R st-sfr %f1, [%r17, %r31]
.word 0xc1bfdb60 ! 114: STDFA_R stda %f0, [%r0, %r31]
.word 0x8d903172 ! 115: WRPR_PSTATE_I wrpr %r0, 0x1172, %pstate
.word 0x87802058 ! 116: WRASI_I wr %r0, 0x0058, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_76) + 40, 16, 16)) -> intp(2,0,8)
setx 0x993df71598200c8f, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xa5702f2f ! 118: POPC_I popc 0x0f2f, %r18
.word 0x91d02035 ! 119: Tcc_I ta icc_or_xcc, %r0 + 53
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r1, [%r0+0x3c8] %asi
.word 0x9d920014 ! 120: WRPR_WSTATE_R wrpr %r8, %r20, %wstate
.word 0xe19fe1a0 ! 121: LDDFA_I ldda [%r31, 0x01a0], %f16
.word 0xc3eac023 ! 122: PREFETCHA_R prefetcha [%r11, %r3] 0x01, #one_read
.word 0x8d802004 ! 123: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x35400001 ! 1: FBPUE fbue,a,pn %fcc0, <label_0x1>
.word 0x81982d94 ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x0d94, %hpstate
.word 0xc32fc008 ! 125: STXFSR_R st-sfr %f1, [%r8, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_20_83-donret_20_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00228a00 | (0x83 << 24)), %r13
wrhpr %g0, 0x655, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (20)
.word 0x2c800001 ! 1: BNEG bneg,a <label_0x1>
.word 0x25400001 ! 126: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd1e7e00b ! 127: CASA_R casa [%r31] %asi, %r11, %r8
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x85833144 ! 130: WRCCR_I wr %r12, 0x1144, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
.word 0xc1bfe020 ! 132: STDFA_I stda %f0, [0x0020, %r31]
.word 0xa7a00170 ! 133: FABSq dis not found
.word 0xdad7e128 ! 134: LDSHA_I ldsha [%r31, + 0x0128] %asi, %r13
.word 0x24cb0001 ! 135: BRLEZ brlez,a,pt %r12,<label_0xb0001>
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 136: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0x97b20306 ! 137: ALIGNADDRESS alignaddr %r8, %r6, %r11
.word 0xe137e11a ! 138: STQF_I - %f16, [0x011a, %r31]
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 139: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x2f400001 ! 1: FBPU fbu,a,pn %fcc0, <label_0x1>
.word 0x8d9036ff ! 140: WRPR_PSTATE_I wrpr %r0, 0x16ff, %pstate
.word 0xc3ec402d ! 141: PREFETCHA_R prefetcha [%r17, %r13] 0x01, #one_read
.word 0x95a000d0 ! 142: FNEGd fnegd %f16, %f10
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa1b4c7c2 ! 143: PDIST pdistn %d50, %d2, %d16
.word 0x83d0001e ! 144: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x8584edbc ! 146: WRCCR_I wr %r19, 0x0dbc, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe73fc010 ! 147: STDF_R std %f19, [%r16, %r31]
.word 0xa7844001 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r17, %r1, %-
.word 0xe637e178 ! 149: STH_I sth %r19, [%r31 + 0x0178]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_98) + 32, 16, 16)) -> intp(0,0,31)
setx 0x72c6476983d61638, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0x8d19a04437ee58bd, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe6800bc0 ! 152: LDUWA_R lduwa [%r0, %r0] 0x5e, %r19
.word 0xe62fe0dc ! 153: STB_I stb %r19, [%r31 + 0x00dc]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r18, [%r0+0x3e0] %asi
.word 0x9d924011 ! 154: WRPR_WSTATE_R wrpr %r9, %r17, %wstate
.word 0x9950c000 ! 155: RDPR_TT <illegal instruction>
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0xe7150004 ! 1: LDQF_R - [%r20, %r4], %f19
.word 0xe19fe000 ! 157: LDDFA_I ldda [%r31, 0x0000], %f16
tsubcctv %r4, 0x1358, %r17
.word 0xd407e12c ! 158: LDUW_I lduw [%r31 + 0x012c], %r10
.word 0xaf800011 ! 159: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c033 ! 160: CASA_I casa [%r31] 0x 1, %r19, %r10
.word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1>
.word 0x24cfc001 ! 161: BRLEZ brlez,a,pt %r31,<label_0xfc001>
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610050, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 162: RDPC rd %pc, %r16
.word 0x38800001 ! 1: BGU bgu,a <label_0x1>
.word 0x81982b8f ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x0b8f, %hpstate
mov 0x0, %r1 ! (VA for ASI 0x5a)
.word 0xd4c04b40 ! 164: LDSWA_R ldswa [%r1, %r0] 0x5a, %r10
.word 0xc1bfe180 ! 165: STDFA_I stda %f0, [0x0180, %r31]
.word 0x819820dd ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x00dd, %hpstate
.word 0x93d0001e ! 167: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x8d802004 ! 168: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0xd43fe1c0 ! 169: STD_I std %r10, [%r31 + 0x01c0]
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
.word 0xe19fe160 ! 173: LDDFA_I ldda [%r31, 0x0160], %f16
.word 0xd51fe048 ! 174: LDDF_I ldd [%r31, 0x0048], %f10
.word 0xd44fe1b8 ! 175: LDSB_I ldsb [%r31 + 0x01b8], %r10
.word 0x91934013 ! 176: WRPR_PIL_R wrpr %r13, %r19, %pil
mov 0x20, %r1 ! (VA for ASI 0x4c)
.word 0xd4904980 ! 177: LDUHA_R lduha [%r1, %r0] 0x4c, %r10
setx 0xb6d5358f9182465d, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe19fdc00 ! 179: LDDFA_R ldda [%r31, %r0], %f16
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100c0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 181: RDPC rd %pc, %r16
.word 0xaf800011 ! 182: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
setx 0x4ae8310246683cd0, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe0a8 ! 184: LDXA_I ldxa [%r31, + 0x00a8] %asi, %r16
setx 0x89e0f53a818c82b0, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_20_120) + 32, 16, 16)) -> intp(2,0,14)
setx 0xe0c95aa21fabee2d, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa7b4c7d3 ! 187: PDIST pdistn %d50, %d50, %d50
.word 0x91d0001e ! 188: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xa7820012 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r8, %r18, %-
.word 0xda97e1e8 ! 190: LDUHA_I lduha [%r31, + 0x01e8] %asi, %r13
.word 0x879ce990 ! 191: WRHPR_HINTP_I wrhpr %r19, 0x0990, %hintp
.word 0x83d02034 ! 192: Tcc_I te icc_or_xcc, %r0 + 52
.word 0xa7810014 ! 193: WR_GRAPHICS_STATUS_REG_R wr %r4, %r20, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x87ac4a51 ! 194: FCMPd fcmpd %fcc<n>, %f48, %f48
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c02c ! 1: CASA_I casa [%r31] 0x 1, %r12, %r9
.word 0xd29fc02d ! 195: LDDA_R ldda [%r31, %r13] 0x01, %r9
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x97b147cc ! 197: PDIST pdistn %d36, %d12, %d42
set user_data_start, %r31
.word 0x8584fa7c ! 198: WRCCR_I wr %r19, 0x1a7c, %ccr
.word 0xc1bfc2c0 ! 199: STDFA_R stda %f0, [%r0, %r31]
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0c84e60 ! 200: LDSBA_R ldsba [%r1, %r0] 0x73, %r16
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONHPRIV ! macro
setx join_lbl_0_0, %g1, %g2
.word 0xe08008a0 ! 1: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0xe19fdb60 ! 2: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe08008a0 ! 3: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802004 ! 5: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x2d400001 ! 1: FBPG fbg,a,pn %fcc0, <label_0x1>
.word 0x8d903e0b ! 6: WRPR_PSTATE_I wrpr %r0, 0x1e0b, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_2) + 56, 16, 16)) -> intp(7,0,19)
setx 0xa587d25567803154, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa784800b ! 12: WR_GRAPHICS_STATUS_REG_R wr %r18, %r11, %-
setx fp_data_quads, %r19, %r20
.word 0x91a009c4 ! 13: FDIVd fdivd %f0, %f4, %f8
.word 0x91d0001e ! 14: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x879c4009 ! 15: WRHPR_HINTP_R wrhpr %r17, %r9, %hintp
.word 0xa5703641 ! 16: POPC_I popc 0x1641, %r18
.word 0x87802058 ! 17: WRASI_I wr %r0, 0x0058, %asi
.word 0xa7a109aa ! 18: FDIVs fdivs %f4, %f10, %f19
.word 0xa9a00161 ! 19: FABSq dis not found
.word 0xe49fe0c0 ! 20: LDDA_I ldda [%r31, + 0x00c0] %asi, %r18
.word 0xe44fe148 ! 21: LDSB_I ldsb [%r31 + 0x0148], %r18
.word 0x85837b95 ! 22: WRCCR_I wr %r13, 0x1b95, %ccr
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa9414000 ! 24: RDPC rd %pc, %r20
.word 0x8d903b5d ! 25: WRPR_PSTATE_I wrpr %r0, 0x1b5d, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa1702190 ! 1: POPC_I popc 0x0190, %r16
.word 0xa9a449c9 ! 26: FDIVd fdivd %f48, %f40, %f20
setx 0x1c1a7285575e7b55, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xaf800011 ! 29: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7d4 ! 1: PDIST pdistn %d62, %d20, %d20
.word 0x97703953 ! 30: POPC_I popc 0x1953, %r11
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xd11fe0c0 ! 33: LDDF_I ldd [%r31, 0x00c0], %f8
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e058 ! 35: LDSWA_I ldswa [%r31, + 0x0058] %asi, %r8
.word 0xd0dfc032 ! 36: LDXA_R ldxa [%r31, %r18] 0x01, %r8
.word 0xb3800011 ! 37: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xe19fe1c0 ! 38: LDDFA_I ldda [%r31, 0x01c0], %f16
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100e0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 39: RDPC rd %pc, %r16
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0x95a209aa ! 40: FDIVs fdivs %f8, %f10, %f10
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0xa7508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe180 ! 43: LDXA_I ldxa [%r31, + 0x0180] %asi, %r19
.word 0x99a189a1 ! 44: FDIVs fdivs %f6, %f1, %f12
fblg,a,pn %fcc0, skip_10_25
.word 0xa1a509c9 ! 45: FDIVd fdivd %f20, %f40, %f16
.word 0x9d902000 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0000, %wstate
setx 0xa1b472e66b91a7a8, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0x87ab0a46 ! 48: FCMPd fcmpd %fcc<n>, %f12, %f6
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0x645368b8f7623f00, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3e0] %asi
.word 0x9d944010 ! 51: WRPR_WSTATE_R wrpr %r17, %r16, %wstate
.word 0xe63fe030 ! 52: STD_I std %r19, [%r31 + 0x0030]
.word 0xa781a83e ! 53: WR_GRAPHICS_STATUS_REG_I wr %r6, 0x083e, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x38800001 ! 1: BGU bgu,a <label_0x1>
.word 0x8d902abe ! 55: WRPR_PSTATE_I wrpr %r0, 0x0abe, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
stxa %r20, [%g0]0x54 ! I unsupported page size ..
.word 0x87aaca53 ! 57: FCMPd fcmpd %fcc<n>, %f42, %f50
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
.word 0xe8bfc02a ! 59: STDA_R stda %r20, [%r31 + %r10] 0x01
.word 0xe8cfe1a8 ! 60: LDSBA_I ldsba [%r31, + 0x01a8] %asi, %r20
.word 0xa3a509b0 ! 61: FDIVs fdivs %f20, %f16, %f17
.word 0x97410000 ! 62: RDTICK rd %tick, %r11
.word 0xd297c02d ! 63: LDUHA_R lduha [%r31, %r13] 0x01, %r9
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r6, [%r0+0x3e0] %asi
.word 0x9d948011 ! 64: WRPR_WSTATE_R wrpr %r18, %r17, %wstate
.word 0xd3e7c020 ! 65: CASA_I casa [%r31] 0x 1, %r0, %r9
setx fp_data_quads, %r19, %r20
.word 0x89a009c4 ! 66: FDIVd fdivd %f0, %f4, %f4
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_10_42-donret_10_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00658400 | (28 << 24)), %r13
wrhpr %g0, 0x1c43, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (10)
.word 0xd26fe1e3 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x01e3]
.word 0x91b507d0 ! 68: PDIST pdistn %d20, %d16, %d8
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe1a0 ! 71: LDXA_I ldxa [%r31, + 0x01a0] %asi, %r19
.word 0xe737e0f1 ! 72: STQF_I - %f19, [0x00f1, %r31]
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa1b207c4 ! 74: PDIST pdistn %d8, %d4, %d16
.word 0xd22fe137 ! 75: STB_I stb %r9, [%r31 + 0x0137]
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
.word 0x9194800d ! 77: WRPR_PIL_R wrpr %r18, %r13, %pil
.word 0xd3e7e012 ! 78: CASA_R casa [%r31] %asi, %r18, %r9
.word 0x91d02033 ! 79: Tcc_I ta icc_or_xcc, %r0 + 51
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0x153ff68237553918, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e130 ! 84: STQF_I - %f9, [0x0130, %r31]
set user_data_start, %r31
.word 0x8581f452 ! 85: WRCCR_I wr %r7, 0x1452, %ccr
.word 0x91d0001e ! 86: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0xdc2e0ebd727a68f9, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffff5d0fffff424, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd2800ba0 ! 92: LDUWA_R lduwa [%r0, %r0] 0x5d, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa7414000 ! 93: RDPC rd %pc, %r19
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe1e0 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x01e0]
.word 0xe09fc028 ! 94: LDDA_R ldda [%r31, %r8] 0x01, %r16
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r17, [%r0+0x3e0] %asi
.word 0x9d930008 ! 96: WRPR_WSTATE_R wrpr %r12, %r8, %wstate
.word 0xc19fd920 ! 97: LDDFA_R ldda [%r31, %r0], %f0
.word 0xc19fdb60 ! 98: LDDFA_R ldda [%r31, %r0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610060, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x93414000 ! 99: RDPC rd %pc, %r9
.word 0xdb37e0fa ! 100: STQF_I - %f13, [0x00fa, %r31]
.word 0xa9702fe8 ! 101: POPC_I popc 0x0fe8, %r20
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902004 ! 103: WRPR_CWP_I wrpr %r0, 0x0004, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 106: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x87acca49 ! 107: FCMPd fcmpd %fcc<n>, %f50, %f40
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0xed6a6e9ebab02557, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e00b ! 110: CASA_R casa [%r31] %asi, %r11, %r11
.word 0xc1bfe040 ! 111: STDFA_I stda %f0, [0x0040, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_10_72-donret_10_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x004cd600 | (16 << 24)), %r13
wrhpr %g0, 0x41d, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (10)
.word 0x27400001 ! 1: FBPUL fbul,a,pn %fcc0, <label_0x1>
.word 0xa9a409d0 ! 112: FDIVd fdivd %f16, %f16, %f20
.word 0xd3e7e010 ! 113: CASA_R casa [%r31] %asi, %r16, %r9
.word 0xe19fe1e0 ! 114: LDDFA_I ldda [%r31, 0x01e0], %f16
.word 0x8d9036cd ! 115: WRPR_PSTATE_I wrpr %r0, 0x16cd, %pstate
.word 0x87802083 ! 116: WRASI_I wr %r0, 0x0083, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_76) + 48, 16, 16)) -> intp(1,0,31)
setx 0xf21ea6f0853b3714, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xa5a489a3 ! 118: FDIVs fdivs %f18, %f3, %f18
.word 0x93d02033 ! 119: Tcc_I tne icc_or_xcc, %r0 + 51
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r1, [%r0+0x3c8] %asi
.word 0x9d940008 ! 120: WRPR_WSTATE_R wrpr %r16, %r8, %wstate
.word 0xc1bfe180 ! 121: STDFA_I stda %f0, [0x0180, %r31]
.word 0xc3eb0034 ! 122: PREFETCHA_R prefetcha [%r12, %r20] 0x01, #one_read
.word 0x8d802004 ! 123: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x2ac9c001 ! 1: BRNZ brnz,a,pt %r7,<label_0x9c001>
.word 0x819826b7 ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x06b7, %hpstate
.word 0xd11fc012 ! 125: LDDF_R ldd [%r31, %r18], %f8
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_10_83-donret_10_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00ca2a00 | (32 << 24)), %r13
wrhpr %g0, 0x1ed9, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (10)
.word 0x21400001 ! 1: FBPN fbn,a,pn %fcc0, <label_0x1>
.word 0x26cc0001 ! 126: BRLZ brlz,a,pt %r16,<label_0xc0001>
.word 0xd0bfc031 ! 127: STDA_R stda %r8, [%r31 + %r17] 0x01
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x8584b211 ! 130: WRCCR_I wr %r18, 0x1211, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
.word 0xc1bfe180 ! 132: STDFA_I stda %f0, [0x0180, %r31]
.word 0xa3a00166 ! 133: FABSq dis not found
.word 0xdad7e058 ! 134: LDSHA_I ldsha [%r31, + 0x0058] %asi, %r13
.word 0x93a449c5 ! 135: FDIVd fdivd %f48, %f36, %f40
setx fp_data_quads, %r19, %r20
.word 0x91a009a4 ! 136: FDIVs fdivs %f0, %f4, %f8
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0x95b08301 ! 137: ALIGNADDRESS alignaddr %r2, %r1, %r10
.word 0xe137e070 ! 138: STQF_I - %f16, [0x0070, %r31]
setx fp_data_quads, %r19, %r20
.word 0xc3e8273e ! 139: PREFETCHA_I prefetcha [%r0, + 0x073e] %asi, #one_read
.word 0x36800001 ! 1: BGE bge,a <label_0x1>
.word 0x8d903cf5 ! 140: WRPR_PSTATE_I wrpr %r0, 0x1cf5, %pstate
.word 0xa5b14492 ! 141: FCMPLE32 fcmple32 %d36, %d18, %r18
.word 0xa7a000c9 ! 142: FNEGd fnegd %f40, %f50
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x9bb187cc ! 143: PDIST pdistn %d6, %d12, %d44
.word 0x91d0001e ! 144: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x8584a96f ! 146: WRCCR_I wr %r18, 0x096f, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe7e7e011 ! 147: CASA_R casa [%r31] %asi, %r17, %r19
.word 0xa784c003 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r19, %r3, %-
.word 0xe637e0e6 ! 149: STH_I sth %r19, [%r31 + 0x00e6]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_98) + 40, 16, 16)) -> intp(4,0,4)
setx 0x2155ddce77765283, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0x02616b63abb65de4, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe6800b40 ! 152: LDUWA_R lduwa [%r0, %r0] 0x5a, %r19
.word 0xe62fe15f ! 153: STB_I stb %r19, [%r31 + 0x015f]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r18, [%r0+0x3c8] %asi
.word 0x9d91000a ! 154: WRPR_WSTATE_R wrpr %r4, %r10, %wstate
.word 0xa750c000 ! 155: RDPR_TT <illegal instruction>
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0x91b7c70b ! 1: FMULD8SUx16 fmuld8ulx16 %f31, %f11, %d8
.word 0xc19fc3e0 ! 157: LDDFA_R ldda [%r31, %r0], %f0
tsubcctv %r19, 0x10d7, %r16
.word 0xd407e05c ! 158: LDUW_I lduw [%r31 + 0x005c], %r10
.word 0xaf800011 ! 159: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c034 ! 160: CASA_I casa [%r31] 0x 1, %r20, %r10
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x24cfc001 ! 161: BRLEZ brlez,a,pt %r31,<label_0xfc001>
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610020, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa3414000 ! 162: RDPC rd %pc, %r17
.word 0x2a800001 ! 1: BCS bcs,a <label_0x1>
.word 0x8198398b ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x198b, %hpstate
mov 0x20, %r1 ! (VA for ASI 0x5a)
.word 0xd4d04b40 ! 164: LDSHA_R ldsha [%r1, %r0] 0x5a, %r10
.word 0xc1bfe020 ! 165: STDFA_I stda %f0, [0x0020, %r31]
.word 0x81983cd6 ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x1cd6, %hpstate
.word 0x93d0001e ! 167: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x8d802000 ! 168: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xd43fe119 ! 169: STD_I std %r10, [%r31 + 0x0119]
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
.word 0xe19fdf20 ! 173: LDDFA_R ldda [%r31, %r0], %f16
.word 0xd51fe000 ! 174: LDDF_I ldd [%r31, 0x0000], %f10
.word 0xd44fe048 ! 175: LDSB_I ldsb [%r31 + 0x0048], %r10
.word 0x9194800d ! 176: WRPR_PIL_R wrpr %r18, %r13, %pil
mov 0x0, %r1 ! (VA for ASI 0x4c)
.word 0xd4d04980 ! 177: LDSHA_R ldsha [%r1, %r0] 0x4c, %r10
setx 0xfd8b8390a1d93c08, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xc1bfe020 ! 179: STDFA_I stda %f0, [0x0020, %r31]
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100a0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa5414000 ! 181: RDPC rd %pc, %r18
.word 0xb3800011 ! 182: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx 0x5c7ec9eadd2b7c11, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe1b8 ! 184: LDXA_I ldxa [%r31, + 0x01b8] %asi, %r16
setx 0x4b549685cb1180dc, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_10_120) + 48, 16, 16)) -> intp(2,0,31)
setx 0xa56892bc94cb678a, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa1b407c4 ! 187: PDIST pdistn %d16, %d4, %d16
.word 0x83d0001e ! 188: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0xa7820007 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r8, %r7, %-
.word 0xda97e008 ! 190: LDUHA_I lduha [%r31, + 0x0008] %asi, %r13
.word 0x879b317e ! 191: WRHPR_HINTP_I wrhpr %r12, 0x117e, %hintp
.word 0x91d020b4 ! 192: Tcc_I ta icc_or_xcc, %r0 + 180
.word 0xa781c004 ! 193: WR_GRAPHICS_STATUS_REG_R wr %r7, %r4, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x87a98a52 ! 194: FCMPd fcmpd %fcc<n>, %f6, %f18
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c031 ! 1: CASA_I casa [%r31] 0x 1, %r17, %r9
.word 0xd3e7e011 ! 195: CASA_R casa [%r31] %asi, %r17, %r9
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x9f80222c ! 197: SIR sir 0x022c
set user_data_start, %r31
.word 0x8584a43a ! 198: WRCCR_I wr %r18, 0x043a, %ccr
.word 0xe19fc3e0 ! 199: LDDFA_R ldda [%r31, %r0], %f16
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0d04e60 ! 200: LDSHA_R ldsha [%r1, %r0] 0x73, %r16
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
ta T_CHANGE_NONHPRIV ! macro
setx join_lbl_0_0, %g1, %g2
.word 0xe08008a0 ! 1: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0xe19fdf20 ! 2: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe08008a0 ! 3: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802004 ! 5: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x3f400001 ! 1: FBPO fbo,a,pn %fcc0, <label_0x1>
.word 0x8d9033ce ! 6: WRPR_PSTATE_I wrpr %r0, 0x13ce, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_2) + 16, 16, 16)) -> intp(3,0,11)
setx 0x873bc2ffa4dc00db, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa7840012 ! 12: WR_GRAPHICS_STATUS_REG_R wr %r16, %r18, %-
setx fp_data_quads, %r19, %r20
.word 0x91a009a4 ! 13: FDIVs fdivs %f0, %f4, %f8
.word 0x93d0001e ! 14: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x879c400c ! 15: WRHPR_HINTP_R wrhpr %r17, %r12, %hintp
.word 0xa1703467 ! 16: POPC_I popc 0x1467, %r16
.word 0x8780208a ! 17: WRASI_I wr %r0, 0x008a, %asi
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_6
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_6
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_6
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xa7b4848b ! 18: FCMPLE32 fcmple32 %d18, %d42, %r19
.word 0x9ba00170 ! 19: FABSq dis not found
.word 0xe49fe0b8 ! 20: LDDA_I ldda [%r31, + 0x00b8] %asi, %r18
.word 0xe44fe1d0 ! 21: LDSB_I ldsb [%r31 + 0x01d0], %r18
.word 0x8584eba3 ! 22: WRCCR_I wr %r19, 0x0ba3, %ccr
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610030, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 24: RDPC rd %pc, %r16
.word 0x8d903a8a ! 25: WRPR_PSTATE_I wrpr %r0, 0x1a8a, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa1702090 ! 1: POPC_I popc 0x0090, %r16
.word 0x87ac8a4d ! 26: FCMPd fcmpd %fcc<n>, %f18, %f44
setx 0x2e1c9b9d88028234, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xb3800011 ! 29: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7d3 ! 1: PDIST pdistn %d62, %d50, %d20
.word 0x93a089aa ! 30: FDIVs fdivs %f2, %f10, %f9
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xd11fc008 ! 33: LDDF_R ldd [%r31, %r8], %f8
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e190 ! 35: LDSWA_I ldswa [%r31, + 0x0190] %asi, %r8
.word 0xd0dfc034 ! 36: LDXA_R ldxa [%r31, %r20] 0x01, %r8
.word 0xaf800011 ! 37: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xe19fe0a0 ! 38: LDDFA_I ldda [%r31, 0x00a0], %f16
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610040, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa3414000 ! 39: RDPC rd %pc, %r17
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0x9ba089b3 ! 40: FDIVs fdivs %f2, %f19, %f13
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0x93508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe098 ! 43: LDXA_I ldxa [%r31, + 0x0098] %asi, %r19
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_24
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_24
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_24
ldxa [0x50]%asi, %r14 !Running_rw
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0x99b28482 ! 44: FCMPLE32 fcmple32 %d10, %d2, %r12
.word 0xc36cbc29 ! 45: PREFETCH_I prefetch [%r18 + 0xfffffc29], #one_read
.word 0x9d902003 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0003, %wstate
setx 0x9f0a55e5dc840f57, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0x9ba309b1 ! 48: FDIVs fdivs %f12, %f17, %f13
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0x32360dbf98097d70, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r17, [%r0+0x3e0] %asi
.word 0x9d94c010 ! 51: WRPR_WSTATE_R wrpr %r19, %r16, %wstate
.word 0xe63fe050 ! 52: STD_I std %r19, [%r31 + 0x0050]
.word 0xa7846d7b ! 53: WR_GRAPHICS_STATUS_REG_I wr %r17, 0x0d7b, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x37400001 ! 1: FBPGE fbge,a,pn %fcc0, <label_0x1>
.word 0x8d902611 ! 55: WRPR_PSTATE_I wrpr %r0, 0x0611, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
stxa %r20, [%g0]0x54 ! I unsupported page size ..
.word 0x87a94a46 ! 57: FCMPd fcmpd %fcc<n>, %f36, %f6
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
.word 0xe8bfc034 ! 59: STDA_R stda %r20, [%r31 + %r20] 0x01
.word 0xe8cfe060 ! 60: LDSBA_I ldsba [%r31, + 0x0060] %asi, %r20
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_36
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_36
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_36
ldxa [0x50]%asi, %r14 !Running_rw
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xa3b187d3 ! 61: PDIST pdistn %d6, %d50, %d48
.word 0xa1410000 ! 62: RDTICK rd %tick, %r16
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_38
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_38
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_38
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xd3e7e014 ! 63: CASA_R casa [%r31] %asi, %r20, %r9
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r17, [%r0+0x3e8] %asi
.word 0x9d950014 ! 64: WRPR_WSTATE_R wrpr %r20, %r20, %wstate
.word 0xd23fc000 ! 65: STD_R std %r9, [%r31 + %r0]
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 66: FCMPd fcmpd %fcc<n>, %f0, %f4
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_8_42-donret_8_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x002f4d00 | (0x83 << 24)), %r13
wrhpr %g0, 0x15ce, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (8)
.word 0xd26fe055 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x0055]
.word 0xa1a449b1 ! 68: FDIVs fdivs %f17, %f17, %f16
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe1a8 ! 71: LDXA_I ldxa [%r31, + 0x01a8] %asi, %r19
.word 0xe737e0a8 ! 72: STQF_I - %f19, [0x00a8, %r31]
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x97b507d2 ! 74: PDIST pdistn %d20, %d18, %d42
.word 0xd22fe0f7 ! 75: STB_I stb %r9, [%r31 + 0x00f7]
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
.word 0x9190c004 ! 77: WRPR_PIL_R wrpr %r3, %r4, %pil
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_47
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_47
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_47
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xd31fe1e0 ! 78: LDDF_I ldd [%r31, 0x01e0], %f9
.word 0x93d02032 ! 79: Tcc_I tne icc_or_xcc, %r0 + 50
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x00000000003a0000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0xfc30ea0a6a3887bc, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e04a ! 84: STQF_I - %f9, [0x004a, %r31]
set user_data_start, %r31
.word 0x8581201a ! 85: WRCCR_I wr %r4, 0x001a, %ccr
.word 0x83d0001e ! 86: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0xe0b2c2274147251f, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffffa4efffff001, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd2800c60 ! 92: LDUWA_R lduwa [%r0, %r0] 0x63, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610070, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x9b414000 ! 93: RDPC rd %pc, %r13
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe0f0 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x00f0]
.word 0xe09fe000 ! 94: LDDA_I ldda [%r31, + 0x0000] %asi, %r16
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r5, [%r0+0x3c8] %asi
.word 0x9d920005 ! 96: WRPR_WSTATE_R wrpr %r8, %r5, %wstate
.word 0xe19fe000 ! 97: LDDFA_I ldda [%r31, 0x0000], %f16
.word 0xc19fd920 ! 98: LDDFA_R ldda [%r31, %r0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x91414000 ! 99: RDPC rd %pc, %r8
.word 0xdb37e09c ! 100: STQF_I - %f13, [0x009c, %r31]
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_62
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_62
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_62
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0x91a289a3 ! 101: FDIVs fdivs %f10, %f3, %f8
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902005 ! 103: WRPR_CWP_I wrpr %r0, 0x0005, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x8da009a4 ! 106: FDIVs fdivs %f0, %f4, %f6
.word 0xa5a309b1 ! 107: FDIVs fdivs %f12, %f17, %f18
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0x21fb51e43fba7450, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e013 ! 110: CASA_R casa [%r31] %asi, %r19, %r11
.word 0xe1bfe180 ! 111: STDFA_I stda %f16, [0x0180, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_8_72-donret_8_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x1500 | (28 << 24)), %r13
wrhpr %g0, 0xb97, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (8)
.word 0x34800001 ! 1: BG bg,a <label_0x1>
.word 0x97a509d0 ! 112: FDIVd fdivd %f20, %f16, %f42
.word 0xd31fe060 ! 113: LDDF_I ldd [%r31, 0x0060], %f9
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_74
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_74
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_74
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000000e1200000, %r20, %r19)
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xe19fdf20 ! 114: LDDFA_R ldda [%r31, %r0], %f16
.word 0x8d90292f ! 115: WRPR_PSTATE_I wrpr %r0, 0x092f, %pstate
.word 0x87802082 ! 116: WRASI_I wr %r0, 0x0082, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_76) + 48, 16, 16)) -> intp(1,0,22)
setx 0xdf2013c9df9adf58, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xa7a409c5 ! 118: FDIVd fdivd %f16, %f36, %f50
.word 0x91d02032 ! 119: Tcc_I ta icc_or_xcc, %r0 + 50
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r11, [%r0+0x3c0] %asi
.word 0x9d908001 ! 120: WRPR_WSTATE_R wrpr %r2, %r1, %wstate
.word 0xe19fe100 ! 121: LDDFA_I ldda [%r31, 0x0100], %f16
.word 0xa1702f2f ! 122: POPC_I popc 0x0f2f, %r16
.word 0x8d802000 ! 123: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x22cc4001 ! 1: BRZ brz,a,pt %r17,<label_0xc4001>
.word 0x819836cd ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x16cd, %hpstate
.word 0xd13fc009 ! 125: STDF_R std %f8, [%r9, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_8_83-donret_8_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00e98e00 | (20 << 24)), %r13
wrhpr %g0, 0x9cb, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (8)
.word 0x22800001 ! 1: BE be,a <label_0x1>
.word 0x3c800001 ! 126: BPOS bpos,a <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_84
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_84
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_84
ldxa [0x50]%asi, %r14 !Running_rw
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xd09fc033 ! 127: LDDA_R ldda [%r31, %r19] 0x01, %r8
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x85847284 ! 130: WRCCR_I wr %r17, 0x1284, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
.word 0xe19fde00 ! 132: LDDFA_R ldda [%r31, %r0], %f16
.word 0xa9a00174 ! 133: FABSq dis not found
.word 0xdad7e130 ! 134: LDSHA_I ldsha [%r31, + 0x0130] %asi, %r13
.word 0x39400001 ! 135: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x91a009a4 ! 136: FDIVs fdivs %f0, %f4, %f8
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xa3b44311 ! 137: ALIGNADDRESS alignaddr %r17, %r17, %r17
.word 0xe137e05a ! 138: STQF_I - %f16, [0x005a, %r31]
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 139: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x27400001 ! 1: FBPUL fbul,a,pn %fcc0, <label_0x1>
.word 0x8d90382e ! 140: WRPR_PSTATE_I wrpr %r0, 0x182e, %pstate
.word 0xc3ec8022 ! 141: PREFETCHA_R prefetcha [%r18, %r2] 0x01, #one_read
.word 0x9ba000cb ! 142: FNEGd fnegd %f42, %f44
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x95b487d2 ! 143: PDIST pdistn %d18, %d18, %d10
.word 0x83d0001e ! 144: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x8584275f ! 146: WRCCR_I wr %r16, 0x075f, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe6dfc033 ! 147: LDXA_R ldxa [%r31, %r19] 0x01, %r19
.word 0xa7808013 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r2, %r19, %-
.word 0xe637e0b8 ! 149: STH_I sth %r19, [%r31 + 0x00b8]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_98) + 40, 16, 16)) -> intp(0,0,26)
setx 0x85373312c419a067, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0x7c0570486605b9d5, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe6800bc0 ! 152: LDUWA_R lduwa [%r0, %r0] 0x5e, %r19
.word 0xe62fe02a ! 153: STB_I stb %r19, [%r31 + 0x002a]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r13, [%r0+0x3c0] %asi
.word 0x9d94c010 ! 154: WRPR_WSTATE_R wrpr %r19, %r16, %wstate
.word 0x9b50c000 ! 155: RDPR_TT <illegal instruction>
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0xe3148009 ! 1: LDQF_R - [%r18, %r9], %f17
.word 0xc1bfd920 ! 157: STDFA_R stda %f0, [%r0, %r31]
tsubcctv %r19, 0x12c0, %r2
.word 0xd407e054 ! 158: LDUW_I lduw [%r31 + 0x0054], %r10
.word 0xaf800011 ! 159: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c031 ! 160: CASA_I casa [%r31] 0x 1, %r17, %r10
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87afca51 ! 161: FCMPd fcmpd %fcc<n>, %f62, %f48
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610060, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa7414000 ! 162: RDPC rd %pc, %r19
.word 0x36800001 ! 1: BGE bge,a <label_0x1>
.word 0x81982dc4 ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x0dc4, %hpstate
mov 0x8, %r1 ! (VA for ASI 0x5a)
.word 0xd4c04b40 ! 164: LDSWA_R ldswa [%r1, %r0] 0x5a, %r10
.word 0xe1bfe080 ! 165: STDFA_I stda %f16, [0x0080, %r31]
.word 0x8198355d ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x155d, %hpstate
.word 0x91d0001e ! 167: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x8d802000 ! 168: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xd43fe020 ! 169: STD_I std %r10, [%r31 + 0x0020]
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_111
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_111
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_111
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xe1bfdb60 ! 173: STDFA_R stda %f16, [%r0, %r31]
.word 0xd51fe168 ! 174: LDDF_I ldd [%r31, 0x0168], %f10
.word 0xd44fe100 ! 175: LDSB_I ldsb [%r31 + 0x0100], %r10
.word 0x91924011 ! 176: WRPR_PIL_R wrpr %r9, %r17, %pil
mov 0x10, %r1 ! (VA for ASI 0x4c)
.word 0xd4d04980 ! 177: LDSHA_R ldsha [%r1, %r0] 0x4c, %r10
setx 0xf4a6c275e792f059, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xc19fe000 ! 179: LDDFA_I ldda [%r31, 0x0000], %f0
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 181: RDPC rd %pc, %r16
.word 0xb3800011 ! 182: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx 0xdb0450b78dcbb1ed, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe0a0 ! 184: LDXA_I ldxa [%r31, + 0x00a0] %asi, %r16
setx 0x1442cbfd995c1bc2, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_8_120) + 8, 16, 16)) -> intp(3,0,13)
setx 0xd6411c2f9f5b8a7c, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x9bb447d4 ! 187: PDIST pdistn %d48, %d20, %d44
.word 0x91d0001e ! 188: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xa7844014 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r17, %r20, %-
.word 0xda97e040 ! 190: LDUHA_I lduha [%r31, + 0x0040] %asi, %r13
.word 0x879ce921 ! 191: WRHPR_HINTP_I wrhpr %r19, 0x0921, %hintp
.word 0x83d02035 ! 192: Tcc_I te icc_or_xcc, %r0 + 53
.word 0xa781c00c ! 193: WR_GRAPHICS_STATUS_REG_R wr %r7, %r12, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x91a289a8 ! 194: FDIVs fdivs %f10, %f8, %f8
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c031 ! 1: CASA_I casa [%r31] 0x 1, %r17, %r9
.word 0xd29fc034 ! 195: LDDA_R ldda [%r31, %r20] 0x01, %r9
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xa3b247d4 ! 197: PDIST pdistn %d40, %d20, %d48
set user_data_start, %r31
.word 0x8584a624 ! 198: WRCCR_I wr %r18, 0x0624, %ccr
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_iaw_8_127
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_8_127
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_iaw_8_127
ldxa [0x50]%asi, %r14 !Running_rw
setx common_target, %r20, %r19
stxa %r16, [0x60] %asi ! Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi ! restore %asi
.word 0xe19fe160 ! 199: LDDFA_I ldda [%r31, 0x0160], %f16
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0904e60 ! 200: LDUHA_R lduha [%r1, %r0] 0x73, %r16
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONHPRIV ! macro
setx join_lbl_0_0, %g1, %g2
.word 0xe08008a0 ! 1: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0xe19fda00 ! 2: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe0800b20 ! 3: LDUWA_R lduwa [%r0, %r0] 0x59, %r16
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802000 ! 5: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x22c98001 ! 1: BRZ brz,a,pt %r6,<label_0x98001>
.word 0x8d90359d ! 6: WRPR_PSTATE_I wrpr %r0, 0x159d, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_2) + 8, 16, 16)) -> intp(6,0,12)
setx 0xf9022915486c79ce, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa7814008 ! 12: WR_GRAPHICS_STATUS_REG_R wr %r5, %r8, %-
setx fp_data_quads, %r19, %r20
.word 0xc3e8366f ! 13: PREFETCHA_I prefetcha [%r0, + 0xfffff66f] %asi, #one_read
.word 0x91d0001e ! 14: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x879a800a ! 15: WRHPR_HINTP_R wrhpr %r10, %r10, %hintp
.word 0x95703fd4 ! 16: POPC_I popc 0x1fd4, %r10
.word 0x87802058 ! 17: WRASI_I wr %r0, 0x0058, %asi
.word 0xa5a1c9a9 ! 18: FDIVs fdivs %f7, %f9, %f18
.word 0xa5a00169 ! 19: FABSq dis not found
.word 0xe49fe000 ! 20: LDDA_I ldda [%r31, + 0x0000] %asi, %r18
.word 0xe44fe0e0 ! 21: LDSB_I ldsb [%r31 + 0x00e0], %r18
.word 0x85806023 ! 22: WRCCR_I wr %r1, 0x0023, %ccr
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610010, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x91414000 ! 24: RDPC rd %pc, %r8
.word 0x8d9029db ! 25: WRPR_PSTATE_I wrpr %r0, 0x09db, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa1702020 ! 1: POPC_I popc 0x0020, %r16
.word 0xa7a309d0 ! 26: FDIVd fdivd %f12, %f16, %f50
setx 0x0154e99635e15282, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xaf800011 ! 29: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7d1 ! 1: PDIST pdistn %d62, %d48, %d20
.word 0x87a9ca54 ! 30: FCMPd fcmpd %fcc<n>, %f38, %f20
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_18
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_18
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_18
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050d0c00e5b,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xd1e7e012 ! 33: CASA_R casa [%r31] %asi, %r18, %r8
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e1d8 ! 35: LDSWA_I ldswa [%r31, + 0x01d8] %asi, %r8
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_19
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_19
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_19
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x0000004099ce5b7c,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xc32fc012 ! 36: STXFSR_R st-sfr %f1, [%r18, %r31]
.word 0xb3800011 ! 37: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xc19fe0a0 ! 38: LDDFA_I ldda [%r31, 0x00a0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610050, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa5414000 ! 39: RDPC rd %pc, %r18
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0xa3b2c48a ! 40: FCMPLE32 fcmple32 %d42, %d10, %r17
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0x91508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe168 ! 43: LDXA_I ldxa [%r31, + 0x0168] %asi, %r19
.word 0x93a489d1 ! 44: FDIVd fdivd %f18, %f48, %f40
.word 0xc3686eb9 ! 45: PREFETCH_I prefetch [%r1 + 0x0eb9], #one_read
.word 0x9d902005 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0005, %wstate
setx 0x2329f954f38dfa3a, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0xa5b44490 ! 48: FCMPLE32 fcmple32 %d48, %d16, %r18
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0xc8ec7450355b0864, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r13, [%r0+0x3c0] %asi
.word 0x9d914012 ! 51: WRPR_WSTATE_R wrpr %r5, %r18, %wstate
.word 0xe63fe071 ! 52: STD_I std %r19, [%r31 + 0x0071]
.word 0xa780797d ! 53: WR_GRAPHICS_STATUS_REG_I wr %r1, 0x197d, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x3c800001 ! 1: BPOS bpos,a <label_0x1>
.word 0x8d903508 ! 55: WRPR_PSTATE_I wrpr %r0, 0x1508, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
stxa %r20, [%g0]0x54 ! I unsupported page size ..
.word 0xa1a489aa ! 57: FDIVs fdivs %f18, %f10, %f16
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_35
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_35
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_35
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050f0db7c7a,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xe89fc02d ! 59: LDDA_R ldda [%r31, %r13] 0x01, %r20
.word 0xe8cfe178 ! 60: LDSBA_I ldsba [%r31, + 0x0178] %asi, %r20
.word 0x87a98a52 ! 61: FCMPd fcmpd %fcc<n>, %f6, %f18
.word 0x95410000 ! 62: RDTICK rd %tick, %r10
.word 0xd2dfc02d ! 63: LDXA_R ldxa [%r31, %r13] 0x01, %r9
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r7, [%r0+0x3d0] %asi
.word 0x9d920011 ! 64: WRPR_WSTATE_R wrpr %r8, %r17, %wstate
.word 0xc36fe14d ! 65: PREFETCH_I prefetch [%r31 + 0x014d], #one_read
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 66: FCMPd fcmpd %fcc<n>, %f0, %f4
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_4_42-donret_4_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x008bf800 | (0x80 << 24)), %r13
wrhpr %g0, 0x1f74, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (4)
.word 0xd26fe1a5 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x01a5]
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_43
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_43
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_43
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x0000004002fc7aa0,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xa5a289b3 ! 68: FDIVs fdivs %f10, %f19, %f18
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe078 ! 71: LDXA_I ldxa [%r31, + 0x0078] %asi, %r19
.word 0xe737e1f1 ! 72: STQF_I - %f19, [0x01f1, %r31]
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa7b087d4 ! 74: PDIST pdistn %d2, %d20, %d50
.word 0xd22fe180 ! 75: STB_I stb %r9, [%r31 + 0x0180]
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
.word 0x9193400c ! 77: WRPR_PIL_R wrpr %r13, %r12, %pil
.word 0xd2bfc02c ! 78: STDA_R stda %r9, [%r31 + %r12] 0x01
.word 0x93d02033 ! 79: Tcc_I tne icc_or_xcc, %r0 + 51
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x0000000400380000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0xe7880972600a6208, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e160 ! 84: STQF_I - %f9, [0x0160, %r31]
set user_data_start, %r31
.word 0x85817319 ! 85: WRCCR_I wr %r5, 0x1319, %ccr
.word 0x93d0001e ! 86: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0xbcec3ee8a5f7afa8, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffff719fffff072, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd2800a80 ! 92: LDUWA_R lduwa [%r0, %r0] 0x54, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100f0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x99414000 ! 93: RDPC rd %pc, %r12
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe1f0 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x01f0]
.word 0xe11fc011 ! 94: LDDF_R ldd [%r31, %r17], %f16
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r16, [%r0+0x3c8] %asi
.word 0x9d914014 ! 96: WRPR_WSTATE_R wrpr %r5, %r20, %wstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_60
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_60
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_60
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x000000402cfaa0f7,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xc1bfde00 ! 97: STDFA_R stda %f0, [%r0, %r31]
.word 0xe19fc2c0 ! 98: LDDFA_R ldda [%r31, %r0], %f16
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100d0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x99414000 ! 99: RDPC rd %pc, %r12
.word 0xdb37e174 ! 100: STQF_I - %f13, [0x0174, %r31]
.word 0xa1a049a5 ! 101: FDIVs fdivs %f1, %f5, %f16
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902001 ! 103: WRPR_CWP_I wrpr %r0, 0x0001, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x89a009a4 ! 106: FDIVs fdivs %f0, %f4, %f4
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_68
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_68
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_68
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040d9e0f7b7,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xa9a4c9d3 ! 107: FDIVd fdivd %f50, %f50, %f20
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0x77abbaa2aadd7513, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e011 ! 110: CASA_R casa [%r31] %asi, %r17, %r11
.word 0xc1bfe0e0 ! 111: STDFA_I stda %f0, [0x00e0, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_4_72-donret_4_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x00422500 | (32 << 24)), %r13
wrhpr %g0, 0x171f, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (4)
.word 0x29400001 ! 1: FBPL fbl,a,pn %fcc0, <label_0x1>
.word 0x9ba2c9d0 ! 112: FDIVd fdivd %f42, %f16, %f44
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_73
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_73
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_73
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050a3f7b7e4,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xd23fe080 ! 113: STD_I std %r9, [%r31 + 0x0080]
.word 0xc1bfe1c0 ! 114: STDFA_I stda %f0, [0x01c0, %r31]
.word 0x8d9038ef ! 115: WRPR_PSTATE_I wrpr %r0, 0x18ef, %pstate
.word 0x8780208b ! 116: WRASI_I wr %r0, 0x008b, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_76) + 0, 16, 16)) -> intp(0,0,21)
setx 0xfec32658d7f71aa3, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_77
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_77
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_77
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040d0f7e476,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xa3b4c493 ! 118: FCMPLE32 fcmple32 %d50, %d50, %r17
.word 0x93d02033 ! 119: Tcc_I tne icc_or_xcc, %r0 + 51
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3c0] %asi
.word 0x9d940010 ! 120: WRPR_WSTATE_R wrpr %r16, %r16, %wstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_79
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_79
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_79
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050d6e476cd,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xe1bfda00 ! 121: STDFA_R stda %f16, [%r0, %r31]
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_80
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_80
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_80
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050a4f6cd3f,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0x87acca51 ! 122: FCMPd fcmpd %fcc<n>, %f50, %f48
.word 0x8d802004 ! 123: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x24800001 ! 1: BLE ble,a <label_0x1>
.word 0x81983b3d ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x1b3d, %hpstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_82
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_82
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_82
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040becd3f62,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xd13fc012 ! 125: STDF_R std %f8, [%r18, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_4_83-donret_4_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x000c9200 | (0x58 << 24)), %r13
wrhpr %g0, 0x8e5, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (4)
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x23400001 ! 126: FBPNE fbne,a,pn %fcc0, <label_0x1>
.word 0xd09fc02a ! 127: LDDA_R ldda [%r31, %r10] 0x01, %r8
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x85842477 ! 130: WRCCR_I wr %r16, 0x0477, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_86
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_86
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_86
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000040e5ff62fd,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xc1bfd920 ! 132: STDFA_R stda %f0, [%r0, %r31]
.word 0xa5a0016a ! 133: FABSq dis not found
.word 0xdad7e1e8 ! 134: LDSHA_I ldsha [%r31, + 0x01e8] %asi, %r13
.word 0x39400001 ! 135: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x8da009a4 ! 136: FDIVs fdivs %f0, %f4, %f6
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xa9b14312 ! 137: ALIGNADDRESS alignaddr %r5, %r18, %r20
.word 0xe137e16c ! 138: STQF_I - %f16, [0x016c, %r31]
setx fp_data_quads, %r19, %r20
.word 0xc3e8273e ! 139: PREFETCHA_I prefetcha [%r0, + 0x073e] %asi, #one_read
.word 0x33400001 ! 1: FBPE fbe,a,pn %fcc0, <label_0x1>
.word 0x8d903591 ! 140: WRPR_PSTATE_I wrpr %r0, 0x1591, %pstate
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_93
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_93
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_93
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x000000503ee2fdf4,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xa570394d ! 141: POPC_I popc 0x194d, %r18
.word 0xa9a000d2 ! 142: FNEGd fnegd %f18, %f20
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa1b487c6 ! 143: PDIST pdistn %d18, %d6, %d16
.word 0x91d0001e ! 144: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x8584ec62 ! 146: WRCCR_I wr %r19, 0x0c62, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe6bfc029 ! 147: STDA_R stda %r19, [%r31 + %r9] 0x01
.word 0xa780c011 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r3, %r17, %-
.word 0xe637e132 ! 149: STH_I sth %r19, [%r31 + 0x0132]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_98) + 8, 16, 16)) -> intp(4,0,3)
setx 0x6ba502414ded985a, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0x85b7a9dd4d6ba59a, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe6800b80 ! 152: LDUWA_R lduwa [%r0, %r0] 0x5c, %r19
.word 0xe62fe0ca ! 153: STB_I stb %r19, [%r31 + 0x00ca]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r19, [%r0+0x3e8] %asi
.word 0x9d94c010 ! 154: WRPR_WSTATE_R wrpr %r19, %r16, %wstate
.word 0x9550c000 ! 155: RDPR_TT <illegal instruction>
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0x91b7c70a ! 1: FMULD8SUx16 fmuld8ulx16 %f31, %f10, %d8
.word 0xe1bfe040 ! 157: STDFA_I stda %f16, [0x0040, %r31]
tsubcctv %r16, 0x1543, %r9
.word 0xd407e08c ! 158: LDUW_I lduw [%r31 + 0x008c], %r10
.word 0xb3800011 ! 159: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c031 ! 160: CASA_I casa [%r31] 0x 1, %r17, %r10
.word 0x26c88001 ! 1: BRLZ brlz,a,pt %r2,<label_0x88001>
.word 0x95b7c4c9 ! 161: FCMPNE32 fcmpne32 %d62, %d40, %r10
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610050, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x99414000 ! 162: RDPC rd %pc, %r12
.word 0x38800001 ! 1: BGU bgu,a <label_0x1>
.word 0x81982d4d ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x0d4d, %hpstate
mov 0x0, %r1 ! (VA for ASI 0x5a)
.word 0xd4884b40 ! 164: LDUBA_R lduba [%r1, %r0] 0x5a, %r10
.word 0xe1bfe040 ! 165: STDFA_I stda %f16, [0x0040, %r31]
.word 0x8198358f ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x158f, %hpstate
.word 0x93d0001e ! 167: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x8d802000 ! 168: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xd43fe1c8 ! 169: STD_I std %r10, [%r31 + 0x01c8]
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
.word 0xc1bfdb60 ! 173: STDFA_R stda %f0, [%r0, %r31]
.word 0xd51fe0c8 ! 174: LDDF_I ldd [%r31, 0x00c8], %f10
.word 0xd44fe1d8 ! 175: LDSB_I ldsb [%r31 + 0x01d8], %r10
.word 0x91930011 ! 176: WRPR_PIL_R wrpr %r12, %r17, %pil
mov 0x10, %r1 ! (VA for ASI 0x4c)
.word 0xd4c04980 ! 177: LDSWA_R ldswa [%r1, %r0] 0x4c, %r10
setx 0x095dec9c3a4abbf3, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter4, %r23
and %r8, 0x38, %r8 ! Core ID
cas [%r23],%g0,%r16 !lock
brz,a %r16, continue_ibp_4_115
sllx %r16, %r8, %r16 !Mask for my core only
ldxa [0x58]%asi, %r17 !Running_status
ldxa [0x50]%asi, %r13 !Running_rw
bne,a %xcc, wait_for_stat_4_115
ldxa [0x58]%asi, %r17 !Running_status
stxa %r16, [0x68]%asi !Park (W1C)
ldxa [0x50]%asi, %r14 !Running_rw
ldxa [0x58]%asi, %r17 !Running_status
bne,a %xcc, wait_for_ibp_4_115
ldxa [0x50]%asi, %r14 !Running_rw
best_set_reg(0x00000050b8fdf4b9,%r19, %r20)
stxa %r16, [0x60] %asi !Unpark (W1S)
st %g0, [%r23] !clear lock
wr %r0, %r12, %asi !restore %asi
.word 0xc19fdf20 ! 179: LDDFA_R ldda [%r31, %r0], %f0
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa3414000 ! 181: RDPC rd %pc, %r17
.word 0xb3800011 ! 182: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx 0xf328ca06fab28c5e, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe170 ! 184: LDXA_I ldxa [%r31, + 0x0170] %asi, %r16
setx 0xc3695fcfd4e2f50e, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_4_120) + 24, 16, 16)) -> intp(0,0,21)
setx 0xd546744c3377672d, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa3b407c7 ! 187: PDIST pdistn %d16, %d38, %d48
.word 0x91d0001e ! 188: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xa7844006 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r17, %r6, %-
.word 0xda97e158 ! 190: LDUHA_I lduha [%r31, + 0x0158] %asi, %r13
.word 0x879c2573 ! 191: WRHPR_HINTP_I wrhpr %r16, 0x0573, %hintp
.word 0x83d020b4 ! 192: Tcc_I te icc_or_xcc, %r0 + 180
.word 0xa7810006 ! 193: WR_GRAPHICS_STATUS_REG_R wr %r4, %r6, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x97b18481 ! 194: FCMPLE32 fcmple32 %d6, %d32, %r11
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c030 ! 1: CASA_I casa [%r31] 0x 1, %r16, %r9
.word 0xd33fc014 ! 195: STDF_R std %f9, [%r20, %r31]
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x87a90a46 ! 197: FCMPd fcmpd %fcc<n>, %f4, %f6
set user_data_start, %r31
.word 0x8580bf35 ! 198: WRCCR_I wr %r2, 0x1f35, %ccr
.word 0xc19fdb60 ! 199: LDDFA_R ldda [%r31, %r0], %f0
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0d84e60 ! 200: LDXA_R ldxa [%r1, %r0] 0x73, %r16
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONHPRIV ! macro
setx join_lbl_0_0, %g1, %g2
.word 0xe08008a0 ! 1: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0xe19fde00 ! 2: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe08008a0 ! 3: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802000 ! 5: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0x21400001 ! 1: FBPN fbn,a,pn %fcc0, <label_0x1>
.word 0x8d9031ef ! 6: WRPR_PSTATE_I wrpr %r0, 0x11ef, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_2) + 48, 16, 16)) -> intp(6,0,27)
setx 0x70fc39ac9a3a3da7, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa7850001 ! 12: WR_GRAPHICS_STATUS_REG_R wr %r20, %r1, %-
setx fp_data_quads, %r19, %r20
.word 0x89a009a4 ! 13: FDIVs fdivs %f0, %f4, %f4
.word 0x93d0001e ! 14: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x879b4012 ! 15: WRHPR_HINTP_R wrhpr %r13, %r18, %hintp
.word 0x977020fa ! 16: POPC_I popc 0x00fa, %r11
.word 0x87802058 ! 17: WRASI_I wr %r0, 0x0058, %asi
.word 0x95702c74 ! 18: POPC_I popc 0x0c74, %r10
.word 0xa1a00170 ! 19: FABSq dis not found
.word 0xe49fe178 ! 20: LDDA_I ldda [%r31, + 0x0178] %asi, %r18
.word 0xe44fe0b8 ! 21: LDSB_I ldsb [%r31 + 0x00b8], %r18
.word 0x8580b6ec ! 22: WRCCR_I wr %r2, 0x16ec, %ccr
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610080, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 24: RDPC rd %pc, %r16
.word 0x8d903639 ! 25: WRPR_PSTATE_I wrpr %r0, 0x1639, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa1702160 ! 1: POPC_I popc 0x0160, %r16
.word 0x9170302d ! 26: POPC_I popc 0x102d, %r8
setx 0x1c3063cbafe5e15d, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xb3800011 ! 29: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7c9 ! 1: PDIST pdistn %d62, %d40, %d20
.word 0x9f802c3e ! 30: SIR sir 0x0c3e
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0x9f8020d0 ! 33: SIR sir 0x00d0
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e1c0 ! 35: LDSWA_I ldswa [%r31, + 0x01c0] %asi, %r8
.word 0xd097c028 ! 36: LDUHA_R lduha [%r31, %r8] 0x01, %r8
.word 0xb3800011 ! 37: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xc19fe020 ! 38: LDDFA_I ldda [%r31, 0x0020], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100f0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa7414000 ! 39: RDPC rd %pc, %r19
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0xc3e84030 ! 40: PREFETCHA_R prefetcha [%r1, %r16] 0x01, #one_read
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0xa7508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe098 ! 43: LDXA_I ldxa [%r31, + 0x0098] %asi, %r19
.word 0xa7b24482 ! 44: FCMPLE32 fcmple32 %d40, %d2, %r19
fbug,a,pn %fcc0, skip_2_25
.word 0xa3b104d1 ! 45: FCMPNE32 fcmpne32 %d4, %d48, %r17
.word 0x9d902005 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0005, %wstate
setx 0xe5c6b96d0b0dfe0e, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %r20, [%g0]0x5c ! D unsupported page size ..
.word 0xa1b50487 ! 48: FCMPLE32 fcmple32 %d20, %d38, %r16
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0x41f8db6d3f7b0ecc, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3e8] %asi
.word 0x9d94c012 ! 51: WRPR_WSTATE_R wrpr %r19, %r18, %wstate
.word 0xe63fe073 ! 52: STD_I std %r19, [%r31 + 0x0073]
.word 0xa784734a ! 53: WR_GRAPHICS_STATUS_REG_I wr %r17, 0x134a, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x3a800001 ! 1: BCC bcc,a <label_0x1>
.word 0x8d9032a9 ! 55: WRPR_PSTATE_I wrpr %r0, 0x12a9, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
stxa %r20, [%g0]0x54 ! I unsupported page size ..
.word 0x87ab0a4d ! 57: FCMPd fcmpd %fcc<n>, %f12, %f44
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
.word 0xe9e7e00c ! 59: CASA_R casa [%r31] %asi, %r12, %r20
.word 0xe8cfe158 ! 60: LDSBA_I ldsba [%r31, + 0x0158] %asi, %r20
.word 0x97b0c481 ! 61: FCMPLE32 fcmple32 %d34, %d32, %r11
.word 0x97410000 ! 62: RDTICK rd %tick, %r11
.word 0xd31fe110 ! 63: LDDF_I ldd [%r31, 0x0110], %f9
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r6, [%r0+0x3c0] %asi
.word 0x9d944011 ! 64: WRPR_WSTATE_R wrpr %r17, %r17, %wstate
.word 0xc32fc000 ! 65: STXFSR_R st-sfr %f1, [%r0, %r31]
setx fp_data_quads, %r19, %r20
.word 0xc3e83972 ! 66: PREFETCHA_I prefetcha [%r0, + 0xfffff972] %asi, #one_read
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_2_42-donret_2_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00525d00 | (16 << 24)), %r13
wrhpr %g0, 0x1c9b, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (2)
.word 0xd26fe001 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x0001]
.word 0xa7a209a1 ! 68: FDIVs fdivs %f8, %f1, %f19
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe0d0 ! 71: LDXA_I ldxa [%r31, + 0x00d0] %asi, %r19
.word 0xe737e1b8 ! 72: STQF_I - %f19, [0x01b8, %r31]
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x9bb407c4 ! 74: PDIST pdistn %d16, %d4, %d44
.word 0xd22fe14e ! 75: STB_I stb %r9, [%r31 + 0x014e]
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
.word 0x9194c010 ! 77: WRPR_PIL_R wrpr %r19, %r16, %pil
.word 0xd2dfc029 ! 78: LDXA_R ldxa [%r31, %r9] 0x01, %r9
.word 0x91d020b5 ! 79: Tcc_I ta icc_or_xcc, %r0 + 181
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x00000004003a0000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0xb0ca4ba384ea2cdc, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e1e2 ! 84: STQF_I - %f9, [0x01e2, %r31]
set user_data_start, %r31
.word 0x8583638d ! 85: WRCCR_I wr %r13, 0x038d, %ccr
.word 0x83d0001e ! 86: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0x26c829ce6d02c3c3, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe1a00000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffff3c4fffffe4a, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd28008a0 ! 92: LDUWA_R lduwa [%r0, %r0] 0x45, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610040, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x95414000 ! 93: RDPC rd %pc, %r10
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe170 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x0170]
.word 0xc32fc012 ! 94: STXFSR_R st-sfr %f1, [%r18, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r18, [%r0+0x3e0] %asi
.word 0x9d90c011 ! 96: WRPR_WSTATE_R wrpr %r3, %r17, %wstate
.word 0xc1bfd920 ! 97: STDFA_R stda %f0, [%r0, %r31]
.word 0xc19fc3e0 ! 98: LDDFA_R ldda [%r31, %r0], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100f0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa5414000 ! 99: RDPC rd %pc, %r18
.word 0xdb37e064 ! 100: STQF_I - %f13, [0x0064, %r31]
.word 0x87ab4a46 ! 101: FCMPd fcmpd %fcc<n>, %f44, %f6
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902006 ! 103: WRPR_CWP_I wrpr %r0, 0x0006, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0xc3e82fe8 ! 106: PREFETCHA_I prefetcha [%r0, + 0x0fe8] %asi, #one_read
.word 0xc3ec0032 ! 107: PREFETCHA_R prefetcha [%r16, %r18] 0x01, #one_read
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0x10332766f4e81f17, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e014 ! 110: CASA_R casa [%r31] %asi, %r20, %r11
.word 0xe1bfe160 ! 111: STDFA_I stda %f16, [0x0160, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_2_72-donret_2_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x00f42800 | (0x8b << 24)), %r13
wrhpr %g0, 0xe95, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (2)
.word 0x2ac90001 ! 1: BRNZ brnz,a,pt %r4,<label_0x90001>
.word 0x93a0c9d4 ! 112: FDIVd fdivd %f34, %f20, %f40
.word 0xd297c029 ! 113: LDUHA_R lduha [%r31, %r9] 0x01, %r9
.word 0xe1bfe120 ! 114: STDFA_I stda %f16, [0x0120, %r31]
.word 0x8d903d55 ! 115: WRPR_PSTATE_I wrpr %r0, 0x1d55, %pstate
.word 0x87802082 ! 116: WRASI_I wr %r0, 0x0082, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_76) + 16, 16, 16)) -> intp(4,0,25)
setx 0xbc94eb1716237f30, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc3ecc028 ! 118: PREFETCHA_R prefetcha [%r19, %r8] 0x01, #one_read
.word 0x91d02034 ! 119: Tcc_I ta icc_or_xcc, %r0 + 52
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r1, [%r0+0x3c0] %asi
.word 0x9d90c005 ! 120: WRPR_WSTATE_R wrpr %r3, %r5, %wstate
.word 0xc1bfe180 ! 121: STDFA_I stda %f0, [0x0180, %r31]
.word 0xa1a049c7 ! 122: FDIVd fdivd %f32, %f38, %f16
.word 0x8d802004 ! 123: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x26800001 ! 1: BL bl,a <label_0x1>
.word 0x81983387 ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x1387, %hpstate
.word 0xd0dfc028 ! 125: LDXA_R ldxa [%r31, %r8] 0x01, %r8
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_2_83-donret_2_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x00a21000 | (0x55 << 24)), %r13
wrhpr %g0, 0xf15, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (2)
.word 0x33400001 ! 1: FBPE fbe,a,pn %fcc0, <label_0x1>
.word 0x3d400001 ! 126: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0xc32fc00b ! 127: STXFSR_R st-sfr %f1, [%r11, %r31]
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x8580f85b ! 130: WRCCR_I wr %r3, 0x185b, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
.word 0xe19fe0e0 ! 132: LDDFA_I ldda [%r31, 0x00e0], %f16
.word 0xa9a00174 ! 133: FABSq dis not found
.word 0xdad7e100 ! 134: LDSHA_I ldsha [%r31, + 0x0100] %asi, %r13
.word 0x9f80273e ! 135: SIR sir 0x073e
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 136: FCMPd fcmpd %fcc<n>, %f0, %f4
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0x93b18305 ! 137: ALIGNADDRESS alignaddr %r6, %r5, %r9
.word 0xe137e066 ! 138: STQF_I - %f16, [0x0066, %r31]
setx fp_data_quads, %r19, %r20
.word 0x91a009c4 ! 139: FDIVd fdivd %f0, %f4, %f8
.word 0x23400001 ! 1: FBPNE fbne,a,pn %fcc0, <label_0x1>
.word 0x8d903c70 ! 140: WRPR_PSTATE_I wrpr %r0, 0x1c70, %pstate
.word 0xa7703859 ! 141: POPC_I popc 0x1859, %r19
.word 0xa7a000d1 ! 142: FNEGd fnegd %f48, %f50
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x99b307c6 ! 143: PDIST pdistn %d12, %d6, %d12
.word 0x93d0001e ! 144: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x8584bc63 ! 146: WRCCR_I wr %r18, 0x1c63, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe69fe150 ! 147: LDDA_I ldda [%r31, + 0x0150] %asi, %r19
.word 0xa7804013 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r1, %r19, %-
.word 0xe637e0f2 ! 149: STH_I sth %r19, [%r31 + 0x00f2]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_98) + 16, 16, 16)) -> intp(0,0,23)
setx 0xde03745a0a60370f, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0xe9d1cb5d876509a2, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe68008a0 ! 152: LDUWA_R lduwa [%r0, %r0] 0x45, %r19
.word 0xe62fe146 ! 153: STB_I stb %r19, [%r31 + 0x0146]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r13, [%r0+0x3d8] %asi
.word 0x9d934010 ! 154: WRPR_WSTATE_R wrpr %r13, %r16, %wstate
.word 0xa150c000 ! 155: RDPR_TT <illegal instruction>
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0xd5148012 ! 1: LDQF_R - [%r18, %r18], %f10
.word 0xe19fe000 ! 157: LDDFA_I ldda [%r31, 0x0000], %f16
tsubcctv %r16, 0x1b66, %r16
.word 0xd407e050 ! 158: LDUW_I lduw [%r31 + 0x0050], %r10
.word 0xb3800011 ! 159: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c02b ! 160: CASA_I casa [%r31] 0x 1, %r11, %r10
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x95a7c9d4 ! 161: FDIVd fdivd %f62, %f20, %f10
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610080, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa3414000 ! 162: RDPC rd %pc, %r17
.word 0x2b400001 ! 1: FBPUG fbug,a,pn %fcc0, <label_0x1>
.word 0x8198339c ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x139c, %hpstate
mov 0x10, %r1 ! (VA for ASI 0x5a)
.word 0xd4d04b40 ! 164: LDSHA_R ldsha [%r1, %r0] 0x5a, %r10
.word 0xe1bfe1e0 ! 165: STDFA_I stda %f16, [0x01e0, %r31]
.word 0x81982d05 ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x0d05, %hpstate
.word 0x83d0001e ! 167: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0x8d802000 ! 168: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xd43fe0e8 ! 169: STD_I std %r10, [%r31 + 0x00e8]
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe0a00000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
.word 0xc19fd920 ! 173: LDDFA_R ldda [%r31, %r0], %f0
.word 0xd51fe118 ! 174: LDDF_I ldd [%r31, 0x0118], %f10
.word 0xd44fe0e0 ! 175: LDSB_I ldsb [%r31 + 0x00e0], %r10
.word 0x91924004 ! 176: WRPR_PIL_R wrpr %r9, %r4, %pil
mov 0x10, %r1 ! (VA for ASI 0x4c)
.word 0xd4904980 ! 177: LDUHA_R lduha [%r1, %r0] 0x4c, %r10
setx 0x6eb5656978bd07b0, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xc1bfdc00 ! 179: STDFA_R stda %f0, [%r0, %r31]
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x20610080, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x9b414000 ! 181: RDPC rd %pc, %r13
.word 0xb3800011 ! 182: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx 0x1b925fce746aaf7e, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe098 ! 184: LDXA_I ldxa [%r31, + 0x0098] %asi, %r16
setx 0x2595ad93bce9ce0b, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_2_120) + 48, 16, 16)) -> intp(2,0,11)
setx 0x81a1f04261a0f8fc, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa3b447d3 ! 187: PDIST pdistn %d48, %d50, %d48
.word 0x91d0001e ! 188: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xa7848004 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r18, %r4, %-
.word 0xda97e040 ! 190: LDUHA_I lduha [%r31, + 0x0040] %asi, %r13
.word 0x8799213a ! 191: WRHPR_HINTP_I wrhpr %r4, 0x013a, %hintp
.word 0x91d02033 ! 192: Tcc_I ta icc_or_xcc, %r0 + 51
.word 0xa783000d ! 193: WR_GRAPHICS_STATUS_REG_R wr %r12, %r13, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x9f8039e0 ! 194: SIR sir 0x19e0
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c02c ! 1: CASA_I casa [%r31] 0x 1, %r12, %r9
.word 0xd2bfc02c ! 195: STDA_R stda %r9, [%r31 + %r12] 0x01
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x9b7032be ! 197: POPC_I popc 0x12be, %r13
set user_data_start, %r31
.word 0x85852469 ! 198: WRCCR_I wr %r20, 0x0469, %ccr
.word 0xc1bfe000 ! 199: STDFA_I stda %f0, [0x0000, %r31]
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0d04e60 ! 200: LDSHA_R ldsha [%r1, %r0] 0x73, %r16
.word 0x8f902001 ! 1: WRPR_TL_I wrpr %r0, 0x0001, %tl
ta T_CHANGE_NONHPRIV ! macro
setx join_lbl_0_0, %g1, %g2
.word 0xe08008a0 ! 1: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0xe19fda00 ! 2: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe08008a0 ! 3: LDUWA_R lduwa [%r0, %r0] 0x45, %r16
.word 0x89800011 ! 4: WRTICK_R wr %r0, %r17, %tick
.word 0x8d802004 ! 5: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x28800001 ! 1: BLEU bleu,a <label_0x1>
.word 0x8d903e3f ! 6: WRPR_PSTATE_I wrpr %r0, 0x1e3f, %pstate
.word 0xe0bfc020 ! 7: STDA_R stda %r16, [%r31 + %r0] 0x01
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_2) + 16, 16, 16)) -> intp(3,0,21)
setx 0x864829281e011335, %r1, %r28
.word 0x39400001 ! 8: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xc32fc000 ! 9: STXFSR_R st-sfr %f1, [%r0, %r31]
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 10: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x2a780001 ! 11: BPCS <illegal instruction>
.word 0xa7828004 ! 12: WR_GRAPHICS_STATUS_REG_R wr %r10, %r4, %-
setx fp_data_quads, %r19, %r20
.word 0x91a009a4 ! 13: FDIVs fdivs %f0, %f4, %f8
.word 0x91d0001e ! 14: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0x879cc012 ! 15: WRHPR_HINTP_R wrhpr %r19, %r18, %hintp
.word 0xa7703f5a ! 16: POPC_I popc 0x1f5a, %r19
.word 0x8780201c ! 17: WRASI_I wr %r0, 0x001c, %asi
.word 0xc3e9002a ! 18: PREFETCHA_R prefetcha [%r4, %r10] 0x01, #one_read
.word 0xa5a00174 ! 19: FABSq dis not found
.word 0xe49fe1f0 ! 20: LDDA_I ldda [%r31, + 0x01f0] %asi, %r18
.word 0xe44fe158 ! 21: LDSB_I ldsb [%r31 + 0x0158], %r18
.word 0x8582ab00 ! 22: WRCCR_I wr %r10, 0x0b00, %ccr
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 23: WRPR_TBA_R wrpr %r0, %r12, %tba
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100a0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 24: RDPC rd %pc, %r16
.word 0x8d9033bd ! 25: WRPR_PSTATE_I wrpr %r0, 0x13bd, %pstate
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa1702040 ! 1: POPC_I popc 0x0040, %r16
.word 0xa9a189a1 ! 26: FDIVs fdivs %f6, %f1, %f20
setx 0x12d34a0fa10bc542, %r1, %r28
.word 0x25400001 ! 27: FBPLG fblg,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 28: FBPULE fbule,a,pn %fcc0, <label_0x1>
wrhpr %r17, %g0, %hsys_tick_cmpr
.word 0xb3800011 ! 29: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xa9b7c7d2 ! 1: PDIST pdistn %d62, %d18, %d20
.word 0x91702d27 ! 30: POPC_I popc 0x0d27, %r8
.word 0xd03fc000 ! 31: STD_R std %r8, [%r31 + %r0]
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 32: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xd09fc02b ! 33: LDDA_R ldda [%r31, %r11] 0x01, %r8
.word 0xd127c000 ! 34: STF_R st %f8, [%r0, %r31]
.word 0xd0c7e118 ! 35: LDSWA_I ldswa [%r31, + 0x0118] %asi, %r8
.word 0xd0bfc02b ! 36: STDA_R stda %r8, [%r31 + %r11] 0x01
.word 0xb3800011 ! 37: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xc19fe000 ! 38: LDDFA_I ldda [%r31, 0x0000], %f0
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100c0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x91414000 ! 39: RDPC rd %pc, %r8
.word 0xc3eb0024 ! 40: PREFETCHA_R prefetcha [%r12, %r4] 0x01, #one_read
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 41: JMPL_R jmpl %r27 + %r0, %r27
.word 0xa7508000 ! 42: RDPR_TSTATE <illegal instruction>
.word 0xe6dfe0c0 ! 43: LDXA_I ldxa [%r31, + 0x00c0] %asi, %r19
.word 0x95a109c9 ! 44: FDIVd fdivd %f4, %f40, %f10
.word 0x9f80217f ! 45: SIR sir 0x017f
.word 0x9d902002 ! 46: WRPR_WSTATE_I wrpr %r0, 0x0002, %wstate
setx 0xbe6d4826d4c92419, %r1, %r28
.word 0x39400001 ! 47: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0xa7b44493 ! 48: FCMPLE32 fcmple32 %d48, %d50, %r19
.word 0xe677c000 ! 49: STX_R stx %r19, [%r31 + %r0]
setx 0xe19ffcc836aa4d81, %r1, %r28
.word 0x25400001 ! 50: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r19, [%r0+0x3c8] %asi
.word 0x9d948011 ! 51: WRPR_WSTATE_R wrpr %r18, %r17, %wstate
.word 0xe63fe138 ! 52: STD_I std %r19, [%r31 + 0x0138]
.word 0xa784720a ! 53: WR_GRAPHICS_STATUS_REG_I wr %r17, 0x120a, %-
.word 0xe71fc000 ! 54: LDDF_R ldd [%r31, %r0], %f19
.word 0x2accc001 ! 1: BRNZ brnz,a,pt %r19,<label_0xcc001>
.word 0x8d9029a3 ! 55: WRPR_PSTATE_I wrpr %r0, 0x09a3, %pstate
.word 0x8b90000c ! 56: WRPR_TBA_R wrpr %r0, %r12, %tba
.word 0xa9a409d3 ! 57: FDIVd fdivd %f16, %f50, %f20
.word 0x89800011 ! 58: WRTICK_R wr %r0, %r17, %tick
.word 0xc32fc00b ! 59: STXFSR_R st-sfr %f1, [%r11, %r31]
.word 0xe8cfe008 ! 60: LDSBA_I ldsba [%r31, + 0x0008] %asi, %r20
.word 0x9ba209b3 ! 61: FDIVs fdivs %f8, %f19, %f13
.word 0x93410000 ! 62: RDTICK rd %tick, %r9
.word 0xd31fe040 ! 63: LDDF_I ldd [%r31, 0x0040], %f9
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r20, [%r0+0x3e8] %asi
.word 0x9d920004 ! 64: WRPR_WSTATE_R wrpr %r8, %r4, %wstate
.word 0xc30fc000 ! 65: LDXFSR_R ld-fsr [%r31, %r0], %f1
setx fp_data_quads, %r19, %r20
.word 0x87a80a44 ! 66: FCMPd fcmpd %fcc<n>, %f0, %f4
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_1_42-donret_1_42+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x0091d700 | (0x89 << 24)), %r13
wrhpr %g0, 0xed9, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (1)
.word 0xd26fe055 ! 67: LDSTUB_I ldstub %r9, [%r31 + 0x0055]
.word 0xc3ed0032 ! 68: PREFETCHA_R prefetcha [%r20, %r18] 0x01, #one_read
.word 0x8b90000c ! 69: WRPR_TBA_R wrpr %r0, %r12, %tba
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 70: JMPL_R jmpl %r27 + %r0, %r27
.word 0xe6dfe0a8 ! 71: LDXA_I ldxa [%r31, + 0x00a8] %asi, %r19
.word 0xe737e098 ! 72: STQF_I - %f19, [0x0098, %r31]
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xe65fc000 ! 73: LDX_R ldx [%r31 + %r0], %r19
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x93b4c7d4 ! 74: PDIST pdistn %d50, %d20, %d40
.word 0xd22fe158 ! 75: STB_I stb %r9, [%r31 + 0x0158]
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xbfe7c000 ! 1: SAVE_R save %r31, %r0, %r31
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xd25fc000 ! 76: LDX_R ldx [%r31 + %r0], %r9
.word 0x9194c014 ! 77: WRPR_PIL_R wrpr %r19, %r20, %pil
.word 0xd33fc00c ! 78: STDF_R std %f9, [%r12, %r31]
.word 0x91d020b5 ! 79: Tcc_I ta icc_or_xcc, %r0 + 181
.word 0x89800011 ! 80: WRTICK_R wr %r0, %r17, %tick
setx 0x0000000000380000, %r11, %r12
.word 0x8b90000c ! 81: WRPR_TBA_R wrpr %r0, %r12, %tba
setx 0xc6abd848c920c73c, %r1, %r28
.word 0x25400001 ! 82: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xd25fc000 ! 83: LDX_R ldx [%r31 + %r0], %r9
.word 0xd337e1ac ! 84: STQF_I - %f9, [0x01ac, %r31]
set user_data_start, %r31
.word 0x8581646f ! 85: WRCCR_I wr %r5, 0x046f, %ccr
.word 0x83d0001e ! 86: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0xd327c000 ! 87: STF_R st %f9, [%r0, %r31]
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 88: JMPL_R jmpl %r27 + %r0, %r27
setx 0x7edcfa3ff8215ece, %r1, %r28
.word 0x39400001 ! 89: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
best_set_reg(0xe0200000, %r20, %r27)
.word 0xb7c6c000 ! 90: JMPL_R jmpl %r27 + %r0, %r27
setx 0xfffff549fffffd38, %g1, %g7
.word 0xa3800007 ! 91: WR_PERF_COUNTER_R wr %r0, %r7, %-
.word 0xd28008a0 ! 92: LDUWA_R lduwa [%r0, %r0] 0x45, %r9
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 93: RDPC rd %pc, %r16
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xe06fe0a0 ! 1: LDSTUB_I ldstub %r16, [%r31 + 0x00a0]
.word 0xe09fc030 ! 94: LDDA_R ldda [%r31, %r16] 0x01, %r16
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 95: FBPULE fbule,a,pn %fcc0, <label_0x1>
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r13, [%r0+0x3e0] %asi
.word 0x9d950013 ! 96: WRPR_WSTATE_R wrpr %r20, %r19, %wstate
.word 0xe19fda00 ! 97: LDDFA_R ldda [%r31, %r0], %f16
.word 0xe19fda00 ! 98: LDDFA_R ldda [%r31, %r0], %f16
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100a0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x9b414000 ! 99: RDPC rd %pc, %r13
.word 0xdb37e140 ! 100: STQF_I - %f13, [0x0140, %r31]
.word 0xc3eb4024 ! 101: PREFETCHA_R prefetcha [%r13, %r4] 0x01, #one_read
.word 0x89800011 ! 102: WRTICK_R wr %r0, %r17, %tick
.word 0x93902007 ! 103: WRPR_CWP_I wrpr %r0, 0x0007, %cwp
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 104: FBPULE fbule,a,pn %fcc0, <label_0x1>
stxa %r2, [%r0] ASI_LSU_CONTROL
.word 0x3d400001 ! 105: FBPULE fbule,a,pn %fcc0, <label_0x1>
setx fp_data_quads, %r19, %r20
.word 0x89a009a4 ! 106: FDIVs fdivs %f0, %f4, %f4
.word 0x97a409a4 ! 107: FDIVs fdivs %f16, %f4, %f11
.word 0x8143e011 ! 108: MEMBAR membar #LoadLoad | #Lookaside
setx 0x003f33467c26414a, %r1, %r28
.word 0x25400001 ! 109: FBPLG fblg,a,pn %fcc0, <label_0x1>
set sync_thr_counter6, %r23
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_MA_SYNC] %asi, %g0
stxa %g1, [%g0 + 0x80] %asi
.word 0xd7e7e009 ! 110: CASA_R casa [%r31] %asi, %r9, %r11
.word 0xc1bfe160 ! 111: STDFA_I stda %f0, [0x0160, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_1_72-donret_1_72), %r12
add %r12, 0x8, %r11 ! nonseq tnpc
set (0x0045b400 | (4 << 24)), %r13
wrhpr %g0, 0xd8c, %htstate
ta T_CHANGE_NONPRIV ! rand=0 (1)
.word 0x3a800001 ! 1: BCC bcc,a <label_0x1>
.word 0x93a449c8 ! 112: FDIVd fdivd %f48, %f8, %f40
.word 0xd2dfc034 ! 113: LDXA_R ldxa [%r31, %r20] 0x01, %r9
.word 0xc19fe180 ! 114: LDDFA_I ldda [%r31, 0x0180], %f0
.word 0x8d903e8d ! 115: WRPR_PSTATE_I wrpr %r0, 0x1e8d, %pstate
.word 0x8780201c ! 116: WRASI_I wr %r0, 0x001c, %asi
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_76) + 8, 16, 16)) -> intp(6,0,12)
setx 0x2c0eea58c154aa2a, %r1, %r28
.word 0x39400001 ! 117: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x97b487d1 ! 118: PDIST pdistn %d18, %d48, %d42
.word 0x93d02032 ! 119: Tcc_I tne icc_or_xcc, %r0 + 50
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r7, [%r0+0x3e0] %asi
.word 0x9d92c004 ! 120: WRPR_WSTATE_R wrpr %r11, %r4, %wstate
.word 0xc19fda00 ! 121: LDDFA_R ldda [%r31, %r0], %f0
.word 0x91a2c9c2 ! 122: FDIVd fdivd %f42, %f2, %f8
.word 0x8d802004 ! 123: WRFPRS_I wr %r0, 0x0004, %fprs
.word 0x25400001 ! 1: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0x81982497 ! 124: WRHPR_HPSTATE_I wrhpr %r0, 0x0497, %hpstate
.word 0xc32fc00a ! 125: STXFSR_R st-sfr %f1, [%r10, %r31]
ta T_CHANGE_HPRIV ! macro
add %r12, (donretarg_1_83-donret_1_83+4), %r12
add %r12, 0x4, %r11 ! seq tnpc
set (0x008d6600 | (0x4f << 24)), %r13
wrhpr %g0, 0x1d55, %htstate
ta T_CHANGE_NONHPRIV ! rand=1 (1)
.word 0x24cc4001 ! 1: BRLEZ brlez,a,pt %r17,<label_0xc4001>
.word 0x3a800001 ! 126: BCC bcc,a <label_0x1>
.word 0xd09fc033 ! 127: LDDA_R ldda [%r31, %r19] 0x01, %r8
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0x9d97c000 ! 1: WRPR_WSTATE_R wrpr %r31, %r0, %wstate
.word 0xbfefc000 ! 1: RESTORE_R restore %r31, %r0, %r31
.word 0xd05fc000 ! 128: LDX_R ldx [%r31 + %r0], %r8
.word 0x24800001 ! 129: BLE ble,a <label_0x1>
.word 0x85846102 ! 130: WRCCR_I wr %r17, 0x0102, %ccr
.word 0x22800001 ! 131: BE be,a <label_0x1>
.word 0xc19fd960 ! 132: LDDFA_R ldda [%r31, %r0], %f0
.word 0x9ba00165 ! 133: FABSq dis not found
.word 0xdad7e010 ! 134: LDSHA_I ldsha [%r31, + 0x0010] %asi, %r13
.word 0x93a0c9c6 ! 135: FDIVd fdivd %f34, %f6, %f40
setx fp_data_quads, %r19, %r20
.word 0x8da009c4 ! 136: FDIVd fdivd %f0, %f4, %f6
.word 0x20800001 ! 1: BN bn,a <label_0x1>
.word 0xa1b28310 ! 137: ALIGNADDRESS alignaddr %r10, %r16, %r16
.word 0xe137e09c ! 138: STQF_I - %f16, [0x009c, %r31]
setx fp_data_quads, %r19, %r20
.word 0xc3e8273e ! 139: PREFETCHA_I prefetcha [%r0, + 0x073e] %asi, #one_read
.word 0x2cc9c001 ! 1: BRGZ brgz,a,pt %r7,<label_0x9c001>
.word 0x8d903fe4 ! 140: WRPR_PSTATE_I wrpr %r0, 0x1fe4, %pstate
.word 0x9ba4c9a7 ! 141: FDIVs fdivs %f19, %f7, %f13
.word 0x99a000c6 ! 142: FNEGd fnegd %f6, %f12
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0xa7b207cc ! 143: PDIST pdistn %d8, %d12, %d50
.word 0x83d0001e ! 144: Tcc_R te icc_or_xcc, %r0 + %r30
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONPRIV ! macro
.word 0x8584fc0f ! 146: WRCCR_I wr %r19, 0x1c0f, %ccr
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xe69fe060 ! 147: LDDA_I ldda [%r31, + 0x0060] %asi, %r19
.word 0xa7850008 ! 148: WR_GRAPHICS_STATUS_REG_R wr %r20, %r8, %-
.word 0xe637e1f0 ! 149: STH_I sth %r19, [%r31 + 0x01f0]
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_98) + 48, 16, 16)) -> intp(0,0,21)
setx 0xac86ccda092db929, %r1, %r28
.word 0x39400001 ! 150: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
setx 0xf1afd04ecaf253ea, %r1, %r28
.word 0x25400001 ! 151: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe6800be0 ! 152: LDUWA_R lduwa [%r0, %r0] 0x5f, %r19
.word 0xe62fe0bd ! 153: STB_I stb %r19, [%r31 + 0x00bd]
.word 0x87802025 ! 1: WRASI_I wr %r0, 0x0025, %asi
stxa %r4, [%r0+0x3c0] %asi
.word 0x9d948004 ! 154: WRPR_WSTATE_R wrpr %r18, %r4, %wstate
.word 0x9150c000 ! 155: RDPR_TT <illegal instruction>
.word 0x3a800001 ! 156: BCC bcc,a <label_0x1>
setx common_target, %r12, %r27
.word 0x91b7c713 ! 1: FMULD8SUx16 fmuld8ulx16 %f31, %f19, %d8
.word 0xe1bfe160 ! 157: STDFA_I stda %f16, [0x0160, %r31]
tsubcctv %r18, 0x15dc, %r5
.word 0xd407e12c ! 158: LDUW_I lduw [%r31 + 0x012c], %r10
.word 0xaf800011 ! 159: WR_TICK_CMPR_REG_R wr %r0, %r17, %-
.word 0xd5e7c031 ! 160: CASA_I casa [%r31] 0x 1, %r17, %r10
.word 0x39400001 ! 1: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
.word 0x39400001 ! 161: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0x95414000 ! 162: RDPC rd %pc, %r10
.word 0x3a800001 ! 1: BCC bcc,a <label_0x1>
.word 0x81982e5f ! 163: WRHPR_HPSTATE_I wrhpr %r0, 0x0e5f, %hpstate
mov 0x10, %r1 ! (VA for ASI 0x5a)
.word 0xd4d84b40 ! 164: LDXA_R ldxa [%r1, %r0] 0x5a, %r10
.word 0xe1bfe160 ! 165: STDFA_I stda %f16, [0x0160, %r31]
.word 0x81983acf ! 166: WRHPR_HPSTATE_I wrhpr %r0, 0x1acf, %hpstate
.word 0x93d0001e ! 167: Tcc_R tne icc_or_xcc, %r0 + %r30
.word 0x8d802000 ! 168: WRFPRS_I wr %r0, 0x0000, %fprs
.word 0xd43fe121 ! 169: STD_I std %r10, [%r31 + 0x0121]
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 170: JMPL_R jmpl %r27 + %r0, %r27
best_set_reg(0xe1200000, %r20, %r27)
.word 0xb7c6c000 ! 171: JMPL_R jmpl %r27 + %r0, %r27
.word 0xd45fc000 ! 172: LDX_R ldx [%r31 + %r0], %r10
.word 0xe1bfdc00 ! 173: STDFA_R stda %f16, [%r0, %r31]
.word 0xd51fe128 ! 174: LDDF_I ldd [%r31, 0x0128], %f10
.word 0xd44fe1d8 ! 175: LDSB_I ldsb [%r31 + 0x01d8], %r10
.word 0x91948014 ! 176: WRPR_PIL_R wrpr %r18, %r20, %pil
mov 0x20, %r1 ! (VA for ASI 0x4c)
.word 0xd4d04980 ! 177: LDSHA_R ldsha [%r1, %r0] 0x4c, %r10
setx 0x998579d80d5b64ce, %r1, %r28
.word 0x25400001 ! 178: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xc19fe180 ! 179: LDDFA_I ldda [%r31, 0x0180], %f0
.word 0xc30fc000 ! 180: LDXFSR_R ld-fsr [%r31, %r0], %f1
set sync_thr_counter5, %r23
sllx %o1, 5, %o3 !(CID*256)
cas [%r23],%g0,%r10 !lock
ldxa [%g0 + ASI_SPU_CWQ_SYNC] %asi, %l1
and %l1, 0x3, %l1 ! Check if busy/enabled ..
stxa %l1, [%g0 + ASI_SPU_CWQ_CSR] %asi
best_set_reg(0x206100b0, %l1, %l2) !# Control Word
ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l2
stxa %l2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
.word 0xa1414000 ! 181: RDPC rd %pc, %r16
.word 0xb3800011 ! 182: WR_STICK_CMPR_REG_R wr %r0, %r17, %-
setx 0x1df994f9eeae4ceb, %r1, %r28
.word 0x25400001 ! 183: FBPLG fblg,a,pn %fcc0, <label_0x1>
.word 0xe0dfe088 ! 184: LDXA_I ldxa [%r31, + 0x0088] %asi, %r16
setx 0x32df799cac974275, %r1, %r28
.word 0x25400001 ! 185: FBPLG fblg,a,pn %fcc0, <label_0x1>
#if (defined SPC || defined CMP1)
!$EV trig_pc_d(1, expr(@VA(.MAIN.intvec_1_120) + 8, 16, 16)) -> intp(5,0,30)
setx 0xb0b3ff9d3514afbc, %r1, %r28
.word 0x39400001 ! 186: FBPUGE fbuge,a,pn %fcc0, <label_0x1>
stxa %l3, [%g0] ASI_SPARC_PWR_MGMT
.word 0x9bb1c7cb ! 187: PDIST pdistn %d38, %d42, %d44
.word 0x91d0001e ! 188: Tcc_R ta icc_or_xcc, %r0 + %r30
.word 0xa7844009 ! 189: WR_GRAPHICS_STATUS_REG_R wr %r17, %r9, %-
.word 0xda97e058 ! 190: LDUHA_I lduha [%r31, + 0x0058] %asi, %r13
.word 0x879b638f ! 191: WRHPR_HINTP_I wrhpr %r13, 0x038f, %hintp
.word 0x91d020b5 ! 192: Tcc_I ta icc_or_xcc, %r0 + 181
.word 0xa7844010 ! 193: WR_GRAPHICS_STATUS_REG_R wr %r17, %r16, %-
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0x93a4c9a2 ! 194: FDIVs fdivs %f19, %f2, %f9
setx common_target, %r12, %r27
lduw [%r27], %r12 ! Load common dest into dcache ..
.word 0xd3e7c033 ! 1: CASA_I casa [%r31] 0x 1, %r19, %r9
.word 0xd23fe0a0 ! 195: STD_I std %r9, [%r31 + 0x00a0]
.word 0xc30fc000 ! 196: LDXFSR_R ld-fsr [%r31, %r0], %f1
stxa %r19, [%g0] ASI_LSU_CONTROL
.word 0xa1b4c7c1 ! 197: PDIST pdistn %d50, %d32, %d16
set user_data_start, %r31
.word 0x8584f50f ! 198: WRCCR_I wr %r19, 0x150f, %ccr
.word 0xc19fda00 ! 199: LDDFA_R ldda [%r31, %r0], %f0
mov 0x0, %r1 ! (VA for ASI 0x73)
.word 0xe0c04e60 ! 200: LDSWA_R ldswa [%r1, %r0] 0x73, %r16
.word 0x8f902000 ! 1: WRPR_TL_I wrpr %r0, 0x0000, %tl
ta T_CHANGE_NONHPRIV ! macro
best_set_reg(HV_TRAP_BASE_PA, %r1, %r2)
! fp data rs1, rs2, fsr, gsr quads ..
.xword 0x0044000000000000
.xword 0x4028000000000000
.xword 0x0fc0400400000000
.xword 0x0000000000000000
.xword 0x0041000000000000
.xword 0x4022000000000000
.xword 0x0600800000000000
.xword 0x0000000000000000
.xword 0x0220000000000000
.xword 0x4140000000000000
.xword 0x4fc0400400000000
.xword 0x0000000000000000
.xword 0x4090000000000000
.xword 0x0090000000000000
.xword 0x0f80400800000000
.xword 0x0a00000000000000
.xword 0x3dc5d6a075f93f25
.xword 0xd95195e8d5fa3106
.xword 0xebc1e15e8656080a
.xword 0x995dd1ab4c15ef75
.xword 0xd3429f94cbf9df37
.xword 0x5011c46d098cd1d1
.xword 0xcd2c3152b16c3d2a
.xword 0x71cac2f4df1f170e
.xword 0xadd4e29f8ba3072d
.xword 0xb87ecd88731b723e
.xword 0x9857f8f38d935b6a
.xword 0x3fd49c272adf35a8
.xword 0x1577c508becb9c4a
.xword 0x69919cae37b9e537
.xword 0xafd796fa0ee25e33
.xword 0x4f5994d14d04cf3f
.xword 0x4cab6273a1ce6e29
.xword 0x98ea410ecbb5b1be
.xword 0x7f945928e81009ab
.xword 0xce5a2282410ed932
.xword 0x142427fc0fb9d0ba
.xword 0x4f4312662ca0a124
.xword 0xb0876124e7fdbef6
.xword 0x9c5009e273ab445d
.xword 0xef6cd964e0a31091
.xword 0x929117a1c26a1a4a
.xword 0x58f11e246cb0ac38
.xword 0xe908434ae0ad3afb
.xword 0xfceaf9b50b2fc57b
.xword 0x7502e6634880f575
.xword 0x3f0a4911f5d17a34
.xword 0xd17e1c5618a2523e
.xword 0xefbd44bc114a6b72
.xword 0xa50cc98d70cb9cb3
.xword 0xca58704cb2b1a90e
.xword 0x4a6c151cebba117e
.xword 0x9d0118ffdb1c828b
.xword 0xe5728c746185719f
.xword 0xe52a7cb8316f88c7
.xword 0x4b97276eb35bb6c2
.xword 0x8b443d0b1473e1a7
.xword 0x3f56ce59beebda27
.xword 0xf3951387254b99b8
.xword 0x258fdee76bb94c01
.xword 0xb9a2443feb0b4d03
.xword 0xadc6ccc7fcad6201
.xword 0x2447040d672ffd64
.xword 0x6c71f84ee89ecb3b
.xword 0x8cc3f377f19d15bc
.xword 0x2a658567e05c6df3
.xword 0xf60c49076a2ff4c3
.xword 0xacb34b7bcbe758c2
.xword 0x641a36a24efcb531
.xword 0x5d38ea62545fd979
.xword 0xeb479a9d21e541ab
.xword 0xdf26006951722f80
.xword 0x4d2d3959870a51cd
.xword 0xe960cbccd4352ac6
.xword 0x49ed5d335634b99d
.xword 0xee44906c9aadacfe
.xword 0x1ee279a79ce6bca8
.xword 0x8d936ffa42ffd86e
.xword 0x6194e8184bcfa7cc
.xword 0x301466557cc1609b
.xword 0x1a611cd9d1da663d
.xword 0x19f0b11d6dcd4ff7
.xword 0x0ec0d65012b7e02e
.xword 0x67370eb28d13f9b0
.xword 0x00ffdb1037fcab57
.xword 0x136fa0573ed11f91
.xword 0xd5013599f6ee32a2
.xword 0xd2a4892d49e3e0a0
.xword 0x6ff37df74232a26f
.xword 0x7156636f79ffc217
.xword 0x20f2b1a7b7a80a01
.xword 0x543cb05b351ef590
.xword 0x9065738df05fa371
.xword 0x59ad8cc8c0e5fdf9
.xword 0xc33355e0699f12a5
.xword 0x9869ce87fb358c2e
.xword 0xdc432e270ee2035a
.xword 0xc8a78454dae5d5e7
.xword 0xad76a55af8b18f63
.xword 0xcd2768687a8ef6f9
.xword 0x1139ea3e0573cc1c
.xword 0xe0ee152f5bb16a50
.xword 0xc457a382cfb8140c
.xword 0x284317150ba56810
.xword 0x2a095b9101944cbb
.xword 0xe3e2042b0668afad
.xword 0x68e7153c594b5480
.xword 0x9038519de8867fe8
.xword 0x0fbab1bbbf510d2c
.xword 0xd513be9895bcc929
.xword 0xeb950d9cf9d29ff7
.xword 0xc7e529766bfd0dfa
.xword 0x0d2367a92cab515e
.xword 0x46e4babd4b375840
.xword 0xd82c7f1fb3e0d133
.xword 0xda4dbe272c23871d
.xword 0x75c4cfc86379cdcd
.xword 0x553e563b2262a318
.xword 0x2785865349190a3b
.xword 0x0a66438622639591
.xword 0xc9115aaf9083f0fb
.xword 0xc65f52a220366326
.xword 0xb38a7d9e668f3272
.xword 0x449f683736b26c2d
.xword 0xf8763dd56e147dc9
.xword 0x28e2f477f28e9bc9
.xword 0x40a8773812fcc048
.xword 0xaa766c60ac67e7ec
.xword 0xf6e1ae094faf9d4c
.xword 0x0f0be3e2a3b25528
.xword 0x79f1e5152714961e
.xword 0xc8e9567536e8f081
.xword 0x14dc47d135534d64
.xword 0xee6f38457b4ba293
.xword 0x11ff93e8fb0a2c0d
.xword 0x981a76e6f57a4e5f
.xword 0xfa4f03616b8c9cb6
.xword 0x5610ca22df8a9683
.xword 0x66bf7a928287fef0
.xword 0xbad5dc7c0031e7da
.xword 0xac3d1117e1d84119
.xword 0x8774460638d191c2
.xword 0x7f128a56c0f7000b
.xword 0x18c0c8828e8d3060
.xword 0xc0dab0de909a906c
.xword 0xf323f839f1a54521
.xword 0x87e0c6a61df7aae0
.xword 0x7ebcededec77d584
.xword 0x9df2ea0232e33a73
.xword 0x5e0a65b89d66da9a
.xword 0x3668f4c279196fb1
.xword 0x2a1f77346bc74bdf
.xword 0x414a365ce8a7ba06
.xword 0x959c425ef0512d98
.xword 0x5a1f5d474a33517e
.xword 0xc1cc8dfaf596406a
.xword 0xd6be8c8fa2610088
.xword 0x8c936c0c739e0471
.xword 0xbbce96f29d275f37
.xword 0xa9fd11de30db562e
.xword 0xb49701e6f08bc5a4
.xword 0x84b5e86b0ded84db
.xword 0x65510e7c2ef135ca
.xword 0xeaa57a11873a23a4
.xword 0x8ac2b534337cc2db
.xword 0x8950f55eccef72a5
.xword 0xdb2337fa20395b52
.xword 0x9b9c8da0b53a4f1d
.xword 0xe5f47ad41137cef1
.xword 0xea9011400707df0f
.xword 0xbf7852bcbcc1d943
.xword 0xd0e1cd39f7c4b011
.xword 0x121a3ad9b0b7d678
.xword 0xf1661d6ca9f90f60
.xword 0x1e76a96257ec1a38
.xword 0x9a24d9600364f27e
.xword 0x8efeb6756e241f7d
.xword 0x517b8610dcfcbd1c
.xword 0x496e9bf37c551ae8
.xword 0x76eec375b9d149e9
.xword 0x4d7941a08dc7ecba
.xword 0xd31c21b4ad42c797
.xword 0x1d86131179dfd534
.xword 0x8933fc10810db69f
.xword 0x9843237c36eb95db
.xword 0x105789fd9841411c
.xword 0x42a07d6ec62860ab
.xword 0x3aa32e0ce492d63c
.xword 0x34f0ca3185f8ab52
.xword 0xf100946f144b3e3e
.xword 0x76da371202115795
.xword 0x1639afa4eae09577
.xword 0xf9c3d3e45f7ab30b
.xword 0xdba3055f77d6b1af
.xword 0xff446703d7d25daf
.xword 0x61f01a0fb214905e
.xword 0xae4a8dc62d48d7d4
.xword 0x93f037342dbbdc82
.xword 0x15618f1534e7b0da
.xword 0x04f8c2cc5c36f91a
.xword 0x2925e917480461c0
.xword 0xb73c9f8d4fb99e4c
.xword 0xc362de628a11998a
.xword 0x33d74240aca8b54c
.xword 0xa2377b60a6c5a2af
.xword 0x83480ba8eea6c986
.xword 0x3900f5d4fbb00f08
.xword 0x504c4ecc4db30290
.xword 0x035167316eb7d43d
.xword 0x956bbc254cf0b7e9
.xword 0x87e699767cc629f5
.xword 0xe041c75a6c74b56c
.xword 0x4262f5b035814cc9
.xword 0xc3611234002ae98d
.xword 0x0539d5e88c71a103
.xword 0xdd2ffbffe8d970a4
.xword 0x63fc37771197e327
.xword 0x00db8f5417e4fc12
.xword 0xf3d851d1362b1212
.xword 0x4e5ee9ba26d3764e
.xword 0x61f504d36faf6bbb
.xword 0xd51147ef6788b9c0
.xword 0xe11d88a058bb6b04
.xword 0x42d07f04631a9e74
.xword 0x00c6edb4a963078b
.xword 0x16883314ba6d7873
.xword 0x91dd048f29854661
.xword 0x25646f06c058c4af
.xword 0xff41195bea2784fc
.xword 0x6b4cdb4f829952dc
.xword 0x2b993dece48be54e
.xword 0x88b1df077d4b66c7
.xword 0xd311df76b9a3449c
.xword 0x8cbdb0c531e9ec9e
.xword 0x7fa20f58910ca12a
.xword 0xa0fc5d2183dbdc2e
.xword 0x8a727ee6c454f506
.xword 0x6cb0a9e91a9834ee
.xword 0xdb7266afe89be053
.xword 0x4058b48a2fcd0065
.xword 0xd5d81996c594c499
.xword 0xfcd61e8b366e6bb5
.xword 0xe958391d7af226d7
.xword 0x6f13616f4b1ecf9d
.xword 0x6cde6d21865684d2
.xword 0x67eb467b4b3074eb
.xword 0xfd0f6af4d60369ba
.xword 0xb179d56ca323de3b
.xword 0xa6d79eb566a93a41
.xword 0x73edcdc465021a82
.xword 0x0d91122df8d40d8f
.xword 0x9099b6a053a48687
.xword 0x72a042cdddf3887f
.xword 0x700e4583ba578a1c
.xword 0x14322618b27b8f87
.xword 0x615d5041d3a797c9
.xword 0xacf09b67dec65a1c
.xword 0xed38c2c0c09b34bb
.xword 0xe8408e4b8ec01204
.xword 0x8d6ec44fc49bd181
.xword 0xdb4ce594ebf66c5a
.xword 0x0decad08b9539561
.xword 0x5a02a0ef950a1fa0
.xword 0x6a903db6e39628b4
.xword 0x6882bbd8b76fae8a
.xword 0xca3c636411fb04e5
.xword 0xdb6c913fd532ba6f
.xword 0x544508694ea8ddf4
.xword 0xca477de45eceb4ae
.xword 0x044d9e156092555d
.xword 0xec94a8e9ff599971
.xword 0xb8eeaf6ec83d02ac
.global restore_range_regs
wr %g0, ASI_MMU_REAL_RANGE, %asi
ldxa [ASI_MMU_REAL_RANGE_0] %asi, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_0] %asi
ldxa [ASI_MMU_REAL_RANGE_1] %asi, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_1] %asi
ldxa [ASI_MMU_REAL_RANGE_2] %asi, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_2] %asi
ldxa [ASI_MMU_REAL_RANGE_3] %asi, %g2
stxa %g2, [ASI_MMU_REAL_RANGE_3] %asi
# 10 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_extensions.s"
.global retry_with_base_tba
!if pc[13:5]==0, then assume not a relocated handler
brnz,a %r5, retry_with_base_tba
!assume %r27 is where we came from ..
best_set_reg(TRAP_BASE_VA, %r3, %r5)
add %l2, htrap_5_ext_done-htrap_5_ext, %l2
stxa %l1, [%g0] ASI_LSU_CTL_REG
! If TT != 2, then goto trap handler
and %l3, 0x4, %l3 ! If previously in hpriv mode, go to hpriv
brnz,a %l3, wdog_2_goto_handler_1
srlx %l1, 7, %l3 ! Send priv sw traps to priv mode ..
cmp %l3, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap ..
be,a wdog_2_goto_handler_1
# 86 "/import/n2-aus-localdir1/somePerson/n2cdmspp/verif/diag/assembly/include/tlu_custom_trap_extensions.s"
! Red mode other reset handler
! Get htba, and tt and make trap address
! Jump to trap handler ..
! IF TL=6, shift stack by one ..
stxa %l1, [%g0] ASI_LSU_CTL_REG
and %l2, 0x4, %l2 ! If previously in hpriv mode, go to hpriv
brnz,a %l2, red_goto_handler
srlx %l1, 7, %l2 ! Send priv sw traps to priv mode ..
cmp %l2, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap ..
wrhpr %l1, 0x20, %hpstate
! Shift stack down by 1 ...
! If TT != 2, then goto trap handler
stxa %l1, [%g0] ASI_LSU_CTL_REG
SECTION .CWQ_DATA DATA_VA =0x4000
.xword 0xad32fa52374cc6ba
.xword 0x4cbf52280549003a
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
!# CWQ_BASE for core N is CWQ_BASE+(N*256)
!# CWQ_LAST for core N is CWQ_LAST+(N*256)
SECTION .MyHTRAPS_0 TEXT_VA = 0x0000000000280000, DATA_VA = 0x00000000002c0000
PA = ra2pa(0x0000000000280000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000000002c0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
#include "tlu_htraps_ext.s"
SECTION .MyHTRAPS_1 TEXT_VA = 0x00000000002a0000, DATA_VA = 0x00000000002e0000
PA = ra2pa(0x00000000002a0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000000002e0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
#include "tlu_htraps_ext.s"
SECTION .MyHTRAPS_2 TEXT_VA = 0x0000000200280000, DATA_VA = 0x00000002002c0000
PA = ra2pa(0x0000000200280000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000002002c0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
#include "tlu_htraps_ext.s"
SECTION .MyHTRAPS_3 TEXT_VA = 0x00000002002a0000, DATA_VA = 0x00000002002e0000
PA = ra2pa(0x00000002002a0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000002002e0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
#include "tlu_htraps_ext.s"
SECTION .MyTRAPS_0 TEXT_VA = 0x0000000000380000, DATA_VA = 0x00000000003c0000
PA = ra2pa(0x0000000000380000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000000003c0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
SECTION .MyTRAPS_1 TEXT_VA = 0x00000000003a0000, DATA_VA = 0x00000000003e0000
PA = ra2pa(0x00000000003a0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000000003e0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
SECTION .MyTRAPS_2 TEXT_VA = 0x0000000400380000, DATA_VA = 0x00000004003c0000
PA = ra2pa(0x0000000400380000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000004003c0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
SECTION .MyTRAPS_3 TEXT_VA = 0x00000004003a0000, DATA_VA = 0x00000004003e0000
PA = ra2pa(0x00000004003a0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
PA = ra2pa(0x00000004003e0000,0),
part_0_ctx_zero_tsb_config_3,
part_0_ctx_nonzero_tsb_config_3,
TTE_Size = PART0_Z_PAGE_SIZE_3,
SECTION .MyDATA_0 TEXT_VA = 0x00000000e0140000, DATA_VA = 0x0000000060140000
PA = ra2pa(0x0000000170100000,0),
part_0_ctx_zero_tsb_config_0,
part_0_ctx_nonzero_tsb_config_0,
PA = ra2pa(0x0000000170100000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
.xword 0x9e77ee7f704e3adb
.xword 0xac6d590e44408197
.xword 0x5a1aa8a80e6e6de0
.xword 0x5a39354fb4c3c01e
.xword 0x86166615052aac64
.xword 0x8149d81174c1f9b3
.xword 0x601baea331e12ffd
.xword 0x4cdaf2a080fe1eac
.xword 0x8042e608ccc7156a
.xword 0x711148b9c41272c9
.xword 0x25dc88eca0327e7b
.xword 0xea6663fd7ef53f80
.xword 0x94ac7d676e75015a
.xword 0x63e57a3c70edaddf
.xword 0x4cf263a216a9a2d3
.xword 0xe5dfa39fc2ad9e23
.xword 0x06719d8adfb5c3b2
.xword 0x5c9d4f9e85f9f825
.xword 0x025da98a332688b3
.xword 0xd3ae867de122376c
.xword 0x5a7e277e0543a9cd
.xword 0x54c54327c286e9bb
.xword 0x36073b9ef40246e3
.xword 0xc5dd0b2787140497
.xword 0x6ba7a109169ae962
.xword 0xd882236166c84f77
.xword 0x87b8d90f4cf628d8
.xword 0x6c822e2856382d94
.xword 0xe7aebf6fcce8f616
.xword 0x77091ede64b86a51
.xword 0x853d810d7e19e3fa
.xword 0xef65f7a83d6ac9cb
SECTION .MyDATA_1 TEXT_VA = 0x00000000e0340000, DATA_VA = 0x0000000060340000
PA = ra2pa(0x0000000170300000,0),
part_0_ctx_zero_tsb_config_0,
part_0_ctx_nonzero_tsb_config_0,
PA = ra2pa(0x0000000170300000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
.xword 0x92a8f8fe4a6a939e
.xword 0x3c4c92c9f6ebeda8
.xword 0x1cda48aadb472f57
.xword 0x773664ff3b90fcd2
.xword 0x1f005f406d045bf4
.xword 0xd454e1d1a17e24bb
.xword 0x144cf830e9d3d833
.xword 0x8ff11464fcd6d164
.xword 0x770bddf6a1a7ff75
.xword 0x55870209d88c58e9
.xword 0xfda94d75d09e2598
.xword 0x36851818583c7597
.xword 0x3571a0fe19c972af
.xword 0xa33ecb849ed5452c
.xword 0x504f96d7b161999c
.xword 0x4eb0fa4f8f68d5ea
.xword 0xdc6676b71d11bef9
.xword 0x518eedbf6b719c58
.xword 0x0b0db53b3eda03eb
.xword 0xe44eeab3c4880bf2
.xword 0x3ddd40fc4ab20669
.xword 0x1d3408e50480e54f
.xword 0xa67cb2d9da7041dd
.xword 0x0e3f181241ab6cf0
.xword 0x267544e03db946a8
.xword 0xcf29c71dd296560b
.xword 0x0559f5d070aadaec
.xword 0x6e13ccc1627f5ef7
.xword 0x93cddef3656ee1ba
.xword 0x43732b6e688968bf
.xword 0x31569bd1adb11161
.xword 0xdc9da0b97376a03f
SECTION .MyDATA_2 TEXT_VA = 0x00000000e0540000, DATA_VA = 0x0000000060540000
PA = ra2pa(0x0000000170500000,0),
part_0_ctx_zero_tsb_config_0,
part_0_ctx_nonzero_tsb_config_0,
PA = ra2pa(0x0000000170500000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
.xword 0x5caa17143d80488c
.xword 0x798a87103de99cea
.xword 0x97f90bea7d04cc7a
.xword 0xf5f94e9c6d4a3b4b
.xword 0x179c1b2b4978e43e
.xword 0xf517942fe1e1d86b
.xword 0xeb1ac73349171b6d
.xword 0x9d6e3979df75f8f0
.xword 0x252cfa8921d7a7c7
.xword 0x4ca0d98a2d01fa3e
.xword 0xed18fdf8d3e31cd3
.xword 0xaf5b211bd16f1891
.xword 0x40f20af96c900cc9
.xword 0x5f0bbdc9eb8c5ae4
.xword 0x57584b9194f38e1e
.xword 0xfff540871fdf8ce6
.xword 0xa44ba3dd7ea8ceaf
.xword 0xdfddafd8a1bd232f
.xword 0xf172efd30a8a3d50
.xword 0x1c5e0093723abde3
.xword 0xca335b90e865bf43
.xword 0x261f7b0c39a4a1eb
.xword 0xb3112a05caf0353f
.xword 0xef7f2d4e1c22b7b1
.xword 0x9ac6e82ebdd76dc7
.xword 0xd01c28529a2b96db
.xword 0x1b03818db740a62b
.xword 0xf3d2c90679623c8d
.xword 0x1b86227bf401afe5
.xword 0x6e8893805336905b
.xword 0x90f2d82094811372
.xword 0xbd5ffcf4623a9b77
SECTION .MyDATA_3 TEXT_VA = 0x00000000e0740000, DATA_VA = 0x0000000060740000
PA = ra2pa(0x0000000170700000,0),
part_0_ctx_zero_tsb_config_0,
part_0_ctx_nonzero_tsb_config_0,
PA = ra2pa(0x0000000170700000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
.xword 0xc41c3c41fd49c05e
.xword 0x8e38d39fba826ef1
.xword 0x72caf50c13b85b36
.xword 0xd31663a741386132
.xword 0x85c0a9027ce27e6d
.xword 0x7191abd594beff85
.xword 0xf3dd6559cc8e24b6
.xword 0x9b9cfff64f8efc3b
.xword 0xd75454595850fa1e
.xword 0x3ad0259faf35ee66
.xword 0xc250474aff6a0840
.xword 0x4ab61a39426cdd24
.xword 0x377896d4a92b9fac
.xword 0xe82a8056d3e7ffe1
.xword 0x1b0d0dfddbdcc915
.xword 0xc90f57fc0453d9c6
.xword 0x886ec4a5b607e80b
.xword 0x36d02d80e03b5434
.xword 0x62d978d6907714a4
.xword 0x7db376b848f36ed1
.xword 0xe4611a2fa8993908
.xword 0x2cbaca15065bc58d
.xword 0x40639a747fa8e07c
.xword 0x307c6404ed193c20
.xword 0x49806f05531fe453
.xword 0x12064ebfc96affc4
.xword 0x4b842ceed9ec5bd9
.xword 0xe60bc6e281ca2e97
.xword 0x19b4cfa4aa7e66d2
.xword 0xc3b3d7dc0d1a722f
.xword 0xc7dc438a820a28e1
.xword 0xc58457beb374bf9f
SECTION .MyTEXT_0 TEXT_VA = 0x00000000e0200000
PA = ra2pa(0x00000000e0200000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
SECTION .MyTEXT_1 TEXT_VA = 0x00000000e0a00000
PA = ra2pa(0x00000000e0a00000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
SECTION .MyTEXT_2 TEXT_VA = 0x00000000e1200000
PA = ra2pa(0x00000000e1200000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
SECTION .MyTEXT_3 TEXT_VA = 0x00000000e1a00000
PA = ra2pa(0x00000000e1a00000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
SECTION .VaHOLE_0 TEXT_VA = 0x00007fffffffe000
PA = ra2pa(0x00000000ffffe000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
vahole_target2: nop;nop;nop
vahole_target3: nop;nop;nop
SECTION .VaHOLEL_0 TEXT_VA = 0x00000000ffffe000
PA = ra2pa(0x00000000ffffe000,0),
part_0_ctx_zero_tsb_config_0,
part_0_ctx_nonzero_tsb_config_0,
SECTION .ZERO_0 TEXT_VA = 0x0000000000000000
PA = ra2pa(0x0000000000000000,0),
part_0_ctx_zero_tsb_config_1,
part_0_ctx_nonzero_tsb_config_1,
setx HRedmode_Reset_Handler, %g1, %g2
setx wdog_red_ext, %g1, %g2
Software_Initiated_Reset:
setx Software_Reset_Handler, %g1, %g2
! IF TL=6, shift stack by one ..
stxa %l1, [%g0] ASI_LSU_CTL_REG
and %l2, 0x4, %l2 ! If previously in hpriv mode, go to hpriv
brnz,a %l2, red_goto_handler
srlx %l1, 7, %l2 ! Send priv sw traps to priv mode ..
cmp %l2, 0x2 ! 0x2 = priv sw trap, 0x3=hpriv sw trap ..
wrhpr %l1, 0x20, %hpstate
! Shift stack down by 1 ...
! If TT != 2, then goto trap handler
stxa %l1, [%g0] ASI_LSU_CTL_REG
SECTION .VaHOLE_PA_0 TEXT_VA = 0x000000ffffffe000