// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: tlu.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
<runargs -vcs_run_args=+noredwdrkill>
//--------------------------------LONG-------------------------------------
<sys(tlu_long) name=sys(tlu_long)>
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
tlu_rand01_ind_02 tlu_rand01_ind_02.s
tlu_rand02_ind_07 tlu_rand02_ind_07.s
tlu_rand02_ind_08 tlu_rand02_ind_08.s
tlu_rand02_ind_09 tlu_rand02_ind_09.s
tlu_rand02_ind_10 tlu_rand02_ind_10.s
// For long running diags in FC.
tlu_rand03_ind_03 tlu_rand03_ind_03.s
tlu_rand03_ind_04 tlu_rand03_ind_04.s
tlu_rand03_ind_07 tlu_rand03_ind_07.s
tlu_rand03_ind_08 tlu_rand03_ind_08.s
tlu_rand03_ind_05 tlu_rand03_ind_05.s
tlu_rand03_ind_06 tlu_rand03_ind_06.s
tlu_rand03_ind_09 tlu_rand03_ind_09.s
#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
tlu_rand04_ind_02 tlu_rand04_ind_02.s
tlu_rand04_ind_03 tlu_rand04_ind_03.s
tlu_rand04_ind_04 tlu_rand04_ind_04.s
tlu_rand04_ind_19 tlu_rand04_ind_19.s
tlu_rand04_ind_21 tlu_rand04_ind_21.s
tlu_rand04_ind_22 tlu_rand04_ind_22.s
// TLU rand5 diags use user events .
tlu_rand05_ind_04_08_9 tlu_rand05_ind_04_08_9.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on
tlu_rand05_ind_04_08_10 tlu_rand05_ind_04_08_10.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_stb_on
tlu_rand05_ind_04_15_1 tlu_rand05_ind_04_15_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_04_27_1 tlu_rand05_ind_04_27_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_sca_on
tlu_rand05_ind_04_27_3 tlu_rand05_ind_04_27_3.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_05_02_5 tlu_rand05_ind_05_02_5.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_sca_on
tlu_rand05_ind_05_02_8 tlu_rand05_ind_05_02_8.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_05_03_1 tlu_rand05_ind_05_03_1.s
tlu_rand05_ind_05_11_3 tlu_rand05_ind_05_11_3.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_05_19_1 tlu_rand05_ind_05_19_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
tlu_rand05_ind_06_10_4 tlu_rand05_ind_06_10_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
tlu_rand05_ind_06_14_10 tlu_rand05_ind_06_14_10.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_itlb_on
tlu_rand05_ind_06_17_3 tlu_rand05_ind_06_17_3.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_06_20_9 tlu_rand05_ind_06_20_9.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
tlu_rand05_ind_06_27_5 tlu_rand05_ind_06_27_5.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
tlu_rand05_ind_06_20_6 tlu_rand05_ind_06_20_6.s -vcs_run_args=+err_ic_on
tlu_rand05_ind_07_28_1 tlu_rand05_ind_07_28_1.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_07_28_3 tlu_rand05_ind_07_28_3.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_08_01_3 tlu_rand05_ind_08_01_3.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_08_04_5 tlu_rand05_ind_08_04_5.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_08_04_6 tlu_rand05_ind_08_04_6.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_tcc_on
tlu_rand05_ind_08_04_2 tlu_rand05_ind_08_04_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
tlu_rand05_ind_08_05_3 tlu_rand05_ind_08_05_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on
tlu_rand05_ind_08_17_5 tlu_rand05_ind_08_17_5.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_08_22_1 tlu_rand05_ind_08_22_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_08_22_4 tlu_rand05_ind_08_22_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_08_29_7 tlu_rand05_ind_08_29_7.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_08_31_1 tlu_rand05_ind_08_31_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_08_31_2 tlu_rand05_ind_08_31_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_08_31_5 tlu_rand05_ind_08_31_5.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_08_31_6 tlu_rand05_ind_08_31_6.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_09_01_3 tlu_rand05_ind_09_01_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on
tlu_rand05_ind_09_01_4 tlu_rand05_ind_09_01_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on
tlu_rand05_ind_09_02_1 tlu_rand05_ind_09_02_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_09_02_2 tlu_rand05_ind_09_02_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on
tlu_rand05_ind_09_07_5 tlu_rand05_ind_09_07_5.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_09_08_7 tlu_rand05_ind_09_08_7.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_09_1 tlu_rand05_ind_09_09_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_15_6 tlu_rand05_ind_09_15_6.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_20_4 tlu_rand05_ind_09_20_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_22_1 tlu_rand05_ind_09_22_1.s -vcs_run_args=+ssModeFreq=2200
tlu_rand05_ind_09_22_2 tlu_rand05_ind_09_22_2.s -vcs_run_args=+ssModeFreq=2200 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on -vcs_run_args=+err_dsfsr_chkr_on
tlu_rand05_ind_09_26_1 tlu_rand05_ind_09_26_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on -vcs_run_args=+ssModeFreq=2200 -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on
tlu_rand05_ind_09_26_3 tlu_rand05_ind_09_26_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_26_4 tlu_rand05_ind_09_26_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_27_1 tlu_rand05_ind_09_27_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on -vcs_run_args=+ssModeFreq=2200 -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on
tlu_rand05_ind_09_27_3 tlu_rand05_ind_09_27_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_27_4 tlu_rand05_ind_09_27_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_29_1 tlu_rand05_ind_09_29_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on -vcs_run_args=+doModeFreq=2200 -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on
tlu_rand05_ind_09_29_2 tlu_rand05_ind_09_29_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_29_3 tlu_rand05_ind_09_29_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_itlb_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_29_5 tlu_rand05_ind_09_29_5.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_09_29_7 tlu_rand05_ind_09_29_7.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
tlu_rand05_ind_10_04_3 tlu_rand05_ind_10_04_3.s -vcs_run_args=+ssModeFreq=2000 -vcs_run_args=+ssModeMaxSessions=100 -vcs_run_args=+ssModeMin=1000 -vcs_run_args=+ssModeMax=1500 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on -vcs_run_args=+err_dsfsr_chkr_on
tlu_rand05_ind_10_04_4 tlu_rand05_ind_10_04_4.s -vcs_run_args=+doModeFreq=2200 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on -vcs_run_args=+err_dsfsr_chkr_on
tlu_rand05_ind_10_13_1 tlu_rand05_ind_10_13_1.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_10_31_3 tlu_rand05_ind_10_31_3.s -vcs_run_args=+err_sync_on
tlu_rand05_ind_11_13 tlu_rand05_ind_11_13.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
tlu_rand05_ind_11_27 tlu_rand05_ind_11_27.s -vcs_run_args=+err_sync_on -midas_args=-DCREGS_LSU_CTL_REG_DC=0
tlu_trap_state_ind_01_31_1 tlu_trap_state_ind_01_31_1.s
tlu_trap_state_ind_01_31_2 tlu_trap_state_ind_01_31_2.s
tlu_trap_state_ind_01_31_3 tlu_trap_state_ind_01_31_3.s
bug_112121_case3 bug_112121_case3.s
bug_112121_case2 bug_112121_case2.s
bug_112121_case1 bug_112121_case1.s
</runargs> // -vcs_run_args=+thread=all
<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
err_tcc_hstick_diag err_tcc_hstick_diag.s -vcs_run_args=+thread=01
err_tcc_hstick_diag_1 err_tcc_hstick_diag.s -vcs_run_args=+thread=02
err_tcc_hstick_diag_2 err_tcc_hstick_diag.s -vcs_run_args=+thread=04
err_tcc_hstick_diag_3 err_tcc_hstick_diag.s -vcs_run_args=+thread=08
err_tcc_hstick_diag_4 err_tcc_hstick_diag.s -vcs_run_args=+thread=10
err_tcc_hstick_diag_5 err_tcc_hstick_diag.s -vcs_run_args=+thread=20
err_tcc_hstick_diag_6 err_tcc_hstick_diag.s -vcs_run_args=+thread=40
err_tcc_hstick_diag_7 err_tcc_hstick_diag.s -vcs_run_args=+thread=80
err_tcc_stick_diag err_tcc_stick_diag.s -vcs_run_args=+thread=01
err_tcc_stick_diag_1 err_tcc_stick_diag.s -vcs_run_args=+thread=02
err_tcc_stick_diag_2 err_tcc_stick_diag.s -vcs_run_args=+thread=04
err_tcc_stick_diag_3 err_tcc_stick_diag.s -vcs_run_args=+thread=08
err_tcc_stick_diag_4 err_tcc_stick_diag.s -vcs_run_args=+thread=10
err_tcc_stick_diag_5 err_tcc_stick_diag.s -vcs_run_args=+thread=20
err_tcc_stick_diag_6 err_tcc_stick_diag.s -vcs_run_args=+thread=40
err_tcc_stick_diag_7 err_tcc_stick_diag.s -vcs_run_args=+thread=80
err_tcc_tick_diag err_tcc_tick_diag.s -vcs_run_args=+thread=01
err_tcc_tick_diag_1 err_tcc_tick_diag.s -vcs_run_args=+thread=02
err_tcc_tick_diag_2 err_tcc_tick_diag.s -vcs_run_args=+thread=04
err_tcc_tick_diag_3 err_tcc_tick_diag.s -vcs_run_args=+thread=08
err_tcc_tick_diag_4 err_tcc_tick_diag.s -vcs_run_args=+thread=10
err_tcc_tick_diag_5 err_tcc_tick_diag.s -vcs_run_args=+thread=20
err_tcc_tick_diag_6 err_tcc_tick_diag.s -vcs_run_args=+thread=40
err_tcc_tick_diag_7 err_tcc_tick_diag.s -vcs_run_args=+thread=80
err_inj_mondo_diag err_inj_mondo_diag.s -vcs_run_args=+thread=01
err_inj_mondo_diag_1 err_inj_mondo_diag.s -vcs_run_args=+thread=02
err_inj_mondo_diag_2 err_inj_mondo_diag.s -vcs_run_args=+thread=04
err_inj_mondo_diag_3 err_inj_mondo_diag.s -vcs_run_args=+thread=08
err_inj_mondo_diag_4 err_inj_mondo_diag.s -vcs_run_args=+thread=10
err_inj_mondo_diag_5 err_inj_mondo_diag.s -vcs_run_args=+thread=20
err_inj_mondo_diag_6 err_inj_mondo_diag.s -vcs_run_args=+thread=40
err_inj_mondo_diag_7 err_inj_mondo_diag.s -vcs_run_args=+thread=80
err_tsa_diag err_tsa_diag.s -vcs_run_args=+thread=01
err_tsa_diag_1 err_tsa_diag.s -vcs_run_args=+thread=02
err_tsa_diag_2 err_tsa_diag.s -vcs_run_args=+thread=04
err_tsa_diag_3 err_tsa_diag.s -vcs_run_args=+thread=08
err_tsa_diag_4 err_tsa_diag.s -vcs_run_args=+thread=10
err_tsa_diag_5 err_tsa_diag.s -vcs_run_args=+thread=20
err_tsa_diag_6 err_tsa_diag.s -vcs_run_args=+thread=40
err_tsa_diag_7 err_tsa_diag.s -vcs_run_args=+thread=80
err_ittp_bug_103663 err_ittp_bug_103663.s -vcs_run_args=+thread=01
err_hstick_cmpr_cycle err_hstick_cmpr_cycle.s -vcs_run_args=+thread=01
err_hstick_cmpr_cycle_1 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=02
err_hstick_cmpr_cycle_2 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=04
err_hstick_cmpr_cycle_3 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=08
err_hstick_cmpr_cycle_4 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=10
err_hstick_cmpr_cycle_5 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=20
err_hstick_cmpr_cycle_6 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=40
err_hstick_cmpr_cycle_7 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=80
err_stick_cmpr_cycle err_stick_cmpr_cycle.s -vcs_run_args=+thread=01
err_stick_cmpr_cycle_1 err_stick_cmpr_cycle.s -vcs_run_args=+thread=02
err_stick_cmpr_cycle_2 err_stick_cmpr_cycle.s -vcs_run_args=+thread=04
err_stick_cmpr_cycle_3 err_stick_cmpr_cycle.s -vcs_run_args=+thread=08
err_stick_cmpr_cycle_4 err_stick_cmpr_cycle.s -vcs_run_args=+thread=10
err_stick_cmpr_cycle_5 err_stick_cmpr_cycle.s -vcs_run_args=+thread=20
err_stick_cmpr_cycle_6 err_stick_cmpr_cycle.s -vcs_run_args=+thread=40
err_stick_cmpr_cycle_7 err_stick_cmpr_cycle.s -vcs_run_args=+thread=80
err_tick_cmpr_cycle_c0_n2 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=01
err_tick_cmpr_cycle_c0_n2_1 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=02
err_tick_cmpr_cycle_c0_n2_2 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=04
err_tick_cmpr_cycle_c0_n2_3 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=08
err_tick_cmpr_cycle_c0_n2_4 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=10
err_tick_cmpr_cycle_c0_n2_5 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=20
err_tick_cmpr_cycle_c0_n2_6 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=40
err_tick_cmpr_cycle_c0_n2_7 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=80
err_tick_cmpr_cycle_c1_n2 err_tick_cmpr_cycle_c1_n2.s -vcs_run_args=+thread=01
err_tick_cmpr_ue_n2 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=01
err_tick_cmpr_ue_n2_1 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=02
err_tick_cmpr_ue_n2_2 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=04
err_tick_cmpr_ue_n2_3 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=08
err_tick_cmpr_ue_n2_4 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=10
err_tick_cmpr_ue_n2_5 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=20
err_tick_cmpr_ue_n2_6 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=40
err_tick_cmpr_ue_n2_7 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=80
//err_hstick_cmpr_ue_n2 err_hstick_cmpr_ue_n2.s -vcs_run_args=+thread=01
//err_stick_cmpr_ue_n2 err_stick_cmpr_ue_n2.s -vcs_run_args=+thread=01
//err_stick_cmpr_diag_n2 err_stick_cmpr_diag_n2.s -vcs_run_args=+thread=01
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
#if (defined SPC || defined CMP)
tlu_rand05_ind_10_11_8 tlu_rand05_ind_10_11_8.s
// tlu_rand05_ind_85 tlu_rand05_ind_85.s
// tlu_rand05_ind_88 tlu_rand05_ind_88.s
// tlu_rand05_ind_89 tlu_rand05_ind_89.s
// tlu_rand5_7745150 tlu_rand5_7745150.s
tlu_rand05_ind_89_1 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=1
tlu_rand05_ind_89_2 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=2
tlu_rand05_ind_89_3 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=3
tlu_rand05_ind_89_4 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=4
tlu_rand05_ind_89_5 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=5
tlu_rand05_ind_89_6 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=6
tlu_rand05_ind_89_7 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=7
tlu_rand5_nocmp_8130761 tlu_rand5_nocmp_8130761.s
tlu_rand5_nocmp_8257449 tlu_rand5_nocmp_8257449.s -midas_args=-DMULTIPASS=1 -vcs_run_args=+ssModeFreq=2200 -max_cycle 1500000 -vcs_run_args=+ssModeFreq=2000 -vcs_run_args=+ssModeMaxSessions=75 -vcs_run_args=+ssModeInterleaveWeight=40 -vcs_run_args=+doModeFreq=2000 -vcs_run_args=+doModeMaxSessions=100 -vcs_run_args=+doModeLenMin=3000 -vcs_run_args=+softStopFreq=2000 -vcs_run_args=+softStopMaxSessions=20 -vcs_run_args=+softStopLenMax=50
tlu_rand05_nocmp_20050919 tlu_rand05_nocmp_20050919.s -vcs_run_args=+ssModeFreq=2200 -midas_args=-DMULTIPASS=1
tlu_rand5_7833446 tlu_rand5_7833446.s -midas_args=-DMULTIPASS=2
tlu_rand5_nocmp_8334648 tlu_rand5_nocmp_8334648.s -midas_args=-DMULTIPASS=1 -vcs_run_args=+doModeFreq=2200 -vcs_run_args=+doModeLenMin=300 -vcs_run_args=+doModeLenMax=1000
<runargs -rtl_timeout=20000 -vcs_run_args=+th_timeout=50000 -vcs_run_args=+skt_timeout=20000 -max_cycle 1500000 -vcs_run_args=+ssModeFreq=2000 -vcs_run_args=+ssModeMaxSessions=75 -vcs_run_args=+ssModeInterleaveWeight=40 -vcs_run_args=+doModeFreq=2000 -vcs_run_args=+doModeMaxSessions=100 -vcs_run_args=+doModeLenMin=500 -vcs_run_args=+softStopFreq=2000 -vcs_run_args=+softStopMaxSessions=20 -vcs_run_args=+softStopLenMax=50 >
tlu_rand5_nocmp_8823163 tlu_rand5_nocmp_8823163.s
tlu_rand5_nocmp_8820184 tlu_rand5_nocmp_8820184.s
tlu_rand5_nocmp_8814718 tlu_rand5_nocmp_8814718.s
tlu_rand05_bug_118933 tlu_rand05_bug_118933.s -vcs_run_args=+thread=all -rtl_timeout=20000 -vcs_run_args=+th_timeout=50000 -vcs_run_args=+skt_timeout=20000 -midas_args=-DMULTIPASS=0 -max_cycle 1500000 -vcs_run_args=+err_sync_on -vcs_run_args=+err_l2c_on -vcs_run_args=+err_l2c_freq=40 -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+err_stb_on -vcs_run_args=+err_tcc_on
tlu_rand5spu_8687845 tlu_rand5spu_8687845.s -rtl_timeout=10000 -vcs_run_args=+th_timeout=50000 -max_cycle=1500000
// tlu_rand5err_10529315 tlu_rand5err_10529315.s -rtl_timeout=20000 -vcs_run_args=+th_timeout=50000 -vcs_run_args=+skt_timeout=20000 -midas_args=-DMULTIPASS=0 -max_cycle 2000000 -vcs_run_args=+err_sync_on -vcs_run_args=+err_stb_on -midas_args=-DINC_ERR_TRAPS
tlu_rand5stress_10530146 tlu_rand5stress_10530146.s -rtl_timeout=2000 -vcs_run_args=+th_timeout=20000 -midas_args=-DMULTIPASS=1 -max_cycle=2000000
#if (defined SPC || defined CMP1 || defined CMP1L2X )
// tlu_rand05_ind_01_15_1 tlu_rand05_ind_01_15_1.s
// tlu_rand05_ind_01_24_3 tlu_rand05_ind_01_24_3.s
// tlu_rand05_ind_01_28_1 tlu_rand05_ind_01_28_1.s
// tlu_rand05_ind_12_15_3 tlu_rand05_ind_12_15_3.s
// tlu_rand05_ind_04_27_2 tlu_rand05_ind_04_27_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_sca_on
// tlu_rand05_ind_34 tlu_rand05_ind_34.s
// tlu_rand05_ind_36 tlu_rand05_ind_36.s
// tlu_rand05_ind_37 tlu_rand05_ind_37.s
// tlu_rand05_ind_38 tlu_rand05_ind_38.s
// tlu_rand05_ind_41 tlu_rand05_ind_41.s
// tlu_rand05_ind_42 tlu_rand05_ind_42.s
// tlu_rand05_ind_53 tlu_rand05_ind_53.s
// tlu_rand05_ind_57 tlu_rand05_ind_57.s
// tlu_rand05_ind_60 tlu_rand05_ind_60.s
// tlu_rand05_ind_63 tlu_rand05_ind_63.s
tlu_swtraps tlu_swtraps.pal
// tlu_rand05_ind_69 tlu_rand05_ind_69.s
// tlu_rand05_ind_72 tlu_rand05_ind_72.s
</runargs> // -vcs_run_args=+thread=all
<sys(tlu_fast) name=sys(tlu_fast)>
//--------------------------------FAST-------------------------------------
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
tlu_allintvec1 tlu_allintvec1.s
tlu_allintvec2 tlu_allintvec2.s
tlu_simulint tlu_simulint.s -vcs_run_args=+err_chkrs_off
spc_hver_minor_mask_rev_0 spc_hver_minor_mask_rev.s
spc_hver_minor_mask_rev_a spc_hver_minor_mask_rev.s -nosas -vcs_run_args=+hver_mask_minor_rev=10 -midas_args=-DHVER_MASK_MINOR_REV=10
spc_hver_minor_mask_rev_f spc_hver_minor_mask_rev.s -nosas -vcs_run_args=+hver_mask_minor_rev=15 -midas_args=-DHVER_MASK_MINOR_REV=15
tlu_registers_1 tlu_registers_1.pal
tlu_win_traps_n2 tlu_win_traps_n2.s
tlu_tba_htba_range tlu_tba_htba_range.s
tlu_ticknpt_user tlu_ticknpt_user.s
tlu_donret_glsat tlu_donret_glsat.s
tlu_vahole_101221 tlu_vahole_101221.s
//tlu_vahole2 tlu_vahole2.s // Cases that are not implemented.
tlu_reset_maxtl tlu_reset_maxtl.s
tlu_reset_maxtl tlu_bug_103663.s
tlu_wr_alltl tlu_wr_alltl.s
tlu_hitl_priv2hpriv tlu_hitl_priv2hpriv.s // Coverage cases
tlu_rand01_ind_01 tlu_rand01_ind_01.s
tlu_rand01_ind_03 tlu_rand01_ind_03.s
tlu_rand01_ind_04 tlu_rand01_ind_04.s
tlu_rand01_ind_05 tlu_rand01_ind_05.s
tlu_rand01_ind_06 tlu_rand01_ind_06.s
tlu_rand01_ind_07 tlu_rand01_ind_07.s
tlu_rand01_ind_08 tlu_rand01_ind_08.s
tlu_rand02_ind_01 tlu_rand02_ind_01.s
tlu_rand02_ind_03 tlu_rand02_ind_03.s
tlu_rand02_ind_04 tlu_rand02_ind_04.s
tlu_rand02_ind_05 tlu_rand02_ind_05.s
tlu_rand02_ind_06 tlu_rand02_ind_06.s
tlu_rand03_ind_01 tlu_rand03_ind_01.s
tlu_stick_112960 tlu_stick_112960.s
tlu_queueregsiz_114417 tlu_queueregsiz_114417.s
tlu_tct_ret tlu_tct_ret.s
// TLU ASI diags which need to sync for updates
<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK>
tlu_asi_03_08_1 tlu_asi_03_08_1.s
tlu_asi_03_09_1 tlu_asi_03_09_1.s
tlu_asi_03_11_1 tlu_asi_03_11_1.s
tlu_asi_03_16_2 tlu_asi_03_16_2.s
tlu_asi_03_18_2 tlu_asi_03_18_2.s
tlu_asi_04_06_1 tlu_asi_04_06_1.s
</runargs> // -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK
tlu_nonseq_retry_pdist tlu_nonseq_retry_pdist.s
tlu_nonseq_retry_cas tlu_nonseq_retry_cas.s
tlu_nonseq_retry_blk tlu_nonseq_retry_blk.s
tlu_rand04_ind_01 tlu_rand04_ind_01.s
#if (defined SPC || defined CMP1 || defined CMP1L2X || defined CCM1 || defined FC1 )
// tlu_rand05_ind_01_05_2 tlu_rand05_ind_01_05_2.s
tlu_rand05_ind_01_13_1 tlu_rand05_ind_01_13_1.s
// tlu_rand05_ind_01_15_3 tlu_rand05_ind_01_15_3.s
// tlu_rand05_ind_01_27_4 tlu_rand05_ind_01_27_4.s
// tlu_rand05_ind_02_08_4 tlu_rand05_ind_02_08_4.s
// tlu_rand05_ind_03_01_1 tlu_rand05_ind_03_01_1.s
tlu_rand05_ind_39 tlu_rand05_ind_39.s
tlu_rand01_ind_09 tlu_rand01_ind_09.s
// tlu_rand05_ind_39_1 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=1
// tlu_rand05_ind_39_2 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=2
// tlu_rand05_ind_39_3 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=3
// tlu_rand05_ind_39_4 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=4
// tlu_rand05_ind_39_5 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=5
// tlu_rand05_ind_39_6 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=6
// tlu_rand05_ind_39_7 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=7
</runargs> // -vcs_run_args=+thread=all
tlu_rand01_ind_11 tlu_rand01_ind_11.s
tlu_rand02_ind_02 tlu_rand02_ind_02.s
tlu_rand03_ind_02 tlu_rand03_ind_02.s
tlu_rand04_ind_02 tlu_rand04_ind_02.s
tlu_rand04_ind_14 tlu_rand04_ind_14.s
tlu_rand04_ind_15 tlu_rand04_ind_15.s
tlu_rand04_ind_21 tlu_rand04_ind_21.s
tlu_rand03_ind_05 tlu_rand03_ind_05.s
tlu_rand03_ind_06 tlu_rand03_ind_06.s
tlu_rand03_ind_09 tlu_rand03_ind_09.s
tlu_rand04_ind_03 tlu_rand04_ind_03.s
tlu_rand04_ind_04 tlu_rand04_ind_04.s
tlu_rand04_ind_06 tlu_rand04_ind_06.s
tlu_rand04_ind_07 tlu_rand04_ind_07.s
tlu_rand04_ind_16 tlu_rand04_ind_16.s
tlu_rand04_ind_19 tlu_rand04_ind_19.s
tlu_rand04_ind_20 tlu_rand04_ind_20.s
tlu_rand04_ind_22 tlu_rand04_ind_22.s
tlu_rand04_ind_08 tlu_rand04_ind_08.s
tlu_rand04_ind_11 tlu_rand04_ind_11.s -vcs_run_args=+thread=e7
tlu_rand04_ind_11 tlu_rand04_ind_11.s -midas_args=-DCMP_THREAD_START=0xe7 -finish_mask=e7
#if (defined SPC || defined CMP)
tlu_iaw_range_1 tlu_iaw_range.s -vcs_run_args=+thread=11
tlu_iaw_range_2 tlu_iaw_range.s -vcs_run_args=+thread=22
tlu_iaw_range_3 tlu_iaw_range.s -vcs_run_args=+thread=44
tlu_iaw_range_4 tlu_iaw_range.s -vcs_run_args=+thread=88
tlu_107450_mt tlu_107450_mt.s
// Disrupting Traps (Old & New)
<sys(tlu_disrupting) name=tlu_disrupting>
#if (defined SPC || defined CMP)
tlu_rand05_ind_08 tlu_rand05_ind_08.s
tlu_rand05_ind_10 tlu_rand05_ind_10.s
tlu_rand05_ind_11 tlu_rand05_ind_11.s
tlu_rand05_ind_12 tlu_rand05_ind_12.s
tlu_rand05_ind_15 tlu_rand05_ind_15.s
tlu_rand05_ind_16 tlu_rand05_ind_16.s
#if (defined SPC || defined CMP)
tlu_rand05_ind_01 tlu_rand05_ind_01.s
tlu_rand05_ind_02 tlu_rand05_ind_02.s
tlu_rand05_ind_03 tlu_rand05_ind_03.s
tlu_rand05_ind_04 tlu_rand05_ind_04.s
tlu_rand05_ind_06 tlu_rand05_ind_06.s
tlu_rand05_ind_07 tlu_rand05_ind_07.s
tlu_rand05_ind_01_mt tlu_rand05_ind_01.s -vcs_run_args=+thread=all
// tlu_rand05_ind_23 tlu_rand05_ind_23.s -vcs_run_args=+thread=ff
isa3_1215ivtrap2 isa3_1215ivtrap2.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
// OLD DIAGS from ISA3 days .. not duplicated in nightly/all
isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=all
isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
isa3_xir_121503 isa3_xir_121503.s -vcs_run_args=+thread=all -vcs_run_args=+intr_en=all -vcs_run_args=+intr_vect=3 -vcs_run_args=+intr_type=1 -vcs_run_args=+intr_wait=3000 -vcs_run_args=+intr_delay=100
isa3_1215hsysmatrap isa3_1215hsysmatrap.s -vcs_run_args=+thread=all
isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
// isa3_mod_arith_int_1215_0x3d isa3_mod_arith_int_1215_0x3d.s
isa3_spu_cwq_trap_121503 isa3_spu_cwq_trap_121503.s -rtl_timeout=500000 -max_cycle=+5000000
isa3_1215ivtrap isa3_1215ivtrap.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
isa3_intlevel_121503 isa3_intlevel_121503.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
isa3_mondo_121503 isa3_mondo_121503.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
isa3_xir_121503 isa3_xir_121503.s -midas_args=-DCMP_THREAD_START=all -vcs_run_args=+intr_en=all -vcs_run_args=+intr_vect=3 -vcs_run_args=+intr_type=1 -vcs_run_args=+intr_wait=3000 -vcs_run_args=+intr_delay=100 -finish_mask=all
isa3_1215hsysmatrap isa3_1215hsysmatrap.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1
isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
// isa3_mod_arith_int_1215_0x3d isa3_mod_arith_int_1215_0x3d.s
isa3_spu_cwq_trap_121503 isa3_spu_cwq_trap_121503.s -rtl_timeout=500000 -max_cycle=+5000000
<sys(tlu_riesling) name=sys(tlu_riesling)>
<runargs -vcs_run_args=+thread=all>
<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
tlu_rand05_ind_05_04_3 tlu_rand05_ind_05_04_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on
<sys(tlu_l2cerr) name=sys(tlu_l2cerr)>
<runargs -vcs_run_args=+thread=all -midas_args=-DINC_ERR_TRAPS>
err_soc_l2c_rand0 err_soc_l2c_rand0.s
err_soc_l2c_rand1 err_soc_l2c_rand1.s
err_soc_l2c_rand2 err_soc_l2c_rand2.s
err_soc_l2c_rand3 err_soc_l2c_rand3.s
err_soc_l2c_rand4 err_soc_l2c_rand4.s
err_ifu_l2c_rand0 err_ifu_l2c_rand0.s
err_ifu_l2c_rand1 err_ifu_l2c_rand1.s
err_ifu_l2c_rand2 err_ifu_l2c_rand2.s
err_ifu_l2c_rand3 err_ifu_l2c_rand3.s
err_ifu_l2c_rand4 err_ifu_l2c_rand4.s
err_dcu_l2c_rand0 err_dcu_l2c_rand0.s
err_dcu_l2c_rand1 err_dcu_l2c_rand1.s
err_dcu_l2c_rand2 err_dcu_l2c_rand2.s
err_dcu_l2c_rand3 err_dcu_l2c_rand3.s
err_dcu_l2c_rand4 err_dcu_l2c_rand4.s
err_mmu_l2c_rand0 err_mmu_l2c_rand0.s
err_mmu_l2c_rand1 err_mmu_l2c_rand1.s
err_mmu_l2c_rand2 err_mmu_l2c_rand2.s
err_mmu_l2c_rand3 err_mmu_l2c_rand3.s
err_mmu_l2c_rand4 err_mmu_l2c_rand4.s
<sys(tlu_halt) name=sys(tlu_halt)>
err_dcdp_halt err_dcdp_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
err_tcc_hstick_halt err_tcc_hstick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
err_tcc_stick_halt err_tcc_stick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
err_tcc_tick_halt err_tcc_tick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
tlu_halt_hstmatch tlu_halt_hstmatch.s -vcs_run_args=+thread=all
tlu_halt_intvec tlu_halt_intvec.s -vcs_run_args=+thread=all
// tlu_halt_modint tlu_halt_modint.s -vcs_run_args=+thread=all
// tlu_halt_cwqint tlu_halt_cwqint.s -vcs_run_args=+thread=all
tlu_halt_park tlu_halt_park.s -vcs_run_args=+thread=all
tlu_halt_stickint tlu_halt_stickint.s -vcs_run_args=+thread=all
tlu_halt_tickint tlu_halt_tickint.s -vcs_run_args=+thread=all
tlu_halt_xir tlu_halt_xir.s -vcs_run_args=+thread=all
// tlu_intspu_stb_118933 tlu_intspu_stb_118933.s -vcs_run_args=thread=all
err_dcl2c_halt err_dcl2c_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
err_dcl2u_halt err_dcl2u_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
tlu_halt_modint_desr tlu_halt_modint.s -midas_args=-DINJECT_ERR
tlu_halt_cwqint_desr tlu_halt_cwqint.s -midas_args=-DINJECT_ERR
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