verif/env/common/coverage/fc/fc_cov.if.vrhpal

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fc_cov.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
#ifndef INC_FC_COV_IF_VRH
#define INC_FC_COV_IF_VRH

#include <vera_defines.vrh>
#include "fc_cov_defines.vrh"
/////////////////////////////////////////////////////////////////////////////////////////////////
//This interface works with the verilog module csr_cabinet, which contains references to different
//CSR's and other environment related variables.
/////////////////////////////////////////////////////////////////////////////////////////////////
interface fc_modes_cov_if   {
   input clk CLOCK verilog_node "`TOP.core_clk";

   input [5:0] pll_div1 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div1";
   input [5:0] pll_div2 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div2";
   input [5:0] pll_div3 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div3";
   input [5:0] pll_div4 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.ccu_ctl_reg_div4";

   input [1:0] system_clock  INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.system_clock";

   input [22:0] l2_ctl_reg   INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.l2_ctl_reg";

   input [4:0] mem_density   INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.mem_density";

   input rank_sel      INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.rank_sel";

   input single_channel    INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.single_channel";

   input stack_dimm    INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.stack_dimm";

   input [2:0] no_of_dimms INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.no_of_dimms";

   input ncu_clk_ratio INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.ncu_clk_ratio";

   input hash_enable INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.hash_enable";

   input [2:0] pcie_mps  INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.pcie_mps";

   input [2:0] pcie_ref_clk INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.pcie_ref_clk";

   input RANDOM_REDUNDANCY_VALUES INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.RANDOM_REDUNDANCY_VALUES";

   input RANDOM_POR_RST  INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.RANDOM_POR_RST";

   input RANDOM_PB_RST  INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.RANDOM_PB_RST";

   input amb_used  INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.amb_used";

   input [3:0] denali_link_width  INPUT_EDGE INPUT_SKEW verilog_node "`TOP.csr_cabinet.denali_link_width";

   input boot_done  INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.boot_done";

//Partial mode signals
   input        spc0_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc0_core_available";
   input        spc1_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc1_core_available";
   input        spc2_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc2_core_available";
   input        spc3_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc3_core_available";
   input        spc4_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc4_core_available";
   input        spc5_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc5_core_available";
   input        spc6_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc6_core_available";
   input        spc7_core_available INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.spc7_core_available";


   input        l2t_pm INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.l2t_pm";
   input        l2t_ba01 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.l2t_ba01";
   input        l2t_ba23 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.l2t_ba23";
   input        l2t_ba45 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.l2t_ba45";
   input        l2t_ba67 INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.l2t_ba67";

//sun4v mode
   input        sun4v_mode INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.sun4v_mode";

//FIRE dead lock

   input        p2d_npwr_stall_en        INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.p2d_npwr_stall_en";
   input        im2crm_ilu_stall_en      INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.im2crm_ilu_stall_en";
//power_throttle

   input        power_throttle_en        INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.power_throttle_en";
//FSR_RTL used
   input        FSR_RTL          INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.FSR_RTL";
//scrub happened in one of the L2 banks
   input        scrub_happened           INPUT_EDGE    INPUT_SKEW  verilog_node "`TOP.csr_cabinet.scrub_happened";

}

//FC coverage object interface files
interface fc_cov_ccx {

        input           clk     CLOCK                           verilog_node "`TOP.core_clk";

.for($b=0; $b<=7; $b++){
        input   [129:0] spc${b}_pcx_data_pa     INPUT_EDGE      INPUT_SKEW      verilog_node "`CCX.spc${b}_pcx_data_pa";
        input   [8:0]   spc${b}_pcx_req_pq      INPUT_EDGE      INPUT_SKEW      verilog_node "`CCX.spc${b}_pcx_req_pq";

        input   [145:0] cpx_spc${b}_data_cx2    INPUT_EDGE      INPUT_SKEW      verilog_node "`CCX.cpx_spc${b}_data_cx2";

.}
        input   [7:0]   cpx_io_grant_cx         INPUT_EDGE      INPUT_SKEW      verilog_node "`CCX.cpx_io_grant_cx";
}

// ***********************************************************
// SIGNALS FOR RAS VCOs - MAQ
// ***********************************************************
interface fc_MCU_L2_NCU_ESR_intf
{
input           clk                     CLOCK                        verilog_node "`MCU0.iol2clk";
input           mcu_meu_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_meu_error";
input           mcu_mec_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_mec_error";
input           mcu_dac_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_dac_error";
input           mcu_dau_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_dau_error";
input           mcu_dsc_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_dsc_error";
input           mcu_dsu_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_dsu_error";
input           mcu_dbu_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_dbu_error";
input           mcu_meb_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_meb_error";
input           mcu_fbu_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_fbu_error";
input           mcu_fbr_error           PSAMPLE      INPUT_SKEW      verilog_node "`MCU0.rdpctl.rdpctl_fbr_error";


input [63:0]    l2_esr                  PSAMPLE      INPUT_SKEW      verilog_node "tb_top.cpu.l2t0.csr.csr_l2_errstate_reg[63:0]";

input [63:0]    ncu_esr                 PSAMPLE      INPUT_SKEW      verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_esr[63:0]";
}

#endif

interface fc_cov_ncu {

        input           clk     CLOCK                           verilog_node "`TOP.core_clk";
        input   [145:0] ncu_cpx_data    INPUT_EDGE      INPUT_SKEW      verilog_node "`NCU.ncu_cpx_data_ca";

}

interface fc_cov_l2 {

        input           clk     CLOCK                           verilog_node "`TOP.core_clk";
        input   [145:0] l2t0_cpx_data   INPUT_EDGE      INPUT_SKEW      verilog_node "tb_top.cpu.l2t0.l2t_cpx_data_ca";

}