Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / ilu_peu / ilu_peu_pm_state_sample.vrh
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ilu_peu_pm_state_sample.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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#define IDLE 4'b0000
#define PM_NAK 4'b0001
#define PM_NAK_WAIT 4'b0010
#define PM_ACK_ASPM_L1 4'b0011
#define PM_ACK_L1 4'b0100
#define PM_ACK_L23 4'b0101
#define PM_TRANS_L0 4'b0110
#define PM_TRANS_L0_ASPM_L1 4'b0111
#define PM_TRANS_L0_L1 4'b1000
#define PM_TRANS_L0_L23 4'b1001
#define PM_TIMEOUT 4'b1010
#define PM_ACK_FLUSH_ASPM_L1 4'b1011
#define PM_ACK_FLUSH_PME_L1 4'b1100
#define PM_ACK_FLUSH_L23 4'b1101
sample ilu_peu_coverage_pmc_state_coverage_group.lpm2ctb_pmc_state
{
state s_IDLE (IDLE);
state s_PM_NAK (PM_NAK);
state s_PM_NAK_WAIT (PM_NAK_WAIT);
state s_PM_ACK_ASPM_L1 (PM_ACK_ASPM_L1);
state s_PM_ACK_L1 (PM_ACK_L1);
state s_PM_ACK_L23 (PM_ACK_L23);
state s_PM_TRANS_L0 (PM_TRANS_L0);
state s_PM_TRANS_L0_ASPM_L1 (PM_TRANS_L0_ASPM_L1);
state s_PM_TRANS_L0_L1 (PM_TRANS_L0_L1);
state s_PM_TRANS_L0_L23 (PM_TRANS_L0_L23);
state s_PM_TIMEOUT (PM_TIMEOUT);
state s_PM_ACK_FLUSH_ASPM_L1 (PM_ACK_FLUSH_ASPM_L1);
state s_PM_ACK_FLUSH_PME_L1 (PM_ACK_FLUSH_PME_L1);
state s_PM_ACK_FLUSH_L23 (PM_ACK_FLUSH_L23);
// trans t_IDLE_IDLE_01 (IDLE -> IDLE);
trans t_IDLE_PM_TRANS_L0_02 (IDLE -> PM_TRANS_L0);
// trans t_IDLE_PM_TIMEOUT_03 (IDLE -> PM_TIMEOUT);
// trans t_IDLE_PM_ACK_L1_04 (IDLE -> PM_ACK_L1);
// trans t_IDLE_PM_ACK_L23_05 (IDLE -> PM_ACK_L23);
// trans t_IDLE_PM_NAK_06 (IDLE -> PM_NAK);
// trans t_IDLE_PM_ACK_ASPM_L1_07 (IDLE -> PM_ACK_ASPM_L1);
trans t_PM_NAK_PM_NAK_WAIT_03 (PM_NAK -> PM_NAK_WAIT);
// trans t_PM_NAK_PM_NAK_04 (PM_NAK -> PM_NAK);
trans t_PM_NAK_WAIT_IDLE_05 (PM_NAK_WAIT -> IDLE);
// trans t_PM_NAK_WAIT_PM_NAK_WAIT_06 (PM_NAK_WAIT -> PM_NAK_WAIT);
trans t_PM_ACK_ASPM_L1_PM_TRANS_L0_ASPM_L1_07 (PM_ACK_ASPM_L1 -> PM_TRANS_L0_ASPM_L1);
trans t_PM_ACK_ASPM_L1_IDLE_08 (PM_ACK_ASPM_L1 -> IDLE);
// trans t_PM_ACK_ASPM_L1_PM_ACK_ASPM_L1_09 (PM_ACK_ASPM_L1 -> PM_ACK_ASPM_L1);
trans t_PM_ACK_ASPM_L1_PM_ACK_FLUSH_ASPM_L1 (PM_ACK_ASPM_L1 -> PM_ACK_FLUSH_ASPM_L1);
trans t_PM_ACK_L1_PM_TRANS_L0_L1_10 (PM_ACK_L1 -> PM_TRANS_L0_L1);
trans t_PM_ACK_L1_IDLE_11 (PM_ACK_L1 -> IDLE);
// trans t_PM_ACK_L1_PM_ACK_L1_12 (PM_ACK_L1 -> PM_ACK_L1);
trans t_PM_ACK_L23_PM_TRANS_L0_L23_13 (PM_ACK_L23 -> PM_TRANS_L0_L23);
// trans t_PM_ACK_L23_IDLE_14 (PM_ACK_L23 -> IDLE);
// trans t_PM_ACK_L23_PM_ACK_L23_15 (PM_ACK_L23 -> PM_ACK_L23);
trans t_PM_TRANS_L0_IDLE_16 (PM_TRANS_L0 -> IDLE );
// trans t_PM_TRANS_L0_PM_TRANS_L0_17 (PM_TRANS_L0 -> PM_TRANS_L0 );
trans t_PM_TRANS_L0_ASPM_L1_PM_ACK_ASPM_L1_18 (PM_TRANS_L0_ASPM_L1 -> PM_ACK_ASPM_L1);
// trans t_PM_TRANS_L0_ASPM_L1_PM_TRANS_L0_ASPM_L1_19 (PM_TRANS_L0_ASPM_L1 -> PM_TRANS_L0_ASPM_L1);
trans t_PM_TRANS_L0_L1_PM_ACK_L1_20 (PM_TRANS_L0_L1 -> PM_ACK_L1);
// trans t_PM_TRANS_L0_L1_PM_TRANS_L0_L1_21 (PM_TRANS_L0_L1 -> PM_TRANS_L0_L1);
trans t_PM_TRANS_L0_L23_PM_ACK_L23_22 (PM_TRANS_L0_L23 -> PM_ACK_L23);
// trans t_PM_TRANS_L0_L23_PM_TRANS_L0_L23_23 (PM_TRANS_L0_L23 -> PM_TRANS_L0_L23);
trans t_PM_TIMEOUT_IDLE_24 (PM_TIMEOUT -> IDLE);
// trans t_PM_TIMEOUT_PM_TIMEOUT_25 (PM_TIMEOUT -> PM_TIMEOUT);
trans t_PM_ACK_FLUSH_ASPM_L1_IDLE_26 (PM_ACK_FLUSH_ASPM_L1 -> IDLE);
trans t_PM_ACK_FLUSH_PME_L1_IDLE_27 (PM_ACK_FLUSH_PME_L1 -> IDLE);
trans t_PM_ACK_FLUSH_L23_IDLE_28 (PM_ACK_FLUSH_L23 -> IDLE);
}