Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_siu_fields_sample.vrhpal
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: l2_siu_fields_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
wildcard state JBI_CTAG15_0 ({1'b1, 6'bx, 1'b0, 1'bx, 1'b0, 15'bx, 8'bx});
wildcard state JBI_CTAG15_1 ({1'b1, 6'bx, 1'b0, 1'bx, 1'b1, 15'bx, 8'bx});
wildcard state JBI_CTAG14_0 ({1'b1, 6'bx, 1'b0, 1'bx, 1'bx, 1'b0, 14'bx, 8'bx});
wildcard state JBI_CTAG14_1 ({1'b1, 6'bx, 1'b0, 1'bx, 1'bx, 1'b1, 14'bx, 8'bx});
wildcard state JBI_CTAG13_0 ({1'b1, 6'bx, 1'b0, 1'bx, 2'bx, 1'b0, 13'bx, 8'bx});
wildcard state JBI_CTAG13_1 ({1'b1, 6'bx, 1'b0, 1'bx, 2'bx, 1'b1, 13'bx, 8'bx});
wildcard state JBI_CTAG12_0 ({1'b1, 6'bx, 1'b0, 1'bx, 3'bx, 1'b0, 12'bx, 8'bx});
wildcard state JBI_CTAG12_1 ({1'b1, 6'bx, 1'b0, 1'bx, 3'bx, 1'b1, 12'bx, 8'bx});
wildcard state JBI_CTAG11_0 ({1'b1, 6'bx, 1'b0, 1'bx, 4'bx, 1'b0, 11'bx, 8'bx});
wildcard state JBI_CTAG11_1 ({1'b1, 6'bx, 1'b0, 1'bx, 4'bx, 1'b1, 11'bx, 8'bx});
wildcard state JBI_CTAG10_0 ({1'b1, 6'bx, 1'b0, 1'bx, 5'bx, 1'b0, 10'bx, 8'bx});
wildcard state JBI_CTAG10_1 ({1'b1, 6'bx, 1'b0, 1'bx, 5'bx, 1'b1, 10'bx, 8'bx});
wildcard state JBI_CTAG9_0 ({1'b1, 6'bx, 1'b0, 1'bx, 6'bx, 1'b0, 9'bx, 8'bx});
wildcard state JBI_CTAG9_1 ({1'b1, 6'bx, 1'b0, 1'bx, 6'bx, 1'b1, 9'bx, 8'bx});
wildcard state JBI_CTAG8_0 ({1'b1, 6'bx, 1'b0, 1'bx, 7'bx, 1'b0, 8'bx, 8'bx});
wildcard state JBI_CTAG8_1 ({1'b1, 6'bx, 1'b0, 1'bx, 7'bx, 1'b1, 8'bx, 8'bx});
wildcard state JBI_CTAG7_0 ({1'b1, 6'bx, 1'b0, 1'bx, 8'bx, 1'b0, 7'bx, 8'bx});
wildcard state JBI_CTAG7_1 ({1'b1, 6'bx, 1'b0, 1'bx, 8'bx, 1'b1, 7'bx, 8'bx});
wildcard state JBI_CTAG6_0 ({1'b1, 6'bx, 1'b0, 1'bx, 9'bx, 1'b0, 6'bx, 8'bx});
wildcard state JBI_CTAG6_1 ({1'b1, 6'bx, 1'b0, 1'bx, 9'bx, 1'b1, 6'bx, 8'bx});
wildcard state JBI_CTAG5_0 ({1'b1, 6'bx, 1'b0, 1'bx,10'bx, 1'b0, 5'bx, 8'bx});
wildcard state JBI_CTAG5_1 ({1'b1, 6'bx, 1'b0, 1'bx,10'bx, 1'b1, 5'bx, 8'bx});
wildcard state JBI_CTAG4_0 ({1'b1, 6'bx, 1'b0, 1'bx,11'bx, 1'b0, 4'bx, 8'bx});
wildcard state JBI_CTAG4_1 ({1'b1, 6'bx, 1'b0, 1'bx,11'bx, 1'b1, 4'bx, 8'bx});
wildcard state JBI_CTAG3_0 ({1'b1, 6'bx, 1'b0, 1'bx,12'bx, 1'b0, 3'bx, 8'bx});
wildcard state JBI_CTAG3_1 ({1'b1, 6'bx, 1'b0, 1'bx,12'bx, 1'b1, 3'bx, 8'bx});
wildcard state JBI_CTAG2_0 ({1'b1, 6'bx, 1'b0, 1'bx,13'bx, 1'b0, 2'bx, 8'bx});
wildcard state JBI_CTAG2_1 ({1'b1, 6'bx, 1'b0, 1'bx,13'bx, 1'b1, 2'bx, 8'bx});
wildcard state JBI_CTAG1_0 ({1'b1, 6'bx, 1'b0, 1'bx,14'bx, 1'b0, 1'bx, 8'bx});
wildcard state JBI_CTAG1_1 ({1'b1, 6'bx, 1'b0, 1'bx,14'bx, 1'b1, 1'bx, 8'bx});
wildcard state JBI_CTAG0_0 ({1'b1, 6'bx, 1'b0, 1'bx,15'bx, 1'b0, 8'bx});
wildcard state JBI_CTAG0_1 ({1'b1, 6'bx, 1'b0, 1'bx,15'bx, 1'b1, 8'bx});
//JOPES bits
wildcard state JBI_WRI_J_0 ({1'b1, 5'b0xxxx, 3'b100, 24'bx});
#ifndef FC_COVERAGE
wildcard state JBI_WRI_J_1 ({1'b1, 5'b1xxxx, 3'b100, 24'bx}); // no JTAG in FC
#endif
wildcard state JBI_WRI_O_0 ({1'b1, 5'bx0xxx, 3'b100, 24'bx});
wildcard state JBI_WRI_O_1 ({1'b1, 5'bx1xxx, 3'b100, 24'bx});
wildcard state JBI_WRI_P_0 ({1'b1, 5'bxx0xx, 3'b100, 24'bx});
wildcard state JBI_WRI_P_1 ({1'b1, 5'bxx1xx, 3'b100, 24'bx});
wildcard state JBI_WRI_E_0 ({1'b1, 5'bxxx0x, 3'b100, 24'bx});
wildcard state JBI_WRI_E_1 ({1'b1, 5'bxxx1x, 3'b100, 24'bx});
wildcard state JBI_WRI_S_0 ({1'b1, 5'bxxxx0, 3'b100, 24'bx});
wildcard state JBI_WRI_S_1 ({1'b1, 5'bxxxx1, 3'b100, 24'bx});
wildcard state JBI_WR8_J_0 ({1'b1, 5'b0xxxx, 3'b010, 24'bx});
#ifndef FC_COVERAGE
wildcard state JBI_WR8_J_1 ({1'b1, 5'b1xxxx, 3'b010, 24'bx}); // no JTAG in FC
wildcard state JBI_WR8_O_0 ({1'b1, 5'bx0xxx, 3'b010, 24'bx});
wildcard state JBI_WR8_P_0 ({1'b1, 5'bxx0xx, 3'b010, 24'bx});
wildcard state JBI_WR8_S_0 ({1'b1, 5'bxxxx0, 3'b010, 24'bx});
#endif
wildcard state JBI_WR8_O_1 ({1'b1, 5'bx1xxx, 3'b010, 24'bx}); // must be 1
wildcard state JBI_WR8_P_1 ({1'b1, 5'bxx1xx, 3'b010, 24'bx}); // must be 1
wildcard state JBI_WR8_E_0 ({1'b1, 5'bxxx0x, 3'b010, 24'bx});
wildcard state JBI_WR8_E_1 ({1'b1, 5'bxxx1x, 3'b010, 24'bx});
wildcard state JBI_WR8_S_1 ({1'b1, 5'bxxxx1, 3'b010, 24'bx}); // must be 1
wildcard state JBI_RDD_J_0 ({1'b1, 5'b0xxxx, 3'b001, 24'bx});
#ifndef FC_COVERAGE
wildcard state JBI_RDD_J_1 ({1'b1, 5'b1xxxx, 3'b001, 24'bx}); // no JTAG in FC
wildcard state JBI_RDD_P_1 ({1'b1, 5'bxx1xx, 3'b001, 24'bx});
#endif
wildcard state JBI_RDD_O_0 ({1'b1, 5'bx0xxx, 3'b001, 24'bx});
wildcard state JBI_RDD_O_1 ({1'b1, 5'bx1xxx, 3'b001, 24'bx});
wildcard state JBI_RDD_P_0 ({1'b1, 5'bxx0xx, 3'b001, 24'bx}); // must be 0
wildcard state JBI_RDD_E_0 ({1'b1, 5'bxxx0x, 3'b001, 24'bx});
wildcard state JBI_RDD_E_1 ({1'b1, 5'bxxx1x, 3'b001, 24'bx});
wildcard state JBI_RDD_S_0 ({1'b1, 5'bxxxx0, 3'b001, 24'bx});
wildcard state JBI_RDD_S_1 ({1'b1, 5'bxxxx1, 3'b001, 24'bx});
// }