verif/env/common/coverage/mcusat/mcusat_rd_wr_schmoo_sample.vrhpal

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: mcusat_rd_wr_schmoo_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
     wildcard state s_rd_wr_vld0                 ({2'b00, 1'bx});
     wildcard state s_rd_wr_vld1                 ({2'b01, 1'bx});
     wildcard state s_rd_wr_vld2                 ({2'b10, 1'bx});
     wildcard state s_rd_wr_vld3                 ({2'b11, 1'bx});
     wildcard state s_rd_wr_scrb_vld_011         ({2'b01, 1'b1});
     state s_rd_wr_scrb_vld_101                  ({2'b10, 1'b1});
     state s_rd_wr_scrb_vld_111                  ({2'b11, 1'b1});


  // transitions(to same)
     wildcard trans t_rd_wr_vld0_0                 ({2'b00, 1'bx} -> {2'b00, 1'bx});
     wildcard trans t_rd_wr_vld1_1                 ({2'b01, 1'bx} -> {2'b01, 1'bx});
     wildcard trans t_rd_wr_vld2_2                 ({2'b10, 1'bx} -> {2'b10, 1'bx});
     wildcard trans t_rd_wr_vld3_3                 ({2'b11, 1'bx} -> {2'b11, 1'bx});

  // transitions(to different)
     wildcard trans t_rd_wr_vld0_1                 ({2'b00, 1'bx} -> {2'b01, 1'bx});
     wildcard trans t_rd_wr_vld1_2                 ({2'b01, 1'bx} -> {2'b10, 1'bx});
     wildcard trans t_rd_wr_vld0_3                 ({2'b00, 1'bx} -> {2'b11, 1'bx});
     wildcard trans t_rd_wr_vld1_3                 ({2'b01, 1'bx} -> {2'b11, 1'bx});
     wildcard trans t_rd_wr_vld2_3                 ({2'b10, 1'bx} -> {2'b11, 1'bx});
     wildcard trans t_rd_wr_vld3_2                 ({2'b11, 1'bx} -> {2'b10, 1'bx});
     trans t_rd_wr_scrb_010_011                    ({2'b01, 1'b0} -> {2'b01, 1'b1});
     trans t_rd_wr_scrb_100_101                    ({2'b10, 1'b0} -> {2'b10, 1'b1});
     trans t_rd_wr_scrb_110_111                    ({2'b11, 1'b0} -> {2'b11, 1'b1});
     trans t_rd_wr_scrb_101_100                    ({2'b10, 1'b1} -> {2'b10, 1'b0});
     trans t_rd_wr_scrb_111_110                    ({2'b11, 1'b1} -> {2'b11, 1'b0});
     //trans t_rd_wr_scrb_011_110                  ({2'b01, 1'b1} -> {2'b11, 1'b0});
     trans t_bad_rd_wr_scrb_011_111                ({2'b01, 1'b1} -> {2'b11, 1'b1});


  // transitions(combinations)

  // bad states
  //bad_state s_not_WR_Q_STATE (not state);

  // bad transitions
  //bad_trans t_not_WR_Q_TRANS (not trans);
//Commenting out following 10 checkers somePerson,08/30/05
//  bad_trans t_bad_rd_wr_vld3_1                  ({2'b11, 1'bx} -> {2'b01, 1'bx});
//  bad_trans t_bad_rd_wr_vld3_0                  ({2'b11, 1'bx} -> {2'b00, 1'bx});
//  bad_trans t_bad_rd_wr_scrb_101_001            ({2'b10, 1'b1} -> {2'b00, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_101_011            ({2'b10, 1'b1} -> {2'b01, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_111_001            ({2'b11, 1'b1} -> {2'b00, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_111_011            ({2'b11, 1'b1} -> {2'b01, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_111_101            ({2'b11, 1'b1} -> {2'b10, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_011_001            ({2'b01, 1'b1} -> {2'b00, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_011_101            ({2'b01, 1'b1} -> {2'b10, 1'b1});
  // a new write cant be issued to same address if a read is pending
 // bad_trans t_bad_rd_wr_scrb_101_111    ({2'b10, 1'b1} -> {2'b11, 1'b1});

// }