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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / ncu / ncu_cov.if.vrhpal
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ncu_cov.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#ifndef INC_NCU_COV_IF_VRH
#define INC_NCU_COV_IF_VRH
#include <vera_defines.vrh>
#include "ncu_cov_defines.vrh"
#define NCU_C2ISC tb_top.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_c2isc_ctl
#define NCU_I2CSD tb_top.cpu.ncu.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csd_ctl
#define NCU_I2CSC tb_top.cpu.ncu.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csc_ctl
#define NCU_C2IFC tb_top.cpu.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifc_ctl
#define NCU_I2CFC tb_top.cpu.ncu.ncu_fcd_ctl.ncu_i2cfcd_ctl.ncu_i2cfc_ctl
interface ncu_cov_ccx {
input clk CLOCK verilog_node "`NCU.gclk";
input ncu_pcx_stall_pq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ncu_pcx_stall_pq";
input ncu_pcx_stall_pq1 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ncu_pcx_stall_pq1";
#ifdef FC_COVERAGE
input pcx_ncu_data_rdy_px1 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_rdy_px1";
input [129:0] pcx_ncu_data_px2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_px2";
input pcx_ncu_data_rdy_px1_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_rdy_px1";
input [129:0] pcx_ncu_data_px2_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_px2";
#else
input pcx_ncu_data_rdy_px1 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_rdy_px1";
input [129:0] pcx_ncu_data_px2 INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_px2";
input pcx_ncu_data_rdy_px1_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.pcx_ncu_data_rdy_px1";
input [129:0] pcx_ncu_data_px2_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.pcx_ncu_data_px2";
#endif
input [7:0] cpx_ncu_grant_cx INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpx_ncu_grant_cx";
input [7:0] ncu_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ncu_cpx_req_cq";
input [7:0] cpx_ncu_grant_cx_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpx_ncu_grant_cx";
input [145:0] ncu_cpx_data_ca INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpx_data_ca";
}
interface ncu_cov_ios {
input clk CLOCK verilog_node "`NCU.iol2clk";
input int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csc_ctl.int_vld";
input lhs_intman_acc INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csc_ctl.lhs_intman_acc";
input [6:0] lhs_intman_addr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.lhs_intman_addr";
input [6:0] io_intman_addr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.io_intman_addr";
input [1:0] ssi_scksel INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncu_scksel";
input ncu_mio_ssi_mosi INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mio_ssi_mosi";
input mio_ncu_ssi_miso INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mio_ncu_ssi_miso";
input mio_ncu_ext_int_l INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mio_ncu_ext_int_l";
input [2:0] ssi_sm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssitop_ctl.ncu_ssisif_ctl.ssi_sm";
input [1:0] if_sm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssitop_ctl.ncu_ssiuif_ctl.if_sm";
//interface ncu_cov_siu
input siu_ncu_req INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_req";
input ncu_siu_gnt INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_gnt";
input [31:0] siu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_data";
input ncu_dmu_mondo_ack INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mondo_ack";
input ncu_dmu_mondo_nack INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mondo_nack";
input [5:0] ncu_dmu_mondo_id INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mondo_id";
input [31:0] siu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_data";
.for($b=0; $b<4; $b++){
//interface ncu_cov_mcu${b}
input mcu${b}_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_stall";
input mcu${b}_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.mcu${b}_ncu_stall_in";
input ncu_mcu${b}_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_vld";
input [3:0] ncu_mcu${b}_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_data";
input ncu_mcu${b}_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_stall";
input mcu${b}_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_vld";
input [3:0] mcu${b}_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_data";
input mcu${b}_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_vld";
input [3:0] mcu${b}_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_data";
.}
//interface ncu_cov_niu
input niu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_stall";
input niu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.niu_ncu_stall_in";
input ncu_niu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_vld";
input [31:0] ncu_niu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_data";
input ncu_niu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_stall";
input niu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_vld";
input [31:0] niu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_data";
input niu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_vld";
input [31:0] niu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_data";
//interface ncu_cov_dmu
input ncu_dmu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_vld";
input [31:0] ncu_dmu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_data";
input dmu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_vld";
input ncu_dmu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_stall";
input [31:0] dmu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_data";
input dmu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_stall";
input dmu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.dmu_ncu_stall_in";
input dmu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_vld";
input [31:0] dmu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_data";
//interface ncu_cov_dmupio
input dmu_ncu_wrack_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_wrack_vld";
input [3:0] dmu_ncu_wrack_tag INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_wrack_tag";
input ncu_dmu_pio_hdr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_pio_hdr_vld";
input ncu_dmu_mmu_addr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_mmu_addr_vld";
input [63:0] ncu_dmu_pio_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_pio_data";
//interface ncu_cov_rst
input [3:0] ncu_rst_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_data";
input rst_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_stall";
input rst_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.rst_ncu_stall_in";
input ncu_rst_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_vld";
input ncu_rst_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_stall";
input rst_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_vld";
input [3:0] rst_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_data";
input rst_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_vld";
input [3:0] rst_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_data";
//interface ncu_cov_tcu
input [7:0] ncu_tcu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_tcu_data";
input tcu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_stall";
input tcu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.tcu_ncu_stall_in";
input ncu_tcu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_tcu_vld";
input ncu_tcu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_tcu_stall";
input tcu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_vld";
input [7:0] tcu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_data";
input tcu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_vld";
input [7:0] tcu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.tcu_ncu_data";
//interface ncu_cov_dbg1
input [3:0] ncu_dbg1_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dbg1_data";
input dbg1_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_stall";
input dbg1_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.dbg1_ncu_stall_in";
input ncu_dbg1_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dbg1_vld";
input ncu_dbg1_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dbg1_stall";
input dbg1_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_vld";
input [3:0] dbg1_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_data";
input dbg1_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_vld";
input [3:0] dbg1_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dbg1_ncu_data";
//interface ncu_cov_ssi
input [3:0] ncu_ssi_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssi_data";
input ssi_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_stall";
input ssi_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ssi_ncu_stall_in";
input ncu_ssi_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssi_vld";
input ncu_ssi_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssi_stall";
input ssi_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_vld";
input [3:0] ssi_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_data";
input ssi_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_vld";
input [3:0] ssi_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ssi_ncu_data";
//interface ncu_cov_ccu
input ccu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_stall";
input ccu_ncu_stall_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.ccu_ncu_stall_in";
input ncu_ccu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ccu_vld";
input [3:0] ncu_ccu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ccu_data";
input ncu_ccu_stall INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ccu_stall";
input ccu_ncu_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_vld";
input [3:0] ccu_ncu_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_data";
input ccu_ncu_vld_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_vld";
input [3:0] ccu_ncu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ccu_ncu_data";
//interface ncu_cov_efu
input efu_ncu_coreavl_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_coreavl_xfer_en";
input efu_ncu_bankavl_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_bankavl_xfer_en";
input efu_ncu_fuse_data INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_fuse_data";
input efu_ncu_fusestat_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_fusestat_xfer_en";
input efu_ncu_srlnum0_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_srlnum0_xfer_en";
input efu_ncu_srlnum1_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_srlnum1_xfer_en";
input efu_ncu_srlnum2_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.efu_ncu_srlnum2_xfer_en";
//interface ncu_cov_asi
input rst_ncu_unpark_thread INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_unpark_thread";
input rst_ncu_xir_ INPUT_EDGE INPUT_SKEW verilog_node "`NCU.rst_ncu_xir_";
input rst_ncu_unpark_thread_in INPUT_EDGE verilog_node "`NCU.rst_ncu_unpark_thread";
input ncu_rst_xir_done INPUT_EDGE verilog_node "`NCU.ncu_rst_xir_done";
input ncu_spc0_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc0_core_available";
input ncu_spc1_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc1_core_available";
input ncu_spc2_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc2_core_available";
input ncu_spc3_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc3_core_available";
input ncu_spc4_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc4_core_available";
input ncu_spc5_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc5_core_available";
input ncu_spc6_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc6_core_available";
input ncu_spc7_core_available INPUT_EDGE verilog_node "`NCU.ncu_spc7_core_available";
input ncu_spc0_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc0_core_enable_status";
input ncu_spc1_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc1_core_enable_status";
input ncu_spc2_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc2_core_enable_status";
input ncu_spc3_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc3_core_enable_status";
input ncu_spc4_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc4_core_enable_status";
input ncu_spc5_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc5_core_enable_status";
input ncu_spc6_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc6_core_enable_status";
input ncu_spc7_core_enable_status INPUT_EDGE verilog_node "`NCU.ncu_spc7_core_enable_status";
input [7:0] ncu_spc0_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc0_core_running";
input [7:0] ncu_spc1_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc1_core_running";
input [7:0] ncu_spc2_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc2_core_running";
input [7:0] ncu_spc3_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc3_core_running";
input [7:0] ncu_spc4_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc4_core_running";
input [7:0] ncu_spc5_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc5_core_running";
input [7:0] ncu_spc6_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc6_core_running";
input [7:0] ncu_spc7_core_running INPUT_EDGE verilog_node "`NCU.ncu_spc7_core_running";
input [7:0] spc0_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc0_ncu_core_running_status";
input [7:0] spc1_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc1_ncu_core_running_status";
input [7:0] spc2_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc2_ncu_core_running_status";
input [7:0] spc3_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc3_ncu_core_running_status";
input [7:0] spc4_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc4_ncu_core_running_status";
input [7:0] spc5_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc5_ncu_core_running_status";
input [7:0] spc6_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc6_ncu_core_running_status";
input [7:0] spc7_ncu_core_running_status INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc7_ncu_core_running_status";
// end of interface ncu_cov
//interface ncu_cov_bank
input ncu_spc_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_pm";
input ncu_spc_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba01";
input ncu_spc_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba23";
input ncu_spc_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba45";
input ncu_spc_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_ba67";
input ncu_spc_l2_idx_hash_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc_l2_idx_hash_en";
input ncu_sii_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_pm";
input ncu_sii_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba01";
input ncu_sii_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba23";
input ncu_sii_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba45";
input ncu_sii_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_ba67";
input ncu_sii_l2_idx_hash_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_l2_idx_hash_en";
input ncu_l2t_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_pm";
input ncu_l2t_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba01";
input ncu_l2t_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba23";
input ncu_l2t_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba45";
input ncu_l2t_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_l2t_ba67";
input ncu_mcu_pm INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_pm";
input ncu_mcu_ba01 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba01";
input ncu_mcu_ba23 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba23";
input ncu_mcu_ba45 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba45";
input ncu_mcu_ba67 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu_ba67";
input ssi_int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.ssi_int_vld";
input niu_int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.niu_int_vld";
input spc_int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.ncu_man_int_vld";
input sii_mondo_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.sii_mondo_vld";
}
/*
//interface ncu_cov_l2t {
input [41:0] l2t0_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t0_dbgbus_out";
input [41:0] l2t1_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t1_dbgbus_out";
input [41:0] l2t2_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t2_dbgbus_out";
input [41:0] l2t3_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t3_dbgbus_out";
input [41:0] l2t4_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t4_dbgbus_out";
input [41:0] l2t5_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t5_dbgbus_out";
input [41:0] l2t6_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t6_dbgbus_out";
input [41:0] l2t7_dbgbus_out INPUT_EDGE INPUT_SKEW verilog_node "`NCU.l2t7_dbgbus_out";
} // end of interface ncu_cov
*/
interface ncu_rtl_io_cov {
input clk CLOCK verilog_node "`NCU.iol2clk";
input [6:0] intman_tbl_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_raddr";
input [6:0] intman_tbl_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_waddr";
input intman_tbl_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_wr";
input intman_tbl_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intman_tbl_rden";
input [5:0] io_buf_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_tail_ptr";
input io_buf_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_wr";
input [6:0] io_intman_addr INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSD.io_intman_addr";
input int_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CSC.int_vld";
input [4:0] cpu_buf_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_head_ptr";
input cpu_buf_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_rden";
input cpu_buf_rd_sel INPUT_EDGE INPUT_SKEW verilog_node "`NCU_C2ISC.head_inc";
}
interface ncu_rtl_ccx_cov {
input clk CLOCK verilog_node "`NCU.gclk";
input [5:0] io_buf_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_head_ptr";
input io_buf_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.iobuf_rden";
input [5:0] mondo_data_tbl_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data_addr_p0";
input [5:0] mondo_data_tbl_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data_addr_p1";
input mondo_data0_tbl_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data0_wr";
input mondo_data1_tbl_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mondo_data1_wr";
input mondo_data_tbl_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU_C2IFC.cpu_mondo_acc";
input [4:0] cpu_buf_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_tail_ptr";
input cpu_buf_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.cpubuf_wr";
input [4:0] int_buf_raddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_head_ptr";
input [4:0] int_buf_waddr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_tail_ptr";
input int_buf_wr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_wr";
//input int_buf_rd INPUT_EDGE INPUT_SKEW verilog_node "`NCU.intbuf_rd_en";
input int_buf_rd_sel INPUT_EDGE INPUT_SKEW verilog_node "`NCU_I2CFC.intbuf_head_inc";
}
interface ncu_ras_cov {
input clk CLOCK verilog_node "`NCU.iol2clk";
input ncu_rst_fatal_error INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_rst_fatal_error";
input [3:0] siisyn INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_siisyn[63], `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_siisyn[58:56]}";
input [10:0] ncusyn INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncusyn[63:58], `NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncusyn[55:51]}";
input [42:0] ncu_ras_esr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasesr";
input [42:0] ncu_ras_ele INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasele";
input [42:0] ncu_ras_eie INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.raseie";
input [42:0] ncu_ras_fee INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasfee";
input [5:0] ncu_ras_steering INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.ras_err_steering";
input [42:0] raserr_in INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.raserr_in";
input siisyn_v INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.siisyn_v";
input rasesr_v INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasesr_v";
input rasper_v INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasper_v";
input c2i_packet_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.c2i_packet_vld";
input dmu_ncu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ctag_ue";
input dmu_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ctag_ce";
input dmu_ncu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_d_pe";
input dmu_ncu_siicr_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_siicr_pe";
input dmu_ncu_ncucr_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ncucr_pe";
input dmu_ncu_ie INPUT_EDGE INPUT_SKEW verilog_node "`NCU.dmu_ncu_ie";
input niu_ncu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_ctag_ue";
input niu_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_ctag_ce";
input niu_ncu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.niu_ncu_d_pe";
input sii_ncu_niua_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niua_pe";
input sii_ncu_niuctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niuctag_ue";
input sii_ncu_niuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niuctag_ce";
input sii_ncu_niud_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_niud_pe";
input sii_ncu_dmua_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmua_pe";
input sii_ncu_dmuctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmuctag_ue";
input sii_ncu_dmuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmuctag_ce";
input sii_ncu_dmud_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sii_ncu_dmud_pe";
input sio_ncu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sio_ncu_ctag_ue";
input sio_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sio_ncu_ctag_ce";
// input sio_ncu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`NCU.sio_ncu_d_pe";
.for($b=0; $b<4; $b++){
input mcu${b}_ncu_ecc INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_ecc";
input mcu${b}_ncu_fbr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.mcu${b}_ncu_fbr";
.}
input ncu_dmu_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_ctag_uei";
input ncu_dmu_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_ctag_cei";
input ncu_dmu_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_d_pei";
input ncu_dmu_siicr_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_siicr_pei";
input ncu_dmu_ncucr_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_ncucr_pei";
input ncu_dmu_iei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_dmu_iei";
input ncu_niu_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_ctag_uei";
input ncu_niu_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_ctag_cei";
input ncu_niu_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_niu_d_pei";
input ncu_sii_niua_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niua_pei";
input ncu_sii_niuctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niuctag_uei";
input ncu_sii_niuctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niuctag_cei";
input ncu_sii_niud_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_niud_pei";
input ncu_sii_dmua_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmua_pei";
input ncu_sii_dmuctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmuctag_uei";
input ncu_sii_dmuctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmuctag_cei";
input ncu_sii_dmud_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sii_dmud_pei";
input ncu_sio_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sio_ctag_uei";
input ncu_sio_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sio_ctag_cei";
input ncu_sio_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_sio_d_pei";
.for($b=0; $b<4; $b++){
input ncu_mcu${b}_ecci INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_ecci";
input ncu_mcu${b}_fbri INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_mcu${b}_fbri";
.}
input pio_hdr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.pio_hdr_vld";
input mondo_hdr_vld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.mondo_hdr_vld";
input ncuctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.hdrctag_ce";
input ncuctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.hdrctag_ue";
input dperr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.dperr";
input pldvld INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_i2cscd_ctl.sii_ucb_buf.pldvld[0]";
input c2i_rd_intman INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.c2i_rd_intman";
input io_rd_intman_d2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.io_rd_intman_d2";
input intman_pe_n INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.intman_pe_n";
}
// ******************************************************************
// Interface for FC coverage Objects
// ******************************************************************
interface cpx_to_ncu_fifo_cpu_buf {
input wrclk CLOCK verilog_node "`NCU.ncu_cpu_buf_rf_cust.wrclk";
input rdclk INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.rdclk";
input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.wr_en";
input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.rd_en";
input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.wr_adr";
input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_cpu_buf_rf_cust.rd_adr";
}
interface ncu_to_cpx_fifo_iobuf {
input rdclk CLOCK verilog_node "`NCU.ncu_iobuf0_rf_cust.rdclk";
input wrclk INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.wrclk";
input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.wr_en";
input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.rd_en";
input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.wr_adr";
input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_iobuf0_rf_cust.rd_adr";
}
interface ncu_to_cpx_fifo_intbuf {
input rdclk CLOCK verilog_node "`NCU.ncu_intbuf_rf_cust.rdclk";
input wrclk INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.wrclk";
input wr_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.wr_en";
input rd_en INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.rd_en";
input [4:0] wr_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.wr_adr";
input [4:0] rd_adr INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_intbuf_rf_cust.rd_adr";
}
// ******************************************************************
#endif
Full OpenSPARC design & verification tarball including full HDL.