verif/env/common/vera/ccxDevices/ccxDevicesDefines.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ccxDevicesDefines.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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// it under the terms of the GNU General Public License as published by
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// This program is distributed in the hope that it will be useful,
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// ========== Copyright Header End ============================================
#ifndef INC__TMP_CCXDEVICEDEFINES_VRI
#define INC__TMP_CCXDEVICEDEFINES_VRI


#define STD_DISP gDbg

//----------------------------------------------------------
// PCX Packet rqtyp Defines, actual - request
#define PCX_LD        5'b00000
#define PCX_PREF      5'b00000
#define PCX_PREF_ICE  5'b00000
#define PCX_DIAG_LD   5'b00000
#define PCX_D_INVAL   5'b00000
#define PCX_IFILL     5'b10000
#define PCX_I_INVAL   5'b10000
#define PCX_ST        5'b00001
#define PCX_BLK_ST    5'b00001
#define PCX_BLK_INIT_ST 5'b00001
#define PCX_DIAG_ST   5'b00001
#define PCX_CAS1      5'b00010
#define PCX_CAS2      5'b00011
#define PCX_SWAP      5'b00111
#define PCX_STR_LD    5'b00100
#define PCX_STR_ST    5'b00101
#define PCX_MMU_LD    5'b01000

#define PCX_FLUSH     5'b01001


// PCX Packet rqtyp Defines, unique
#define U_PCX_LD        1
#define U_PCX_PREF      2
#define U_PCX_DIAG_LD   3
#define U_PCX_D_INVAL   4
#define U_PCX_IFILL     5
#define U_PCX_I_INVAL   6
#define U_PCX_ST        7
#define U_PCX_BLK_ST    8
#define U_PCX_DIAG_ST   9
#define U_PCX_CAS1      10
#define U_PCX_CAS2      11
#define U_PCX_SWAP      12
#define U_PCX_STR_LD    13
#define U_PCX_STR_ST    14
#define U_PCX_MMU_LD    15
#define U_PCX_PREF_ICE  16
#define U_PCX_BLK_INIT_ST 17

// CPX Packet rtntyp Defines, actual - return
#define CPX_LD       4'b0000
#define CPX_PREF     4'b0000
#define CPX_PREF_ICE 4'b0000
#define CPX_DIAG_LD  4'b0000
#define CPX_NCU_LD   4'b1000
#define CPX_D_INVAL  4'b0100
#define CPX_IFILL    4'b0001
#define CPX_NCU_IFILL 4'b1001
#define CPX_I_INVAL  4'b0100
#define CPX_ST       4'b0100
#define CPX_DIAG_ST  4'b0100
#define CPX_CAS_RTN  4'b0000
#define CPX_CAS_ACK  4'b0100
#define CPX_SWAP_RTN 4'b0000
#define CPX_SWAP_ACK 4'b0100
#define CPX_STR_LD   4'b0010
#define CPX_STR_ST   4'b0110
#define CPX_MMU_RTN  4'b0101
#define CPX_INTR     4'b0111
#define CPX_EVICT    4'b0011
#define CPX_ERROR_L2 4'b1100
#define CPX_ERROR_SOC 4'b1101

#define CPX_BLK_ST   4'b0100
#define CPX_FLUSH    4'b0111

// CPX Packet rtntyp Defines, unique
#define U_CPX_LD       1
#define U_CPX_PREF     2
#define U_CPX_DIAG_LD  3
#define U_CPX_D_INVAL  4
#define U_CPX_IFILL    5
#define U_CPX_I_INVAL  6
#define U_CPX_ST       7
#define U_CPX_DIAG_ST  8
#define U_CPX_CAS_RTN  9
#define U_CPX_CAS_ACK  10
#define U_CPX_SWAP_RTN 11
#define U_CPX_SWAP_ACK 12
#define U_CPX_STR_LD   13
#define U_CPX_STR_ST   14
#define U_CPX_MMU_RTN  15
#define U_CPX_INTR     16
#define U_CPX_EVICT    17
#define U_CPX_ERROR_L2 18
#define U_CPX_BIS      19
#define U_CPX_NCU_LD   20
#define U_CPX_ERROR_SOC 21
#define U_CPX_NCU_IFILL 22
#define U_CPX_PREF_ICE  23
#define U_CPX_BLK_ST    24

// Interrupt types
#define INTR_HW        2'b00
#define INTR_RESET     2'b01
#define INTR_IDLE      2'b10
#define INTR_RESUME    2'b11

// Interrupt vectors
#define INTR_POR       6'b000001
#define INTR_XIR       6'b000011


// I/O Addresses
// CMP ASI Registers

// #define IO_ASI_ADDR                                   8'h90
// #define ASI_CMP_CORE                                  8'h41
// #define ASI_CMP_CORE_AVAIL                            18'h000
// #define ASI_CMP_CORE_ENABLED                          18'h010
// #define ASI_CMP_CORE_ENABLE                           18'h020
// #define ASI_CMP_XIR_STEERING                          18'h030
// #define ASI_CMP_ERROR_STEERING                        18'h040
// #define ASI_CMP_CORE_RUNNING_RW                       18'h050
// #define ASI_CMP_CORE_RUNNING_STATUS                   18'h058
// #define ASI_CMP_CORE_RUNNING_W1S                      18'h060
// #define ASI_CMP_CORE_RUNNING_W1C                      18'h068


// Tag Table defines
#define DATA_TAG       1
#define INSTR_TAG      0
#define TAG_VAL        1'b1
#define TAG_INVAL      1'b0
#define EVICT_D        2'b00
#define EVICT_I        2'b01
#define EVICT_DI       2'b10
#define EVICT_ID       2'b11
#define D_INVAL        2'b01
#define I_INVAL        2'b10


#define PP_CPX 0
#define PP_PCX 1
#define PP_MEM 2
#define PP_SPC 3
#define PP_TRG 4

#define READ 0
#define WRITE 1

#define PASSIVE 1
#define ACTIVE  0

// ccx devices
#define DEV_SPC0 0
#define DEV_SPC1 1
#define DEV_SPC2 2
#define DEV_SPC3 3
#define DEV_SPC4 4
#define DEV_SPC5 5
#define DEV_SPC6 6
#define DEV_SPC7 7
#define DEV_MEM0 8
#define DEV_MEM1 9
#define DEV_MEM2 10
#define DEV_MEM3 11
#define DEV_MEM4 12
#define DEV_MEM5 13
#define DEV_MEM6 14
#define DEV_MEM7 15

#define DEV_MEM8 16
#define DEV_NCU  16


// "same cache line address".
#define CACHE_LINE_MASK 64'h0000007fffffffc0


//#define IDLE_DATA {urandom(),urandom(),urandom(),urandom()}
#define IDLE_DATA 128'hDEAD_BEEF_DEAD_BEEF_DEAD_BEEF_DEAD_BEEF


#endif

//----------------------------------------------------------
//  END OF FILE
//----------------------------------------------------------