// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: cmp.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
//----------------------------------------------------------
// addr[39:0] = {8'h90, cpuid[2:0], tid[2:0], 8'h45, va[17:0]};
// addr[31:26] = {cpuid[2:0], tid[2:0]}
// addr[25:18] = ASI_SWVR_UDB_INTR_W
`define IO_ASI_ADDR 8'h90
`define IO_ASI_ADDR_NCU 39:32
`define IO_ASI_ADDR_CT 31:26
`define IO_ASI_ADDR_REG 25:18
`define IO_ASI_ADDR_VA 17:0
`define IO_ASI_ADDR_ADR 25:0
// {IO_ASI_CPU[39:32],IO_ASI_ADDR_CT[31:26],IO_ASI_ADDR_REG[25:18],IO_ASI_ADDR_VA[17:0]};
`define ASI_CMP_CORE 8'h41
`define ASI_CMP_CORE_AVAIL 18'h000
`define ASI_CMP_CORE_ENABLED 18'h010
`define ASI_CMP_CORE_ENABLE 18'h020
`define ASI_CMP_XIR_STEERING 18'h030
`define ASI_CMP_TICK_ENABLE 18'h038
`define ASI_CMP_ERROR_STEERING 18'h040
`define ASI_CMP_CORE_RUNNING_RW 18'h050
`define ASI_CMP_CORE_RUNNING_STATUS 18'h058
`define ASI_CMP_CORE_RUNNING_W1S 18'h060
`define ASI_CMP_CORE_RUNNING_W1C 18'h068
`define ASI_CMP_CORE_AVAIL_ADR {8'h41,18'h000}
`define ASI_CMP_CORE_ENABLED_ADR {8'h41,18'h010}
`define ASI_CMP_CORE_ENABLE_ADR {8'h41,18'h020}
`define ASI_CMP_XIR_STEERING_ADR {8'h41,18'h030}
`define ASI_CMP_TICK_ENABLE_ADR {8'h41,18'h038}
`define ASI_CMP_ERROR_STEERING_ADR {8'h41,18'h040}
`define ASI_CMP_CORE_RUNNING_RW_ADR {8'h41,18'h050}
`define ASI_CMP_CORE_RUNNING_STATUS_ADR {8'h41,18'h058}
`define ASI_CMP_CORE_RUNNING_W1S_ADR {8'h41,18'h060}
`define ASI_CMP_CORE_RUNNING_W1C_ADR {8'h41,18'h068}
`define ASI_SWVR_UDB_INTR_W 8'h73
// power throttle, [2:0] is encoded number of stalls in 8 cycle window
// 000 - no stalls, 001 - 1 stall, ... 111 - 7 stalls
// this is a reserved address!
// Chip CPU Throttle Control CPU_THROTTLE_CTL (0x98-0000-0828)
`define ASI_POWER_THROTTLE_ADR {8'h00,18'h828}
`define ASI_LSU_MISC 8'h45
`define ASI_WMR_VEC_MASK_ADR {8'h45,18'h18}
`define ASI_OVERLAP_MODE_ADR {8'h45,18'h10}
`define ASI_L2_IDX_HASH_EN_ADR {8'h45,18'h1030}
`define ASI_RESET_STAT 64'h8900000810
`define TID_ADDR 40'h9a00000000
`define INT_VEC_DIS_ADDR 40'h9001cc0000
//----------------------------------------------------------
//----------------------------------------------------------
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