verif/env/common/verilog/monitors/iommu_demap.v

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// OpenSPARC T2 Processor File: iommu_demap.v
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`include "defines.vh"
`include "dispmonDefines.vh"

module iommu_demap ();


        wire            clk = `CPU.dmu.dmc.mmu.clk;
        wire [63:0]     nxt_vld;
        wire [63:0]     ptb2vtb_inv;
        wire            csr2ptb_inv;
        integer         i;

        reg             csr2ptb_inv_local;
        reg             enable;


        assign          csr2ptb_inv = `CPU.dmu.dmc.mmu.csr.csr2ptb_inv ;
        assign          nxt_vld = `CPU.dmu.dmc.mmu.vtb.nxt_vld ;
        assign          ptb2vtb_inv = `CPU.dmu.dmc.mmu.vtb.ptb2vtb_inv ;

initial
begin
        enable = 0;
        i = 0;
        if ($test$plusargs("turn_on_iommu_demap")) enable = 1;
end


        always @ (posedge clk)
                begin
                        csr2ptb_inv_local <= #1 csr2ptb_inv;
                        if(csr2ptb_inv_local == 1 )
                                begin
                                for(i=0;i<63;i=i+1)
                                        begin
                                        if(ptb2vtb_inv[i] == 1) begin
                                                 if ((nxt_vld[i] == 0) && (enable ==1))
                                                 begin
                                                        $dispmon("IOMMU_DEMAP", `ALWAYS, "invalidating %d entry",i);
                                                 end
                                                 else if (nxt_vld[i] == 1) begin
                                                        $dispmon("IOMMU_DEMAP", `ERROR, "valid bit in not zero for %d entry",i);
                                                end
                                                end
                                        end
                                end

                end

endmodule