// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: tlb_fifo.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC0.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC0.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC0.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC0.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC0.pku.pku_flush_buffer0[mytid];
assign pop = `SPC0.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES0.itlb_miss[mytid];
assign icache_miss = `PROBES0.icache_miss[mytid];
assign fetch_bypass = `PROBES0.fetch_bypass[mytid];
assign exc_valid = `SPC0.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC0.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC1.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC1.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC1.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC1.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC1.pku.pku_flush_buffer0[mytid];
assign pop = `SPC1.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES1.itlb_miss[mytid];
assign icache_miss = `PROBES1.icache_miss[mytid];
assign fetch_bypass = `PROBES1.fetch_bypass[mytid];
assign exc_valid = `SPC1.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC1.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC2.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC2.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC2.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC2.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC2.pku.pku_flush_buffer0[mytid];
assign pop = `SPC2.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES2.itlb_miss[mytid];
assign icache_miss = `PROBES2.icache_miss[mytid];
assign fetch_bypass = `PROBES2.fetch_bypass[mytid];
assign exc_valid = `SPC2.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC2.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC3.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC3.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC3.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC3.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC3.pku.pku_flush_buffer0[mytid];
assign pop = `SPC3.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES3.itlb_miss[mytid];
assign icache_miss = `PROBES3.icache_miss[mytid];
assign fetch_bypass = `PROBES3.fetch_bypass[mytid];
assign exc_valid = `SPC3.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC3.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC4.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC4.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC4.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC4.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC4.pku.pku_flush_buffer0[mytid];
assign pop = `SPC4.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES4.itlb_miss[mytid];
assign icache_miss = `PROBES4.icache_miss[mytid];
assign fetch_bypass = `PROBES4.fetch_bypass[mytid];
assign exc_valid = `SPC4.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC4.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC5.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC5.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC5.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC5.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC5.pku.pku_flush_buffer0[mytid];
assign pop = `SPC5.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES5.itlb_miss[mytid];
assign icache_miss = `PROBES5.icache_miss[mytid];
assign fetch_bypass = `PROBES5.fetch_bypass[mytid];
assign exc_valid = `SPC5.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC5.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC6.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC6.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC6.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC6.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC6.pku.pku_flush_buffer0[mytid];
assign pop = `SPC6.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES6.itlb_miss[mytid];
assign icache_miss = `PROBES6.icache_miss[mytid];
assign fetch_bypass = `PROBES6.fetch_bypass[mytid];
assign exc_valid = `SPC6.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC6.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
// FIFO_DEPTH is 1 more than IB depth in RTL
// so that overflow can be detected properly.
parameter FIFO_DEPTH = 9;
output [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
wire push1; // 1st signal to qualify push_select
wire push2; // 2nd signal to qualify push_select
wire [3:0] push_select; // 1-4 tstamps are pushed
wire exc_valid; // Exception valid
wire [3:0] ifu_err_select;
wire [3:0] ifetch_err_vld;
reg [(`TS_WIDTH-1):0] tstamp_curr;
reg [(`TS_WIDTH-1):0] tstamp_prev;
reg [(`TLB_FIFO_WIDTH-1):0] fifo [0:(FIFO_DEPTH-1)]; // reg array
reg [(PTR_WIDTH-1):0] pop_ptr;
reg [(PTR_WIDTH-1):0] push_ptr;
reg [(`TLB_FIFO_WIDTH-1):0] itlb_pipe_d;
//----------------------------------------------------------
// Create wires for reg array so signals can be viewed in Debussy
wire [(`TLB_FIFO_WIDTH-1):0] fifo_0;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_1;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_2;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_3;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_4;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_5;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_6;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_7;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_8;
wire [(`TLB_FIFO_WIDTH-1):0] fifo_9;
//----------------------------------------------------------
assign push1 = `SPC7.ifu_ftu.ftu_fetch_thr_c[mytid];
assign push2 = `SPC7.ifu_ftu.ftu_ibu_redirect_bf[mytid];
assign push_select = `SPC7.ifu_ftu.ftu_instr_valid_c;
assign flush_upper = `SPC7.pku.pku_flush_upper_buffer[mytid];
assign flush_head = `SPC7.pku.pku_flush_buffer0[mytid];
assign pop = `SPC7.pku.pku_pick_p[mytid];
assign itlb_miss = `PROBES7.itlb_miss[mytid];
assign icache_miss = `PROBES7.icache_miss[mytid];
assign fetch_bypass = `PROBES7.fetch_bypass[mytid];
assign exc_valid = `SPC7.ifu_ftu.ftu_exception_valid_c;
// Error Injection - tlb_sync is pipelining some information that is useful to error injection code.
assign ifu_err_vect = {tb_top.ras.ifu_err.ifu_err_code_c[4:0],tb_top.ras.ifu_err.ifu_err_way[2:0]};
assign ifu_err_select = tb_top.ras.ifu_err.ifu_err_select[3:0];
assign ifetch_err_vld = tb_top.ras.ifu_err.ifetch_err_vld[3:0];
assign ifu_err_vect = 8'b0;
assign ifu_err_select = 4'b0;
assign ifetch_err_vld = 4'b0;
//----------------------------------------------------------
ready = `PARGS.tlb_sync_on;
//----------------------------------------------------------
always @ (posedge (`SPC7.l2clk & ready)) begin // {
// Save tstamp if L1 Icache miss & ITLB hit (for later use if bypass)
if (icache_miss & !itlb_miss) begin // {
tstamp_prev = `TOP.core_cycle_cnt - 2;
// if POR|WMR, then no TLBread
if (`TOP.in_reset_core) begin // {
itlb_pipe_d <= pop ? fifo[pop_ptr] : itlb_pipe_d; // Get new value or hold state
//------------------------
// Pop FIFO - special case
// This code must be above the Push FIFO code.
// to handle the case if (flush_head and push and IB was empty)
// Only flush_head if fifo is not empty
// Don't need to qualify with flush_upper because the buffer will
// be cleared by code below.
if (flush_head && (pop_ptr != push_ptr)) begin // {
//------------------------
// push_select may be asserted at same time as exc_valid.
// exc_valid should override.
// If exc_valid, I must push 2 valid tstamp in IB before making IB full.
// this is because the exception instruction will get to W and will
// need a ITLB_READ tstamp.
// exc_valid will only be asserted if there is room in IB for 4 entries
// so it is safe to push 2 entries.
// It is required to push 2 because the 1st entry may be DS of annul branch,
// then the exception happens on next instruction after DS.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
// It is possible to get back-to-back exceptions.
// So, need to check for fifo full before fifo_push.
// It is possible to have only 1 entry available after the 1 exception.
// if there was a pop at the same time as the exception.
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
ib_full = (pop_ptr==0) ? (push_ptr==(FIFO_DEPTH-1)): (push_ptr==(pop_ptr-1));
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[0] && push1 && !push2) begin // {
fifo_push(ifu_err_select[0], ifetch_err_vld[0]);
if (push_select[1] && push1 && !push2) begin // {
fifo_push(ifu_err_select[1], ifetch_err_vld[1]);
if (push_select[2] && push1 && !push2) begin // {
fifo_push(ifu_err_select[2], ifetch_err_vld[2]);
if (push_select[3] && push1 && !push2) begin // {
fifo_push(ifu_err_select[3], ifetch_err_vld[3]);
//------------------------
// It is possible to push and flush_upper in the same cycle.
// If this happens, flush_upper takes priority.
// So, flush code must be after push code since same always block.
// If flush_head and push in same cycle, there will be 1 entry in IB.
// Essentially, flush_head is ignored, then an entry is pushed.
case ({flush_upper, flush_head, pop}) // {
// NOP - case handled in code above
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// Only flush_upper if fifo is not empty
if (pop_ptr != push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d Illegal signal combination for IB. flush_upper=%0b flush_head=%0b pick=%0b",
mycid,mytid,flush_upper,flush_head,pop);
// It is possible to get a pop and exception.
// In this case, the pop will happen, then the IB is made full.
if (exc_valid && push1 && !push2 && !flush_upper) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
for (i=0; i<FIFO_DEPTH; i=i+1) begin // {
//----------------------------------------------------------
// Empty FIFO and reset push/pop pointers
// Increment push_ptr to full buffere
if (pop_ptr == 0) begin // {
//----------------------------------------------------------
// Make sure the FIFO is not empty before pop
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Underflow. PKU is trying to pick from empty IB.", mycid,mytid);
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
// Flush all items from FIFO except head
// Make sure the FIFO is not empty
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IFU is trying to flush upper, but IB is empty.", mycid,mytid);
// Make push ptr 1 entry above pop ptr
if (pop_ptr==(FIFO_DEPTH-1)) begin // {
//----------------------------------------------------------
tstamp_curr = `TOP.core_cycle_cnt - 2;
tmp_err_vect = err_select ? ifu_err_vect : 8'b0;
fifo[push_ptr] <= fetch_bypass ? {cache_err_vld,tmp_err_vect,tstamp_prev} : {cache_err_vld,tmp_err_vect,tstamp_curr};
fifo[push_ptr] <= fetch_bypass ? tstamp_prev : tstamp_curr;
// Increment push pointer
if (push_ptr==(FIFO_DEPTH-1)) begin // {
// Check for Overflow after push
if (pop_ptr == push_ptr) begin // {
`PR_ERROR ("tlb_sync", `ERROR,
"C%0d T%0d IB Overflow. IFU is trying to fetch another instruction, but IB is already full.", mycid,mytid);
//----------------------------------------------------------
//----------------------------------------------------------
//----------------------------------------------------------
projects / OpenSPARC-T2-DV / blob