verif/env/config/fc_scan_common.config

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fc_scan_common.config
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#ifdef GATESIM_ALL
        -nosunv_run
        -nozeroIn_build

#include "fc_gate_all.config"
//      #define USE_FULL_FLOP USE_FULL_FLOP

        -vcs_build_args=+define+PEU_DMU_GATESIM
        -vcs_build_args=+define+CCU_GATESIM
#endif

#if (defined CORES1)
    -config_rtl=CORE_0
    -sunv_args=-define=RTL_NO_SPC1
    -sunv_args=-define=RTL_NO_SPC2
    -sunv_args=-define=RTL_NO_SPC3
    -sunv_args=-define=RTL_NO_SPC4
    -sunv_args=-define=RTL_NO_SPC5
    -sunv_args=-define=RTL_NO_SPC6
    -sunv_args=-define=RTL_NO_SPC7
    -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC1 -DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
    -vera_diag_args="-DRTL_NO_SPC1 -DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
#endif
#if (defined CORES2)
   -config_rtl=CORE_0
   -config_rtl=CORE_1
    -sunv_args=-define=RTL_NO_SPC2
    -sunv_args=-define=RTL_NO_SPC3
    -sunv_args=-define=RTL_NO_SPC4
    -sunv_args=-define=RTL_NO_SPC5
    -sunv_args=-define=RTL_NO_SPC6
    -sunv_args=-define=RTL_NO_SPC7
    -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
    -vera_diag_args="-DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
#endif
#if (defined CORES4)
   -config_rtl=CORE_0
   -config_rtl=CORE_1
   -config_rtl=CORE_2
   -config_rtl=CORE_3
    -sunv_args=-define=RTL_NO_SPC4
    -sunv_args=-define=RTL_NO_SPC5
    -sunv_args=-define=RTL_NO_SPC6
    -sunv_args=-define=RTL_NO_SPC7
    -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
    -vera_diag_args="-DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
#endif
#if (!defined CORES1 && !defined CORES2 && !defined CORES4)
   -config_rtl=CORE_0
   -config_rtl=CORE_1
   -config_rtl=CORE_2
   -config_rtl=CORE_3
   -config_rtl=CORE_4
   -config_rtl=CORE_5
   -config_rtl=CORE_6
   -config_rtl=CORE_7
#endif

   -flist=$DV_ROOT/verif/env/fc_scan/fc_scan_common.flist
   -post_process_cmd="regreport -1 | tee status.log"

#ifdef FULL_GATE
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist
        -flist=$DV_ROOT/verif/env/fc/fc_rptr.flist
#endif

// entire model is gates (model is all gates)
#if (defined USE_GATESIM)
         -config_rtl=GATESIM
         -vera_build_args=GATESIM=GATESIM
         // whatever...
#else
         // whatever...
        // sunv stuff
#endif

#if (defined USE_DMU_GATES)
    -config_rtl=DMU_GATES
    -config_rtl=ASIC_GATES
    -vera_build_args=DMU_GATES=DMU_GATES
    -vera_diag_args="-DDMU_GATES"
    -vera_build_args=ASIC_GATES=ASIC_GATES
#endif
#if (defined USE_PEU_GATES)
    -config_rtl=PEU_GATES
    -config_rtl=ASIC_GATES
    -vera_build_args=PEU_GATES=PEU_GATES
    -vera_diag_args="-DPEU_GATES"
    -vera_build_args=ASIC_GATES=ASIC_GATES
#endif
#if (defined USE_NIU_GATES)
    -config_rtl=NIU_GATES
    -config_rtl=ASIC_GATES
    -vera_build_args=NIU_GATES=NIU_GATES
    -vera_diag_args="-DNIU_GATES"
    -vera_build_args=ASIC_GATES=ASIC_GATES
#endif
#if (defined USE_CCU_GATES)
    -config_rtl=CCU_GATES
    -config_rtl=ASIC_GATES
    -vera_build_args=CCU_GATES=CCU_GATES
    -vera_diag_args="-DCCU_GATES"
    -vera_build_args=ASIC_GATES=ASIC_GATES
#endif

   -asm_diag_root=$DV_ROOT/verif/diag
   -config_rtl=FC_SCAN_BENCH
   -config_rtl=FC_BENCH
   -config_rtl=RTL_SPARC0
   -drm_disk=[/export/home/bw=30]
   -drm_freeprocessor=1.0
   -drm_freeram=3000
   -drm_freeswap=1800
   -drm_type=vcs
   -env_base=$DV_ROOT/verif/env/fc_scan
   -hcs_build_args=-comp_options "+hcs+v2k"
   -hcs_drm_tokens=12

   -fsdbfile=fc_scan_top.fsdb
   -image_diag_root=$DV_ROOT/verif
   -pal_use_tgseed
   // review
   -max_cycle=400000000
   // review
   -rtl_timeout=25000

#if (defined FC_RAW)
   -flist=$DV_ROOT/verif/env/fc_scan/fc_raw.flist
#endif

   -sunv_args=-define=SCAN_MODE
   -sunv_args=-define=LIB
   -sunv_args=-define=SIM
   -sunv_args=-define=VCS
   -sunv_args=-excludepreload
   -sunv_args=-ignorepartial
   -sunv_args=-out=cpu.v
   -sunv_args=-path=SUNV_RTL_PATH
   -sunv_args=-perlinclude=SUNV_PATH/include
   -sunv_args=-preload=SUNVLIBS_SUNV
   -sunv_args=-showCompiledOutCode=off
   -sunv_args=-topcell=cpu
   -sunv_args=-unusednet='unused$:unused\[[0-9]+\]$'
   -sunv_args=-version
   -sunv_args=-warn=2000
   -sunv_args=-excludecell=\^ccu\$
   -sunv_args=-excludecell=\^n2_rng_cust\$
   -sunv_use_nonprim

   // KDW 8-18-05 -vcs_build_args=+define+FSR_NOATPG
   -vcs_build_args=+define+SCAN_MODE
   -vcs_build_args="-Xstrict=0x1 -syslib -lpthread"
   -vcs_build_args="-notice"
   -vcs_build_args=+define+LIB
   -vcs_build_args=+define+SIM
   -vcs_build_args=+define+TOP=tb_top
   -vcs_build_args=+define+X4+
   -vcs_build_args=+nospecify
   -vcs_build_args=+notimingcheck
   -vcs_build_args=+optconfigfile+$DV_ROOT/verif/env/fc_scan/exclude.v
#if (!defined GATESIM)
#if (!defined NO_RAD)
   -vcs_build_args=+rad
#endif
#endif
#ifdef PATCH_713R35
   -vcs_build_args=+optconfigfile+$DV_ROOT/verif/env/fc_scan/tresh
   -vcs_build_args=+rad
//   -vcs_build_args=+memopt
//   -vcs_build_args=-comp64
  -vcs_build_args=-Xman=4
#endif

   -vcs_build_args=+v2k
   -vcs_build_args=-Mupdate
   //-vcs_build_args=-lstdc++
   -vcs_build_args=SUNVLIBS_OTHER

   -vcs_run_args=+0in_checker_finish_delay+3000
   -vcs_run_args=+skt_timeout=50000
   -vcs_run_args=+vcs+flush+log


#if (!defined FC_RAW)
   -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab"
   -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a
   -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/socket/socket_pli.tab"
   -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/libsocket_pli.a

   // vera stuff
   -vcs_run_args=+vera_disable_final_report
   -vcs_run_args=+vera_exit_on_error
   -vcs_use_vera
   // never in common --> -vera_build_args=VERA_SYS_DEFS="-DFC_SCAN_BENCH -DNCURTL -DFC_BENCH"
   -vera_diag_args="-DFC_SCAN_BENCH -DFC_BENCH"
   -vera_config_root=$DV_ROOT/verif
   -vera_diag_root=$DV_ROOT/verif/diag
   -vera_vcon_file=fc_scan_top.vcon
   // vera stuff end
#endif

#ifdef NOSUNV
        -flist=$DV_ROOT/verif/env/fc/remaining.flist
#endif

#ifdef PEU_DMU_GATESIM
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.peu+dmu_gate
#endif
#ifdef CCU_GATESIM
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccu_gate
#endif

#ifdef SUNV_EXCLUDE_IO
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.io_gate
        -sunv_args=-excludecell=\^fsr
        -sunv_args=-excludecell=\^esr
        -sunv_args=-excludecell=\^psr
        -sunv_args=-excludecell=\^mio
        -sunv_args=-excludecell=\^mio
        -sunv_args=-excludecell=\^n2_pcm_main_blk
#endif

#ifdef SUNV_EXCLUDE_CLK_GL_CUST
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.clk_gl_cust_gate
        -sunv_args=-excludecell=\^n2_clk_gl_cust\$
        -sunv_args=-excludecell=\^n2_clk_gl_cmp_tree\$
        -sunv_args=-excludecell=\^n2_clk_gl_dr_tree\$
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_top\$
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_ccu_m0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_rst_m0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_tcu_m0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_17s1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_8s2
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_4s4
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_2
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_2
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_3
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_3
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_2
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_3
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_2
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_0
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_1
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_align
        -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_mcu_dr
#endif


#ifdef SUNV_EXCLUDE_CPU
         -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.cpu_gate
         -sunv_args=-excludecell=\^cpu
#endif

#ifdef SUNV_EXCLUDE_MCU
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.mcu_gate
        -sunv_args=-excludecell=\^mcu
#endif


#ifdef SUNV_EXCLUDE_NIU
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.niu_gate
        -sunv_args=-excludecell=\^niu
        -sunv_args=-excludecell=\^mac
        -sunv_args=-excludecell=\^rtx
        -sunv_args=-excludecell=\^rdp
        -sunv_args=-excludecell=\^tds
#endif
#ifdef SUNV_EXCLUDE_TCU
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.tcu_gate
        -sunv_args=-excludecell=\^tcu
#endif
#ifdef SUNV_EXCLUDE_RST
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.rst_gate
        -sunv_args=-excludecell=\^rst
#endif
#ifdef SUNV_EXCLUDE_EFU
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.efu_gate
        -sunv_args=-excludecell=\^efu
#endif
#ifdef SUNV_EXCLUDE_SII_SIO
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.sii+sio_gate
        -sunv_args=-excludecell=\^sii\$
        -sunv_args=-excludecell=\^sii_ilc_ctl\$
        -sunv_args=-excludecell=\^sii_ild_dp\$
        -sunv_args=-excludecell=\^sii_inc_ctl\$
        -sunv_args=-excludecell=\^sii_ipcc_ctl\$
        -sunv_args=-excludecell=\^sii_ipcc_dp\$
        -sunv_args=-excludecell=\^sii_ipcs_ctl\$
        -sunv_args=-excludecell=\^sii_mb0_ctl\$
        -sunv_args=-excludecell=\^sii_mb1_ctl\$
        -sunv_args=-excludecell=\^sii_stgsio_dp\$
        -sunv_args=-excludecell=\^sio\$
        -sunv_args=-excludecell=\^sio_mb0_ctl\$
        -sunv_args=-excludecell=\^sio_mb1_ctl\$
        -sunv_args=-excludecell=\^sio_mbist_ctl\$
        -sunv_args=-excludecell=\^sio_olc_ctl\$
        -sunv_args=-excludecell=\^sio_old_dp\$
        -sunv_args=-excludecell=\^sio_old_rf_cust\$
        -sunv_args=-excludecell=\^sio_opcc_ctl\$
        -sunv_args=-excludecell=\^sio_opcs_ctl\$
        -sunv_args=-excludecell=\^sio_opd_data_rf_cust\$
        -sunv_args=-excludecell=\^sio_opd_hdr_rf_cust\$
        -sunv_args=-excludecell=\^sio_opdc_dp\$
        -sunv_args=-excludecell=\^sio_opds_dp\$
        -sunv_args=-excludecell=\^sio_stg1_dp\$
        -sunv_args=-excludecell=\^sio_stg2_dp\$
#endif
#ifdef SUNV_EXCLUDE_SPC
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.spc_gate
        // exclude spc
        -sunv_args=-excludecell=\^spc\$
        -sunv_args=-excludecell=\^spc_msf0_dp\$
        -sunv_args=-excludecell=\^spc_msf1_dp\$
        -sunv_args=-excludecell=\^spc_lb_ctl\$
        -sunv_args=-excludecell=\^clkgen_spc_cmp\$
        -sunv_args=-excludecell=\^dmo_dp\$
        -sunv_args=-excludecell=\^gkt\$
        -sunv_args=-excludecell=\^fgu\$
        -sunv_args=-excludecell=\^ifu_ibu\$
        -sunv_args=-excludecell=\^ifu_ftu\$
        -sunv_args=-excludecell=\^ifu_cmu\$
        -sunv_args=-excludecell=\^dec\$
        -sunv_args=-excludecell=\^pku\$
        -sunv_args=-excludecell=\^exu\$
        -sunv_args=-excludecell=\^tlu\$
        -sunv_args=-excludecell=\^lsu\$
        -sunv_args=-excludecell=\^spu\$
        -sunv_args=-excludecell=\^mmu\$
        -sunv_args=-excludecell=\^pmu\$
        -sunv_args=-excludecell=\^spc_mb0_ctl\$
        -sunv_args=-excludecell=\^spc_mb1_ctl\$
        -sunv_args=-excludecell=\^spc_mb2_ctl\$
#endif
#ifdef SUNV_EXCLUDE_CCX
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccx_gate
        // exclude ccx
        -sunv_args=-excludecell=\^ccx\$
        -sunv_args=-excludecell=\^cpx\$
        -sunv_args=-excludecell=\^pcx\$
#endif
#ifdef SUNV_EXCLUDE_L2
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.l2_gate
        // exclude l2t
        -sunv_args=-excludecell=\^l2t\$
        -sunv_args=-excludecell=\^l2t_arb_ctl\$
        -sunv_args=-excludecell=\^l2t_arbadr_dp\$
        -sunv_args=-excludecell=\^l2t_arbdat_dp\$
        -sunv_args=-excludecell=\^l2t_arbdec_dp\$
        -sunv_args=-excludecell=\^l2t_csr_ctl\$
        -sunv_args=-excludecell=\^l2t_csreg_ctl\$
        -sunv_args=-excludecell=\^l2t_decc_dp\$
        -sunv_args=-excludecell=\^l2t_deccck_ctl\$
        -sunv_args=-excludecell=\^l2t_dir_ctl\$
        -sunv_args=-excludecell=\^l2t_dirbuf_ctl\$
        -sunv_args=-excludecell=\^l2t_dirin_dp\$
        -sunv_args=-excludecell=\^l2t_dirlbf_dp\$
        -sunv_args=-excludecell=\^l2t_dirout_dp\$
        -sunv_args=-excludecell=\^l2t_dirrep_ctl\$
        -sunv_args=-excludecell=\^l2t_dirtop_ctl\$
        -sunv_args=-excludecell=\^l2t_dirvec_ctl\$
        -sunv_args=-excludecell=\^l2t_dirvec_dp\$
        -sunv_args=-excludecell=\^l2t_dmo_dp\$
        -sunv_args=-excludecell=\^l2t_dmorpt_dp\$
        -sunv_args=-excludecell=\^l2t_ecc24b_dp\$
        -sunv_args=-excludecell=\^l2t_ecc30b_dp\$
        -sunv_args=-excludecell=\^l2t_ecc39_dp\$
        -sunv_args=-excludecell=\^l2t_ecc39a_dp\$
        -sunv_args=-excludecell=\^l2t_evctag_dp\$
        -sunv_args=-excludecell=\^l2t_ffrpt_dp\$
        -sunv_args=-excludecell=\^l2t_filbuf_ctl\$
        -sunv_args=-excludecell=\^l2t_iqu_ctl\$
        -sunv_args=-excludecell=\^l2t_ique_dp\$
        -sunv_args=-excludecell=\^l2t_l2brep_dp\$
        -sunv_args=-excludecell=\^l2t_l2drpt_dp\$
        -sunv_args=-excludecell=\^l2t_mb0_ctl\$
        -sunv_args=-excludecell=\^l2t_mb2_ctl\$
        -sunv_args=-excludecell=\^l2t_mbist_ctl\$
        -sunv_args=-excludecell=\^l2t_misbuf_ctl\$
        -sunv_args=-excludecell=\^l2t_mrep16x8_dp\$
        -sunv_args=-excludecell=\^l2t_mrep2x64_dp\$
        -sunv_args=-excludecell=\^l2t_mrep32x3_dp\$
        -sunv_args=-excludecell=\^l2t_mrep4x6_dp\$
        -sunv_args=-excludecell=\^l2t_mrep8x16_dp\$
        -sunv_args=-excludecell=\^l2t_oqu_ctl\$
        -sunv_args=-excludecell=\^l2t_oque_dp\$
        -sunv_args=-excludecell=\^l2t_pgen32b_dp\$
        -sunv_args=-excludecell=\^l2t_rdmarpt_dp\$
        -sunv_args=-excludecell=\^l2t_rdmat_ctl\$
        -sunv_args=-excludecell=\^l2t_rep_dp\$
        -sunv_args=-excludecell=\^l2t_ret_dp\$
        -sunv_args=-excludecell=\^l2t_shdwscn_dp\$
        -sunv_args=-excludecell=\^l2t_snp_ctl\$
        -sunv_args=-excludecell=\^l2t_snpd_dp\$
        -sunv_args=-excludecell=\^l2t_tag_ctl\$
        -sunv_args=-excludecell=\^l2t_tagd_dp\$
        -sunv_args=-excludecell=\^l2t_tagdp_ctl\$
        -sunv_args=-excludecell=\^l2t_taghdr_ctl\$
        -sunv_args=-excludecell=\^l2t_tagl_dp\$
        -sunv_args=-excludecell=\^l2t_usaloc_dp\$
        -sunv_args=-excludecell=\^l2t_vlddir_dp\$
        -sunv_args=-excludecell=\^l2t_vuad_ctl\$
        -sunv_args=-excludecell=\^l2t_vuad_dp\$
        -sunv_args=-excludecell=\^l2t_vuaddp_ctl\$
        -sunv_args=-excludecell=\^l2t_vuadio_dp\$
        -sunv_args=-excludecell=\^l2t_vuadpm_dp\$
        -sunv_args=-excludecell=\^l2t_wbuf_ctl\$
        -sunv_args=-excludecell=\^l2t_wbufrpt_dp\$
        // exclude l2b
        -sunv_args=-excludecell=\^l2b
#endif
#ifdef SUNV_EXCLUDE_DB
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.db_gate
        // exclude db0
        -sunv_args=-excludecell=\^db0\$
        -sunv_args=-excludecell=\^db0_red_dp\$
        -sunv_args=-excludecell=\^db0_reduct_ctl\$
        -sunv_args=-excludecell=\^db0_rtc_dp\$
        // exclude db1
        -sunv_args=-excludecell=\^db1\$
        -sunv_args=-excludecell=\^db1_csr_ctl\$
        -sunv_args=-excludecell=\^db1_dbgprt_dp\$
        -sunv_args=-excludecell=\^db1_ucbbusin4_ctl\$
        -sunv_args=-excludecell=\^db1_ucbbusout4_ctl\$
        -sunv_args=-excludecell=\^db1_ucbflow_ctl\$
#endif
#ifdef SUNV_EXCLUDE_NCU
        -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ncu_gate
        -sunv_args=-excludecell=\^ncu\$
        -sunv_args=-excludecell=\^ncu_c2ibuf32_ctl\$
        -sunv_args=-excludecell=\^ncu_c2ibuf4_ctl\$
        -sunv_args=-excludecell=\^ncu_c2ibufpio_ctl\$
        -sunv_args=-excludecell=\^ncu_c2ifc_ctl\$
        -sunv_args=-excludecell=\^ncu_c2ifcd_ctl\$
        -sunv_args=-excludecell=\^ncu_c2ifd_ctl\$
        -sunv_args=-excludecell=\^ncu_c2isc_ctl\$
        -sunv_args=-excludecell=\^ncu_c2iscd_ctl\$
        -sunv_args=-excludecell=\^ncu_c2isd_ctl\$
        -sunv_args=-excludecell=\^ncu_ctrl_ctl\$
        -sunv_args=-excludecell=\^ncu_eccchk11_ctl\$
        -sunv_args=-excludecell=\^ncu_eccchk16_ctl\$
        -sunv_args=-excludecell=\^ncu_eccchk6_ctl\$
        -sunv_args=-excludecell=\^ncu_eccgen11_ctl\$
        -sunv_args=-excludecell=\^ncu_eccgen6_ctl\$
        -sunv_args=-excludecell=\^ncu_fcd_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cbuf32_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cbuf32_ni_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cbuf4_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cbuf4_ni_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cbufsii_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cbuftcu_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cfc_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cfcd_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cfd_ctl\$
        -sunv_args=-excludecell=\^ncu_i2csc_ctl\$
        -sunv_args=-excludecell=\^ncu_i2cscd_ctl\$
        -sunv_args=-excludecell=\^ncu_i2csd_ctl\$
        -sunv_args=-excludecell=\^ncu_mb0_ctl\$
        -sunv_args=-excludecell=\^ncu_mb1_ctl\$
        -sunv_args=-excludecell=\^ncu_scd_ctl\$
        -sunv_args=-excludecell=\^ncu_ssiflow_ctl\$
        -sunv_args=-excludecell=\^ncu_ssisif_ctl\$
        -sunv_args=-excludecell=\^ncu_ssisrg64_ctl\$
        -sunv_args=-excludecell=\^ncu_ssisrg8_ctl\$
        -sunv_args=-excludecell=\^ncu_ssitop_ctl\$
        -sunv_args=-excludecell=\^ncu_ssiui4_ctl\$
        -sunv_args=-excludecell=\^ncu_ssiuif_ctl\$
        -sunv_args=-excludecell=\^ncu_ssiuo4_ctl\$
        -sunv_args=-excludecell=\^ncu_ucbbusin8_ctl\$
        //
#endif

   -vlint_args=+define+TOP=tb_top
   -vlint_args=-binary
   -vlint_args=-depth 999
   -vlint_args=-turn_unspecified_off
   -vlint_args=SUNVLIBS_OTHER
   -vlint_args=-vlint
   -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc
   -vlint_top=tb_top

   -vcs_cm_config=$DV_ROOT/verif/env/fc_scan/fc_scan.cm_config
   -wait_cycle_to_kill=15

   -zeroIn_build_args=+define+EMBED_SIMS_BUILD_ARGS
   -zeroIn_build_args=+define+FC_NO_PEUSAT_CODE
   -zeroIn_build_args=+define+CPU=tb_top.cpu
   -zeroIn_build_args=+define+ESR=tb_top.cpu.esr
   -zeroIn_build_args=+define+MAC=tb_top.cpu.mac
   -zeroIn_build_args=+define+RDP=tb_top.cpu.rdp
   -zeroIn_build_args=+define+RTX=tb_top.cpu.rtx
   -zeroIn_build_args=+define+TDS=tb_top.cpu.tds
   -zeroIn_build_args=+define+TOP=tb_top
   -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/0in_coverages.v
   -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/0in_checkers.v
   -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/fc_scan/fc_scan_zeroIn_cfg.v
   -zeroIn_build_args=-d cpu
   -zeroIn_build_args=+error+command-19
   -zeroIn_build_args=+error+command-46
   -zeroIn_build_args=+error+command-6
   -zeroIn_build_args=+error+command-7
   -zeroIn_build_args=-exit_on_directive_errors
   -zeroIn_build_args=-incr
#ifdef AXIS_BUILD
    -zeroIn_build_args=-sim axis
#else
    -zeroIn_build_args=-sim vcs
#ifndef NOFASTMOD
    -zeroIn_build_args=-fastmod
#endif
#ifndef ZEROINCOV
    -zeroIn_build_args="-fastsim turbo"
#else
      // This arg creates a 0in_coverage_bitmap.txt in the 0in build dir
      -zeroIn_dbg_args=+0in_debug+display_stats_in_binary+coverage_bit_map
#endif
#endif
    -zeroIn_build_args=SUNVLIBS_OTHER

   //-vcs_build_args=+applylearn+$DV_ROOT/verif/env/fc/pli_learn_all.tab
   //-zeroIn_build_args=-fastmod
   SUNVFORCEOPTS