verif/env/config/fgu.config

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fgu.config
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#define USEMOD USEFGU
#define DUT_MOD fgu
//#define USEMOD USECPU
//#define DUT_MOD cpu
// ------------------------------------------------------------------
// ------------------------------------------------------------------
// ------------------------------------------------------------------
// To remove vera:
//    Add the following two lines just after fgu tag
//    -novera_build
//    -novera_run
// ------------------------------------------------------------------
#include "defaults.config"
// ------------------------------------------------------------------

<fgu>
    -novera_build
    -novera_run
    -novcs_use_vera
    -config_rtl=USEMOD
    -asm_diag_root=$DV_ROOT/verif/diag
        -vera_diag_root=$DV_ROOT/verif/diag
        -vera_config_root=$DV_ROOT/verif
        -vera_vcon_file=fgu.vcon
        -image_diag_root=$DV_ROOT/verif
        -wait_cycle_to_kill=10
    -model=fgu
        -flist=$DV_ROOT/verif/env/fgu/fgu.flist
        -env_base=$DV_ROOT/verif/env/fgu
    -drm_disk=[/export/home/bw=30]
        -drm_type=random
        -drm_freeram=1000
        -drm_freeprocessor=1.0
        -drm_license=[vcs=1]
    SUNVFORCEOPTS
    -sunv_args=-version
    -sunv_args=-topcell=DUT_MOD
        -sunv_args=-out=DUT_MOD.v
            -sunv_args=-showCompiledOutCode=off
            -sunv_args=-define=SIM
            -sunv_args=-define=LIB
            -sunv_args=-define=INITLATZERO
//cpu   -sunv_args=-define=RTL_NO_SPC1
//cpu   -sunv_args=-define=RTL_NO_SPC2
//cpu   -sunv_args=-define=RTL_NO_SPC3
//cpu   -sunv_args=-define=RTL_NO_SPC4
//cpu   -sunv_args=-define=RTL_NO_SPC5
//cpu   -sunv_args=-define=RTL_NO_SPC6
//cpu   -sunv_args=-define=RTL_NO_SPC7
//cpu   -sunv_args=-primitives=$DV_ROOT/verif/env/fgu/primitive.list
        -sunv_args=-path=SUNV_RTL_PATH
      -sunv_args=-excludepreload
    -sunv_args=-ignorepartial
            -sunv_args=-unusednet='unused$:unused\[[0-9]+\]$'
            -sunv_args=-warn=2000
            -sunv_args=-preload=SUNVLIBS_SUNV
            -sunv_args=-perlinclude=SUNVPERLINC
    -vlint_top=DUT_MOD
        -vlint_args=-turn_unspecified_off
        -vlint_args=-binary
        -vlint_args=-vlint
        -vlint_args=-depth 999
        -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc
            -vlint_args=SUNVLIBS_OTHER
    -zeroIn_build_args=-fastmod
    -zeroIn_build_args=-exit_on_directive_errors
    -zeroIn_build_args=-d fgu_top
        -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/fgu/fgu_zeroIn_cfg.v
        -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/fgu/fgu_checkers.v
#ifdef ZEROINCOV
#ifdef FGUSAT
        -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/fgu/fgusat_0in_cov.v
#else
        -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/fgu/fgusparc_0in_cov.v
#endif
#else
    -zeroIn_build_args="-fastsim turbo"
#endif
            -zeroIn_build_args=-sim vcs
            -zeroIn_build_args=SUNVLIBS_OTHER
    -vcs_build_args=+v2k
        -vcs_build_args=-y $DV_ROOT/design/exu/rtl
        -vcs_build_args=+define+LIB
        -vcs_build_args=+define+INITLATZERO
        -vcs_build_args=+incdir+$DV_ROOT/verif/env/fgu
        -vcs_build_args=+incdir+$DV_ROOT/verif/env/common/coverage/fgu
    -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab"
    -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a
        -vcs_use_vera
        -vcs_use_ntb
            -vcs_build_args=SUNVLIBS_OTHER
    -vcs_run_args=+0in_checker_finish_delay+30
    -vcs_run_args=+VERB=10
</fgu>