// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: axis_modules.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
//----------------------------------------------------------
//----------------------------------------------------------
module axis_clock_gen(sclkdiv2,sclk,sysclk);
`ifdef AXIS_FBDIMM_NO_FSR
assign sclkdiv2 = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk44;
assign sclkdiv2 = tb_top.cpu.ccu.ccu_pll.clk44;
assign sclkdiv2 = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk44;
assign sysclk=tb_top.cpu.ccu.ccu_pll.clk2424;
assign sysclk=tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk2424;
`ifdef AXIS_FBDIMM_NO_FSR
assign sclk = tb_top.cpu.ccu.ccu_pll.clk33;
assign sclk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk33;
assign sclk = tb_top.cpu.ccu.ccu_pll.clk11;
assign sclk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk11;
assign sclk = tb_top.cpu.ccu.ccu_pll.clk2424;
assign sclk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk2424;
module axis_clock_force (mac_clk,peu_clk);
assign tb_top.cpu.psr_peu_txbclk0 = peu_clk; //ref clk to PEU
assign tb_top.cpu.mac.esr_mac_tclk_0 = mac_clk; //ref clk inputs to xMAC
assign tb_top.cpu.mac.esr_mac_tclk_1 = mac_clk;
assign tb_top.cpu.mac.esr_mac_rclk_0[3] = mac_clk; //ref clk inputs to xMAC
assign tb_top.cpu.mac.esr_mac_rclk_0[2] = mac_clk; // req'd for xPCS loopback
assign tb_top.cpu.mac.esr_mac_rclk_0[1] = mac_clk;
assign tb_top.cpu.mac.esr_mac_rclk_0[0] = mac_clk;
assign tb_top.cpu.mac.esr_mac_rclk_1[3] = mac_clk;
assign tb_top.cpu.mac.esr_mac_rclk_1[2] = mac_clk;
assign tb_top.cpu.mac.esr_mac_rclk_1[1] = mac_clk;
assign tb_top.cpu.mac.esr_mac_rclk_1[0] = mac_clk;
module axis_clock_generator (sclk,fbclk,sysclk);
assign mac_clk = tb_top.cpu.ccu.ccu_pll.n2_core_pll_cust.mac_clk_1;
assign peu_clk = tb_top.cpu.ccu.ccu_pll.n2_core_pll_cust.peu_clk_1;
assign mac_clk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.mac_clk_1;
assign peu_clk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.peu_clk_1;
//assign sclk;=axis_clock_gen.sclk;
//assign fbclk;=axis_clock_gen.sclkdiv2;
//assign sysclk; //=axis_clock_gen.sysclk;
axis_clock_force axis_clock_force (mac_clk,peu_clk);
axis_clock_gen axis_clock_gen (fbclk,sclk,sysclk);
wire [17:0] a_adr0 = addr;
wire [111:0] a_data0=pc_r;
reg [112:0] DBUFF [0:262143];
// always @ (a_adr0 or a_data0 or a_we)
// DBUFF[a_adr0] <= a_data0 ;
`else // !`ifdef PALLADIUM
axis_smem #(18, 112, 1, 0) DBUFF
{a_we }, // Write Enable : 1'b0 means always read
{1'bz }, // Clocks : 1'bz means asynchronous
initial inact_cnt = 64'b1;
always @(posedge clk) begin
pc_r <= {cycle[63:0],pc[47:0]};
if (pc[47:0] != last_pc[47:0]) begin
if (!tb_top.pc_trc_mode || (pc[47:0] != last_pc[47:0]+4)) begin
if (addr == 0) ptr_0_cycle <= cycle;
if ((pc[47:0] != 0) && (pc[47:44] != 4'hf)) inact_cnt <= inact_cnt + 1;
if (inact_cnt == tb_top.thread_wdto) begin // axis tbcall_region
$display("INACT%h_%h at cycle %d, t=%d.",core_r,thread_r,cycle_r,$time);
if(tb_top.stop_on_wdto) begin
module jtag_ice (tms,tdi,tdo,tck,tck_fb);
reg tms_r,tdi_r,tdo_r,tck_r,tck_r2, tck_r3,tck_r_r;
assign tck_fb_to_asl=tck_fb;
always @(posedge tb_top.cpu.ccu.ccu_pll.clk22) begin
always @(posedge tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk22) begin
always @(posedge tck_r_r)
if (dbg & (tms_r | tdi_r | tck_r | tdo_r))
begin // axis tbcall_region
$display($time,"dbg:tms,tdi,tck,tdo %b %b %b %b",tms_r,tdi_r,tck_r,tdo_r);
reg tms_r1,tdi_r1,tdo_r1,tck_r1;
always @(posedge tb_top.cpu.ccu.ccu_pll.clk22) begin
always @(posedge tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk22) begin
always @(tms_r1 or tdi_r1 or tck_r1 or tdo_r1)
begin // axis tbcall_region
$display($time,"dbg1: tms,tdi,tck,tdo %b %b %b %b",tms_r1,tdi_r1,tck_r1,tdo_r1);
wire tck_fb_to_asl_a=tck_fb_to_asl;
wire tck_fb_to_asl_b=tck_fb_to_asl;
axis_asl_use (tdo_to_asl,"d",11,"js1",88);
axis_asl_use (tck_fb_to_asl,"d",11,"js1",89);
axis_asl_use (tck_fb_to_asl_a,"d",11,"js1",93);
axis_asl_use (tck_fb_to_asl_b,"d",11,"js1",97);
axis_asl_drive (tms_from_asl,"d",11,"js1",138);
axis_asl_drive (tdi_from_asl,"d",11,"js1",96);
axis_asl_drive (tck_from_asl,"c",11,"js1",92);
module axis_mcu_errmon (clk,
parameter INST = 0; // Instance of MCU
wire [31:0] rdpctl_err_sts_next;
reg [31:0] rdpctl_err_sts_reg;
assign rdpctl_err_sts_next[25:16] = {rdpctl_meu_error, rdpctl_mec_error, rdpctl_dac_error, rdpctl_dau_error,
rdpctl_dsc_error, rdpctl_dsu_error, rdpctl_dbu_error, rdpctl_meb_error,
rdpctl_fbu_error, rdpctl_fbr_error};
// always @(posedge clk) begin
always @(rdpctl_err_sts_next) begin
if(rdpctl_err_sts_reg != rdpctl_err_sts_next) begin // axis tbcall_region
$display("%d mcu%d rdpctl_err_sts_next <= %08X", $time, INST, rdpctl_err_sts_next);
rdpctl_err_sts_reg <= rdpctl_err_sts_next;
endmodule // axis_mcu_errmon