verif/env/fc/vera/interfaces/ssi.if.vrh

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ssi.if.vrh
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// ========== Copyright Header End ============================================
#ifndef INC_SSI_IF_VRH
#define INC_SSI_IF_VRH


#include <vera_defines.vrh>
#include "defines.vri"

interface ssi_if {

        input           clk     CLOCK           verilog_node "tb_top.SSI_SCK";
        input           ssi_mosi      PSAMPLE      #-0      verilog_node "tb_top.SSI_MOSI";
        output          ssi_miso      PHOLD     #0     verilog_node "tb_top.SSI_MISO";
        output          ssi_int_l     PHOLD     #0     verilog_node "tb_top.SSI_EXT_INT_L";
        input          ssi_sync_l     PSAMPLE      #-0       verilog_node "tb_top.SSI_SYNC_L";
//        input          ssi_reset_l    PSAMPLE      #-0       verilog_node "tb_top.PEX_RESET_L";
        input          ssi_reset_l    PSAMPLE      #-0       verilog_node "tb_top.SSI_SYNC_L";

}

port ssi_iport {
  clk;
  data;
  reset;
}

port ssi_oport {
  clk;
  data;
  int_l;
  sync_l;
}


bind ssi_iport ncu {
  clk ssi_if.clk;
  data ssi_if.ssi_mosi;
  reset ssi_if.ssi_reset_l;
}

bind ssi_oport ssi {
  clk ssi_if.clk;
  data ssi_if.ssi_miso;
  int_l ssi_if.ssi_int_l;
  sync_l ssi_if.ssi_sync_l;
}

#endif