verif/env/niu/mac_sat/vera/include/ntx_mac_drv_ports.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ntx_mac_drv_ports.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#define OMF_CK_IN_TIMING   PSAMPLE #-1
#define OMF_CK_OUT_TIMING  PHOLD #1
#define OMF_CK_CLK_TIMING  CLOCK
#include "neptune_defines.vri"

#ifdef NEPTUNE

interface fom0_if {
   output  [63:0] tx_data       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_data0";
   output  [3:0]  tx_stat       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_stat0";
   output         tx_abort      OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_abort0";
   output         tx_tag        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_tag0";
   input          tx_mac_req    OMF_CK_IN_TIMING   verilog_node  MAC_DUV_PATH.mac_txc_req0";
   output         tx_ack        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_ack0";
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_4ports.clk";
}

interface fom1_if {
   output  [63:0] tx_data       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_data1";
   output  [3:0]  tx_stat       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_stat1";
   output         tx_abort      OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_abort1";
   output         tx_tag        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_tag1";
   input          tx_mac_req    OMF_CK_IN_TIMING   verilog_node  MAC_DUV_PATH.mac_txc_req1";
   output         tx_ack        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_ack1";
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_4ports.clk";
}

interface fom2_if {
   output  [63:0] tx_data       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_data2";
   output         tx_tag        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_tag2";
   input          tx_mac_req    OMF_CK_IN_TIMING   verilog_node  MAC_DUV_PATH.mac_txc_req2";
   output         tx_ack        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_ack2";
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_4ports.clk";
}
interface fom3_if {
   output  [63:0] tx_data       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_data3";
   output         tx_tag        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_tag3";
   input          tx_mac_req    OMF_CK_IN_TIMING   verilog_node  MAC_DUV_PATH.mac_txc_req3";
   output         tx_ack        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_ack3";
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_4ports.clk";
}

#else

interface fom0_if {
   output  [63:0] tx_data       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_data0";
   output  [3:0]  tx_stat       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_stat0";
   output         tx_abort      OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_abort0";
   output         tx_tag        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_tag0";
   input          tx_mac_req    OMF_CK_IN_TIMING   verilog_node  MAC_DUV_PATH.mac_txc_req0";
   output         tx_ack        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_ack0";
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_core.mac_2ports.niu_clk";
}

interface fom1_if {
   output  [63:0] tx_data       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_data1";
   output  [3:0]  tx_stat       OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_stat1";
   output         tx_abort      OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_abort1";
   output         tx_tag        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_tag1";
   input          tx_mac_req    OMF_CK_IN_TIMING   verilog_node  MAC_DUV_PATH.mac_txc_req1";
   output         tx_ack        OMF_CK_OUT_TIMING  verilog_node  MAC_DUV_PATH.txc_mac_ack1";
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_core.mac_2ports.niu_clk";
}

#endif

#ifdef NEPTUNE
interface id_if {
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_4ports.clk";
}

#else

interface id_if {
   input          clk           OMF_CK_CLK_TIMING  verilog_node  MAC_DUV_PATH.mac_core.mac_2ports.niu_clk";
}

#endif

port xfom_def {
  tx_data;
  tx_stat;
  tx_abort;
  tx_tag;
  tx_mac_req;
  tx_ack;
  clk;
 }

port fom_def {
  tx_data;
  tx_tag;
  tx_mac_req;
  tx_ack;
  clk;
 }


port id_def {
  //   init_done;
      clk;
 }

bind id_def init {

   //  init_done  id_if.init_done;
      clk    id_if.clk;

}

#ifdef NEPTUNE
bind xfom_def fom0 {
  tx_data       fom0_if.tx_data;
  tx_stat       fom0_if.tx_stat;
  tx_abort      fom0_if.tx_abort;
  tx_tag        fom0_if.tx_tag;
  tx_mac_req    fom0_if.tx_mac_req;
  tx_ack        fom0_if.tx_ack;
  clk           fom0_if.clk;
   }

bind xfom_def fom1 {
  tx_data       fom1_if.tx_data;
  tx_stat       fom1_if.tx_stat;
  tx_abort      fom1_if.tx_abort;
  tx_tag        fom1_if.tx_tag;
  tx_mac_req    fom1_if.tx_mac_req;
  tx_ack        fom1_if.tx_ack;
  clk           fom1_if.clk;
   }

bind fom_def fom2 {
  tx_data       fom2_if.tx_data;
  tx_tag        fom2_if.tx_tag;
  tx_mac_req    fom2_if.tx_mac_req;
  tx_ack        fom2_if.tx_ack;
  clk           fom2_if.clk;
   }


bind fom_def fom3 {
  tx_data       fom3_if.tx_data;
  tx_tag        fom3_if.tx_tag;
  tx_mac_req    fom3_if.tx_mac_req;
  tx_ack        fom3_if.tx_ack;
  clk           fom3_if.clk;
   }

#else

bind xfom_def fom0 {
  tx_data       fom0_if.tx_data;
  tx_stat       fom0_if.tx_stat;
  tx_abort      fom0_if.tx_abort;
  tx_tag        fom0_if.tx_tag;
  tx_mac_req    fom0_if.tx_mac_req;
  tx_ack        fom0_if.tx_ack;
  clk           fom0_if.clk;
   }

bind xfom_def fom1 {
  tx_data       fom1_if.tx_data;
  tx_stat       fom1_if.tx_stat;
  tx_abort      fom1_if.tx_abort;
  tx_tag        fom1_if.tx_tag;
  tx_mac_req    fom1_if.tx_mac_req;
  tx_ack        fom1_if.tx_ack;
  clk           fom1_if.clk;
   }

#endif