verif/env/niu/vera/include/niu_verilog_tasks.vri

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//
// OpenSPARC T2 Processor File: niu_verilog_tasks.vri
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  #ifdef N2_FC
    hdl_task force_vlan_tbl_entry(bit[15:0] mem_addr, bit[17:0] mem_wr_data) "tb_top.force_vlan_tbl_entry";
    hdl_task force_rxc_cksum_be_partial() "tb_top.force_rxc_cksum_be_partial";
  #else
    hdl_task assert_mdint(bit[2:0] id) "tb_top.assert_mdint";
    hdl_task deassert_mdint(bit[2:0] id) "tb_top.deassert_mdint";
    hdl_task check_mdint_status(bit[2:0] id, var bit status) "tb_top.check_mdint_status";
    //following from vera_top.vr to consolidate all defines here
    hdl_task force_tcam_entry (bit [7:0] tcam_index, bit [199:0] tcam_key) "tb_top.force_tcam_entry" ;
    hdl_task backdoor_init_tcam () "tb_top.backdoor_init_tcam" ;
    hdl_task test_debug_port() "tb_top.test_debug_port" ;

    hdl_task niu_reset(bit[7:0] no_of_clocks) "tb_top.niu_reset";
    hdl_task force_vlan_tbl_entry(bit[15:0] mem_addr, bit[17:0] mem_wr_data) "tb_top.force_vlan_tbl_entry";
    hdl_task force_rxc_cksum_be_partial() "tb_top.force_rxc_cksum_be_partial";
  #endif