Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / vera / niu_pio / dmc_util.vr
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: dmc_util.vr
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
#include <vera_defines.vrh>
#include "dmc_memory_map.vri"
#include "pio_driver.vrh"
#include "niu_mem.vrh"
extern niu_gen_pio gen_pio_drv;
extern CSparseMem SparseMem;
//inclune "dmc_shadow_class.vrh"
#include "cMesg.vrh"
extern Mesg be_msg;
class dmc_util_class {
task new( ) ;
task dmc_init ();
}
task dmc_util_class::new( ) { }
task dmc_util_class::dmc_init () {
bit [63:0] read_data;
integer status;
integer i;
bit [63:0] data;
bit [ 63:0] address;
//gen_pio_drv.pio_wr(RXDMA_CFIG1,64'h0000_0000_8000_0000); //b31 DMA-EN
//gen_pio_drv.pio_wr(RBR_CFIG_A,64'h00FF_0000_0000_0200); // LEN FF , START ADDR 200
////gen_pio_drv.pio_wr(RBR_CFIG_B,64'h0000_0000_0080_8080); //Set all 3 sizes S,M &L
//gen_pio_drv.pio_wr(RBR_CFIG_B,64'h0000_0000_0000_0080); //Set all 3 sizes S,M &L
//gen_pio_drv.pio_wr(RX_LOG_PAGE_VLD,64'h0000_0000_0000_0003);// Logical Page0&1 valid
//gen_pio_drv.pio_wr(RCRCFIG_A,64'h000F_0000_0000_0040);
//gen_pio_drv.pio_wr(TBR_CFIG_A,64'h000F_0000_0000_0080);
//gen_pio_drv.pio_wr(RBR_KICK,64'h0000_0000_0000_0128); //KICK 8 buffers
gen_pio_drv.pio_wr(RBR_HDH,64'h0000_0000_0000_0200);
gen_pio_drv.pio_wr(RBR_HDL,64'h0000_0000_0000_0006);
//gen_pio_drv.pio_wr(RCR_CFIG_A,64'h00FF_0000_0004_0000); // LEN FF , START ADDR 200
be_msg.print(e_mesg_info, "dmc_init", "dmc_pio_class","DMC INIT DONE\n");
}