verif/env/niu/vera/niu_pio/include/fflp_memory_map.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fflp_memory_map.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
#include "neptune_memory_map.vri"

#define fullFFLP_CONFIG          FFLP_ADDRESS_RANGE+FFLP_CONFIG
#define fullFFLP_CAM_KEY_REG0    FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG0
#define fullFFLP_CAM_KEY_REG1    FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG1
#define fullFFLP_CAM_KEY_REG2    FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG2
#define fullFFLP_CAM_KEY_REG3    FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG3
#define fullFFLP_CAM_MASK_REG0   FFLP_ADDRESS_RANGE+20'h0_00b0
#define fullFFLP_CAM_MASK_REG1   FFLP_ADDRESS_RANGE+20'h0_00b8
#define fullFFLP_CAM_MASK_REG2   FFLP_ADDRESS_RANGE+20'h0_00c0
#define fullFFLP_CAM_MASK_REG3   FFLP_ADDRESS_RANGE+20'h0_00c8
#define fullFFLP_CAM_CONTROL     FFLP_ADDRESS_RANGE+FFLP_CAM_CONTROL
#define fullFFLP_TCAM_ERR        FFLP_ADDRESS_RANGE+FFLP_TCAM_ERR

#define FFLP_CONFIG                      20'h0_0100
#define FFLP_DBG_TRAIN_VCT               20'h0_0148
#define FFLP_TCP_CFLAG_MASK              20'h0_0108
#define FFLP_FCRAM_REF_TMR               20'h0_0110
#define FFLP_FCRAM_FIO_ADDR              20'h0_0118
#define FFLP_FCRAM_FIO_DAT               20'h0_0120
#define FFLP_FCRAM_PHY_RD_LAT            20'h0_0150

//L2 class2 class3
#define FFLP_L2_CLS_2                    20'h0_0000
#define FFLP_L2_CLS_3                    20'h0_0008

//L3 class4-7
#define FFLP_L3_CLS_4                    20'h0_0010
#define FFLP_L3_CLS_5                    20'h0_0018
#define FFLP_L3_CLS_6                    20'h0_0020
#define FFLP_L3_CLS_7                    20'h0_0028


//CAM KEY & MASK
#define FFLP_CAM_KEY_REG0                20'h0_0090
#define FFLP_CAM_KEY_REG1                20'h0_0098
#define FFLP_CAM_KEY_REG2                20'h0_00a0
#define FFLP_CAM_KEY_REG3                20'h0_00a8
#define FFLP_CAM_KEY_MASK_REG0           20'h0_00b0
#define FFLP_CAM_KEY_MASK_REG1           20'h0_00b8
#define FFLP_CAM_KEY_MASK_REG2           20'h0_00c0
#define FFLP_CAM_KEY_MASK_REG3           20'h0_00c8
#define FFLP_CAM_CONTROL                 20'h0_00d0

//HOW TO BUILD TCAM KEY REGISTERS
#define FFLP_HOW_TCAM_KEY_CLS_4          20'h0_0030
#define FFLP_HOW_TCAM_KEY_CLS_5          20'h0_0038
#define FFLP_HOW_TCAM_KEY_CLS_6          20'h0_0040
#define FFLP_HOW_TCAM_KEY_CLS_7          20'h0_0048
#define FFLP_HOW_TCAM_KEY_CLS_8          20'h0_0050
#define FFLP_HOW_TCAM_KEY_CLS_9          20'h0_0058
#define FFLP_HOW_TCAM_KEY_CLS_A          20'h0_0060
#define FFLP_HOW_TCAM_KEY_CLS_B          20'h0_0068
#define FFLP_HOW_TCAM_KEY_CLS_C          20'h0_0070
#define FFLP_HOW_TCAM_KEY_CLS_D          20'h0_0078
#define FFLP_HOW_TCAM_KEY_CLS_E          20'h0_0080
#define FFLP_HOW_TCAM_KEY_CLS_F          20'h0_0088

//HOW TO BUILD FLOW KEY REGISTERS
#define FFLP_HOW_FLOW_KEY_CLS_4          20'h0_0000
#define FFLP_HOW_FLOW_KEY_CLS_5          20'h0_0008
#define FFLP_HOW_FLOW_KEY_CLS_6          20'h0_0010
#define FFLP_HOW_FLOW_KEY_CLS_7          20'h0_0018
#define FFLP_HOW_FLOW_KEY_CLS_8          20'h0_0020
#define FFLP_HOW_FLOW_KEY_CLS_9          20'h0_0028
#define FFLP_HOW_FLOW_KEY_CLS_A          20'h0_0030
#define FFLP_HOW_FLOW_KEY_CLS_B          20'h0_0038
#define FFLP_HOW_FLOW_KEY_CLS_C          20'h0_0040
#define FFLP_HOW_FLOW_KEY_CLS_D          20'h0_0048
#define FFLP_HOW_FLOW_KEY_CLS_E          20'h0_0050
#define FFLP_HOW_FLOW_KEY_CLS_F          20'h0_0058

#define FFLP_FLOW_H1POLY                 20'h0_0060
#define FFLP_FLOW_H2POLY                 20'h0_0068
#define FFLP_FLOW_PARTITION_SEL          20'h0_0070
#define FFLP_HASH_TABLE_ADDR             20'h0_0000  // count 8 step 8192
#define FFLP_HASH_TABLE_DATA             20'h0_0008  // count 8 step 8192
#define FFLP_HASH_TABLE_DATA_LOG         20'h0_0010  // count 8 step 8192

//ERROR reg
#define FFLP_VLAN_PAR_ERR                20'h0_8000
#define FFLP_TCAM_ERR                    20'h0_00d8
#define FFLP_HASH_TABLE_DATA_ERR         20'h0_0010
#define FFLP_HASH_TABLE_LOOKUP_ERR1      20'h0_00e0
#define FFLP_HASH_TABLE_LOOKUP_ERR2      20'h0_00e8
#define FFLP_FCRAM_ERR0                  20'h0_0128
#define FFLP_FCRAM_ERR1                  20'h0_0130
#define FFLP_FCRAM_ERR2                  20'h0_0138
#define FFLP_ERR_MASK                    20'h0_0140