verif/env/siu/vera/packets/siu_dmu_packet.vr

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//
// OpenSPARC T2 Processor File: siu_dmu_packet.vr
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#include "siu_basic_packet.vrh"
#include "siu_delay.vrh"

class siu_dmu_packet extends siu_basic_packet {

        // DMU variables
        // Packet type: DMU has PIO read, DMA read, Interrupt, DMA write, Flush packet type, for comparison
        // we need to simplified these to RDD, WRI, WR8, INT, FLUSH, PIO
        reg     read;           // read bit
        reg     bmask;          // byte mask active bit
        reg     target;         // 1 to L2, 0 to NCU
        reg [7:0] be[8];        // byte enable
        integer send_delay;

        task new(
        Siu_Packet_Type type,
        reg [15:0] id,
        reg [39:0] pa,
        reg        bypass = 0,
        reg        posted,
        reg        target,
        reg        ue = 0,
        reg        tout = 0,
        reg        uce = 0,             // un correctable error
        reg [63:0] data0 = 64'h0,
        reg [63:0] data1 = 64'h0,
        reg [63:0] data2 = 64'h0,
        reg [63:0] data3 = 64'h0,
        reg [63:0] data4 = 64'h0,
        reg [63:0] data5 = 64'h0,
        reg [63:0] data6 = 64'h0,
        reg [63:0] data7 = 64'h0,
        reg [7:0] be0 = 8'h0,
        reg [7:0] be1 = 8'h0,
        reg [7:0] be2 = 8'h0,
        reg [7:0] be3 = 8'h0,
        reg [7:0] be4 = 8'h0,
        reg [7:0] be5 = 8'h0,
        reg [7:0] be6 = 8'h0,
        reg [7:0] be7 = 8'h0,
        integer send_delay = DMU_SEND_DELAY_DEF
        );
}

MakeVeraList(siu_dmu_packet);

task siu_dmu_packet::new(
        Siu_Packet_Type type,
        reg [15:0] id,
        reg [39:0] pa,
        reg        bypass = 0,
        reg        posted,
        reg        target,
        reg        ue = 0,
        reg        tout = 0,
        reg        uce = 0,             // un correctable error
        reg [63:0] data0 = 64'h0,
        reg [63:0] data1 = 64'h0,
        reg [63:0] data2 = 64'h0,
        reg [63:0] data3 = 64'h0,
        reg [63:0] data4 = 64'h0,
        reg [63:0] data5 = 64'h0,
        reg [63:0] data6 = 64'h0,
        reg [63:0] data7 = 64'h0,
        reg [7:0] be0 = 8'h0,
        reg [7:0] be1 = 8'h0,
        reg [7:0] be2 = 8'h0,
        reg [7:0] be3 = 8'h0,
        reg [7:0] be4 = 8'h0,
        reg [7:0] be5 = 8'h0,
        reg [7:0] be6 = 8'h0,
        reg [7:0] be7 = 8'h0,
        integer send_delay = DMU_SEND_DELAY_DEF
)
{
        super.new(type, id, pa, bypass, posted, ue, tout, uce, data0, data1, data2, data3, data4, data5, data6, data7);

        // dmu-siu variables init
        this.target = target;
        this.tout = tout;
        this.uce = uce;
        this.be[0] = be0;
        this.be[1] = be1;
        this.be[2] = be2;
        this.be[3] = be3;
        this.be[4] = be4;
        this.be[5] = be5;
        this.be[6] = be6;
        this.be[7] = be7;
        this.send_delay = send_delay;
}