verif/env/tcu/vera/include/rst.if.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: rst.if.vri
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// ========== Copyright Header End ============================================
#ifndef INC_RST_IF_VRI
#define INC_RST_IF_VRI

#include "tcu_top_defines.vri"

interface sc {
  input  clk                   CLOCK                          verilog_node "`CPU.PLL_CMP_CLK_P";
  input  POR_L_IN              INPUT_EDGE  INPUT_SKEW         verilog_node "`CPU.PWRON_RST_L";
  output POR_L                 OUTPUT_EDGE_N         verilog_node "`CPU.PWRON_RST_L";
  output PB_XIR_L              OUTPUT_EDGE_N         verilog_node "`CPU.BUTTON_XIR_L";
  output PB_RST_L              OUTPUT_EDGE_N         verilog_node "`CPU.PB_RST_L";
}

interface rst {
  input  clk                         CLOCK                          verilog_node "`CPU.PLL_CMP_CLK_P";
  input  tb_clk_stop_all             INPUT_EDGE INPUT_SKEW          verilog_node "`MONTCU.tb_clk_stop_all";
  input  tb_clk_stop_one             INPUT_EDGE INPUT_SKEW          verilog_node "`MONTCU.tb_clk_stop_one";
}

interface rst_l2clk {
  input  clk_l2clk                   CLOCK                          verilog_node "`RST.l2clk";
  input  rst_niu_wmr_                INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_niu_wmr_";
  input  ccu_rst_change              INPUT_EDGE INPUT_SKEW          verilog_node "`RST.ccu_rst_change";
  input  tcu_bisx_done               INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_bisx_done";
  input  tcu_rst_efu_done            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_efu_done";
  input  tcu_pce_ov                  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_pce_ov";
  input  tcu_rst_io_clk_stop         INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_io_clk_stop";
  input  tcu_rst_flush_init_ack      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_flush_init_ack";
  input  tcu_rst_flush_stop_ack      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_flush_stop_ack";
  input  rst_tcu_flush_init_req      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_tcu_flush_init_req";
  input  rst_tcu_flush_stop_req      INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_tcu_flush_stop_req";
  input  rst_tcu_asicflush_stop_req  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_tcu_asicflush_stop_req";
  input  tcu_rst_asicflush_stop_ack  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_asicflush_stop_ack";
  input  rst_l2_por_                 INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_l2_por_";
  input  rst_l2_wmr_                 INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_l2_wmr_";
  input  rst_wmr_protect             INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_wmr_protect";
  input  rst_dmu_peu_por_            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_dmu_peu_por_";
  input  rst_dmu_peu_wmr_            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_dmu_peu_wmr_";
  input  ccu_rst_sync_stable         INPUT_EDGE INPUT_SKEW          verilog_node "`RST.ccu_rst_sync_stable";
  input  tcu_rst_scan_mode           INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_scan_mode";
}

interface rst_iol2clk {
  input  clk_iol2clk                 CLOCK                          verilog_node "`RST.iol2clk";
  input  rst_ncu_unpark_thread       INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_ncu_unpark_thread";
  input  rst_ncu_xir_                INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_ncu_xir_";
  input  ncu_rst_xir_done            INPUT_EDGE INPUT_SKEW          verilog_node "`RST.ncu_rst_xir_done";
  input  rst_mcu_selfrsh             INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_mcu_selfrsh";
#ifdef TCU_SAT
  output ncu_rst_fatal_error         OUTPUT_EDGE_N         verilog_node "`TOP.ncu_rst_fatal_error_vera"; // Forced in tcu_top.vh to enable driving the signal through vera
#else
  output ncu_rst_fatal_error         OUTPUT_EDGE_N         verilog_node "`NCU.ncu_rst_fatal_error";
#endif

  output l2t0_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t0_rst_fatal_error";
  output l2t1_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t1_rst_fatal_error";
  output l2t2_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t2_rst_fatal_error";
  output l2t3_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t3_rst_fatal_error";
  output l2t4_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t4_rst_fatal_error";
  output l2t5_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t5_rst_fatal_error";
  output l2t6_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t6_rst_fatal_error";
  output l2t7_rst_fatal_error        OUTPUT_EDGE_N         verilog_node "`RST.l2t7_rst_fatal_error";
}


#endif