verif/model/pcie/peu/peu_csr.hpp

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: peu_csr.hpp
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#ifndef INC_peu_csr_hpp__
#define INC_peu_csr_hpp__

#include <systemc.h>

#include "pcie_common/config.hpp"
#include "peu_defines.hpp"
#include "pcie_common/csr_if_port.hpp"

#include "pcie_common/data_port.hpp"
#include "pcie_common/logger.hpp"

#include <queue>

#define CSR_ADDR_T      sc_uint<32>
#define CSR_DATA_T      sc_uint<64>

namespace pcie {

  /** CSR Ring Intf packet format */
  class csr_pkt {
  public:
        bool                   is_rsp;
        sc_uint<CSR_CMND_WDTH> cmd;
        sc_uint<CSR_SRCB_WDTH> srcb;
        sc_uint<1>                 write;
        sc_uint<CSR_ADDR_WDTH> addr;
        sc_uint<CSR_DATA_WDTH> data;
        csr_pkt() {
          is_rsp = false;
          cmd = 0x0;
          srcb = 0x0;
          addr = 0x0;
          data = 0x0;
        }
  };

  /**
   * CSR Ring Interface protocol, specific to the T2 design
   */
  class peu_csr : public sc_module
  {
  public:
        peu_csr(sc_module_name module_name) :
          sc_module (module_name),
          csr_port("csr_port")
        {
          LOG_DEBUG << "> PEU_CSR(): CTOR() ";
          SC_THREAD(init);

          SC_THREAD(read_csr_ring);
          SC_THREAD(write_csr_ring);
          SC_THREAD(process_ring_req);
          LOG_DEBUG << "< PEU_CSR(): CTOR() ";
        }

        SC_HAS_PROCESS( peu_csr );

        sc_in  < sc_bv < CSR_RING_WDTH > >      ring_data_in;
        sc_out < sc_bv < CSR_RING_WDTH > >      ring_data_out;
        sc_in  < bool >                 csr_if_clk;
        sc_in  < bool >                 rst_l;

        sc_event csr_init_lock;

        csr_if_port<CSR_ADDR_T, CSR_DATA_T>     csr_port;

  private:
        void read_csr_ring();
        void write_csr_ring();
        void process_ring_req();
        void init();

        USE_NAMESPACE(std)queue<csr_pkt*>       ring_in_q;
        USE_NAMESPACE(std)queue<csr_pkt*>       ring_out_q;
  };

} // namespace pcie_tl

#endif // INC_etl_hpp__