verif/model/verilog/niu/niu_enet_models/phy_clock_doubler_env.v

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`timescale 1ns/10ps
module phy_clock_doubler_env(rbc0,rbc1,
        rbcx2);

input   rbc0;   // input from external SERDES, clocks odd bytes
input   rbc1;   // input from external SERDES, clocks even bytes
output  rbcx2;  // doubled version of clocks

wire    rbc0_ext_del4;  // rbc0_ext delayed 4 ns
wire    rbc1_ext_del4;  // rbc1_ext delayed 4 ns

assign #4000 rbc0_ext_del4 = rbc0;
assign #4000 rbc1_ext_del4 = rbc1;

assign rbcx2 = (~rbc0_ext_del4 & rbc0) |
                   (~rbc1_ext_del4 & rbc1);

endmodule