//////////////////////////////////////////////////////////////////////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// Projects compatibility: ////
//// 16550D uart (mostly supported) ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// Known problems (limits): ////
//// Nothing so far. ////
//// - gorban@opencores.org ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//////////////////////////////////////////////////////////////////////
//// Copyright (C) 2000, 2001 Authors ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//////////////////////////////////////////////////////////////////////
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
// Revision 1.1 2002/07/22 23:02:23 gorban
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
input [(addr_width - 1):0]
input [(addr_width - 1):0]
input [(data_width - 1):0]
output [(data_width - 1):0]
always @(posedge clk) begin