[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / common / include / dram.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: dram.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _DRAM_H
#define	_DRAM_H

#pragma ident	"@(#)dram.h	1.6	07/05/03 SMI"

#ifdef __cplusplus
extern "C" {
#endif

#include <platform/dram.h>

/*
 * Memory Controller definitions
 */

#define	NO_DRAM_BANKS			4
#define	DRAM_BANK_SHIFT			12
#define	DRAM_BANK_STEP			(1 << DRAM_BANK_SHIFT)

#define	DRAM_CSR_BASE  			DRAM_BASE
#define	DRAM_PORT_SHIFT  		12
#define	DRAM_MAX_PORT  			3

#define	DRAM_CAS_ADDR_WIDTH_REG		0x00
#define	DRAM_RAS_ADDR_WIDTH_REG		0x08
#define	DRAM_CAS_LAT_REG		0x10
#define	DRAM_SCRUB_FREQ_REG		0x18
#define	DRAM_REFRESH_FREQ_REG		0x20

/* power management, 1 reg per each pair of channels */
#define	DRAM_OPEN_BANK_MAX		0x28

#define	DRAM_REFRESH_COUNT_REG		0x38
#define	DRAM_SCRUB_ENABLE_REG		0x40

#define	DRAM_PROG_TIME_CTR		0x48	/* Power management */

#define	DRAM_TRRD_REG			0x80
#define	DRAM_TRC_REG			0x88
#define	DRAM_TRCD_REG			0x90
#define	DRAM_TWTR_REG			0x98
#define	DRAM_TRTW_REG			0xa0
#define	DRAM_TRTP_REG			0xa8
#define	DRAM_TRAS_REG			0xb0
#define	DRAM_TRP_REG			0xb8
#define	DRAM_TWR_REG			0xc0
#define	DRAM_TRFC_REG			0xc8
#define	DRAM_TMRD_REG			0xd0
#define	DRAM_TIWTR_REG			0xe0
#define	DRAM_PRECHARGE_WAIT_REG 	0xe8
#define	DRAM_DIMM_STACK_REG 		0x108
#define	DRAM_EXT_WR_MODE2_REG 		0x110
#define	DRAM_EXT_WR_MODE1_REG 		0x118
#define	DRAM_EXT_WR_MODE3_REG 		0x120
#define	DRAM_WAIR_CONTROL_REG 		0x128
#define	DRAM_RANK1_PRESENT_REG 		0x130
#define	DRAM_CHANNEL_DISABLE_REG 	0x138
#define	DRAM_SEL_LO_ADDR_BITS_REG 	0x140
#define	DRAM_SW_DV_COUNT_REG 		0x1b0
#define	DRAM_HW_DMUX_CLK_INV_REG 	0x1b8
#define	DRAM_PAD_EN_CLK_INV_REG 	0x1c0
#define	DRAM_DIMM_PRESENT_REG 		0x218
#define	DRAM_FAILOVER_STATUS_REG 	0x220
#define	DRAM_FAILOVER_MASK 		0x228
#define	DRAM_FBD_CHNL_RESET		0x810

/* HW DEBUG */
#define	DRAM_DBG_TRG_ENBL_REG 		0x230

/* ERROR Regs */
#define	DRAM_ERROR_STATUS_REG 		0x280
#define	DRAM_ERROR_ADDR_REG 		0x288
#define	DRAM_ERROR_INJ_REG 		0x290
#define	DRAM_ERROR_COUNTER_REG 		0x298
#define	DRAM_ERROR_LOC_REG 		0x2a0

#define	DRAM_ERROR_STATUS_INIT		0xfe00000000000000

/* Performance regs */
#define	DRAM_PERF_CTL_REG 		0x400
#define	DRAM_PERF_COUNT_REG 		0x408
#define	DRAM_PERF_CTL0			(DRAM_CSR_BASE + 0x0400)
#define	DRAM_PERF_COUNT0		(DRAM_CSR_BASE + 0x0408)
#define	DRAM_PERF_CTL1			(DRAM_CSR_BASE + 0x1400)
#define	DRAM_PERF_COUNT1		(DRAM_CSR_BASE + 0x1408)
#define	DRAM_PERF_CTL2			(DRAM_CSR_BASE + 0x2400)
#define	DRAM_PERF_COUNT2		(DRAM_CSR_BASE + 0x2408)
#define	DRAM_PERF_CTL3			(DRAM_CSR_BASE + 0x3400)
#define	DRAM_PERF_COUNT3		(DRAM_CSR_BASE + 0x3408)


/* Only 34 regs above are stored in scratch */
#define	DRAM_SCRATCH_CSR_SIZE   	34 * 8

#define	DRAM_DIMM_INIT_REG 		0x1a0
#define	DRAM_INIT_STATUS_REG 		0x210

#define	DRAM_DIMM_INIT_ENBL		1
#define	DRAM_DIMM_INIT_CKE_ENBL		2
#define	DRAM_DIMM_INIT_CLK_ENBL		4

/*
 * DRAM Error Status Register (Count 4 Step 4096)
 */
#define	DRAM_ESR_OFFSET		DRAM_ERROR_STATUS_REG
#define	DRAM_ESR_BASE		(DRAM_BASE + DRAM_ESR_OFFSET)
#define	DRAM_ESR_MEU		(1 << 63)
#define	DRAM_ESR_MEC		(1 << 62)
#define	DRAM_ESR_DAC		(1 << 61)
#define	DRAM_ESR_DAU		(1 << 60)
#define	DRAM_ESR_DSC		(1 << 59)
#define	DRAM_ESR_DSU		(1 << 58)
#define	DRAM_ESR_DBU		(1 << 57)
#define	DRAM_ESR_SYND_MASK	0xffff
#define	DRAM_ESR_SYND_SHIFT	0

#define	DRAM_ESR_CE_BITS	(DRAM_ESR_MEC | DRAM_ESR_DAC | DRAM_ESR_DSC)
#define	DRAM_ESR_UE_BITS	(DRAM_ESR_MEU | DRAM_ESR_DAU | \
				    DRAM_ESR_DSU | DRAM_ESR_DBU)

/*
 * DRAM Error Address Register (Count 4 Step 4096)
 */
#define	DRAM_EAR_OFFSET		DRAM_ERROR_ADDR_REG
#define	DRAM_EAR_BASE		(DRAM_BASE + DRAM_EAR_OFFSET)

/*
 * DRAM Error injection register (Count 4 Step 4096)
 */
#define	DRAM_EIR_OFFSET		DRAM_ERROR_INJ_REG
#define	DRAM_EIR_BASE		(DRAM_BASE + DRAM_EIR_OFFSET)

/*
 * DRAM Error Counter Register (count 4 Step 4096)
 */
#define	DRAM_ECR_OFFSET		DRAM_ERROR_COUNTER_REG
#define	DRAM_ECR_BASE		(DRAM_BASE + DRAM_ECR_OFFSET)
#define	DRAM_ECR_ENB		(1 << 17)
#define	DRAM_ECR_VALID		(1 << 16)
#define	DRAM_ECR_COUNT_MASK	0xffff
#define	DRAM_ECR_COUNT_SHIFT	0

/*
 * DRAM Error Location Register (Count 4 Step 4096)
 */
#define	DRAM_ELR_OFFSET		DRAM_ERROR_LOC_REG
#define	DRAM_ELR_BASE		(DRAM_BASE + DRAM_ELR_OFFSET)
#define	DRAM_ELR_LOC_MASK	0xfffffffff

/*
 * DRAM Scrub Enable Register (Count 4 Step 4096)
 */
#define	DRAM_SCRUB_ENABLE_REG_ENAB	1


#ifdef __cplusplus
}
#endif

#endif /* _DRAM_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: dram.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _DRAM_H
	50	#define _DRAM_H
	51
	52	#pragma ident "@(#)dram.h 1.6 07/05/03 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	#include <platform/dram.h>
	59
	60	/*
	61	* Memory Controller definitions
	62	*/
	63
	64	#define NO_DRAM_BANKS 4
65	#define DRAM_BANK_SHIFT 12
66	#define DRAM_BANK_STEP (1 << DRAM_BANK_SHIFT)
67
68	#define DRAM_CSR_BASE DRAM_BASE
69	#define DRAM_PORT_SHIFT 12
70	#define DRAM_MAX_PORT 3
71
72	#define DRAM_CAS_ADDR_WIDTH_REG 0x00
73	#define DRAM_RAS_ADDR_WIDTH_REG 0x08
74	#define DRAM_CAS_LAT_REG 0x10
75	#define DRAM_SCRUB_FREQ_REG 0x18
76	#define DRAM_REFRESH_FREQ_REG 0x20
77
78	/* power management, 1 reg per each pair of channels */
79	#define DRAM_OPEN_BANK_MAX 0x28
80
81	#define DRAM_REFRESH_COUNT_REG 0x38
82	#define DRAM_SCRUB_ENABLE_REG 0x40
83
84	#define DRAM_PROG_TIME_CTR 0x48 /* Power management */
85
86	#define DRAM_TRRD_REG 0x80
87	#define DRAM_TRC_REG 0x88
88	#define DRAM_TRCD_REG 0x90
89	#define DRAM_TWTR_REG 0x98
90	#define DRAM_TRTW_REG 0xa0
91	#define DRAM_TRTP_REG 0xa8
92	#define DRAM_TRAS_REG 0xb0
93	#define DRAM_TRP_REG 0xb8
94	#define DRAM_TWR_REG 0xc0
95	#define DRAM_TRFC_REG 0xc8
96	#define DRAM_TMRD_REG 0xd0
97	#define DRAM_TIWTR_REG 0xe0
98	#define DRAM_PRECHARGE_WAIT_REG 0xe8
99	#define DRAM_DIMM_STACK_REG 0x108
100	#define DRAM_EXT_WR_MODE2_REG 0x110
101	#define DRAM_EXT_WR_MODE1_REG 0x118
102	#define DRAM_EXT_WR_MODE3_REG 0x120
103	#define DRAM_WAIR_CONTROL_REG 0x128
104	#define DRAM_RANK1_PRESENT_REG 0x130
105	#define DRAM_CHANNEL_DISABLE_REG 0x138
106	#define DRAM_SEL_LO_ADDR_BITS_REG 0x140
107	#define DRAM_SW_DV_COUNT_REG 0x1b0
108	#define DRAM_HW_DMUX_CLK_INV_REG 0x1b8
109	#define DRAM_PAD_EN_CLK_INV_REG 0x1c0
110	#define DRAM_DIMM_PRESENT_REG 0x218
111	#define DRAM_FAILOVER_STATUS_REG 0x220
112	#define DRAM_FAILOVER_MASK 0x228
113	#define DRAM_FBD_CHNL_RESET 0x810
114
115	/* HW DEBUG */
116	#define DRAM_DBG_TRG_ENBL_REG 0x230
117
118	/* ERROR Regs */
119	#define DRAM_ERROR_STATUS_REG 0x280
120	#define DRAM_ERROR_ADDR_REG 0x288
121	#define DRAM_ERROR_INJ_REG 0x290
122	#define DRAM_ERROR_COUNTER_REG 0x298
123	#define DRAM_ERROR_LOC_REG 0x2a0
124
125	#define DRAM_ERROR_STATUS_INIT 0xfe00000000000000
126
127	/* Performance regs */
128	#define DRAM_PERF_CTL_REG 0x400
129	#define DRAM_PERF_COUNT_REG 0x408
130	#define DRAM_PERF_CTL0 (DRAM_CSR_BASE + 0x0400)
131	#define DRAM_PERF_COUNT0 (DRAM_CSR_BASE + 0x0408)
132	#define DRAM_PERF_CTL1 (DRAM_CSR_BASE + 0x1400)
133	#define DRAM_PERF_COUNT1 (DRAM_CSR_BASE + 0x1408)
134	#define DRAM_PERF_CTL2 (DRAM_CSR_BASE + 0x2400)
135	#define DRAM_PERF_COUNT2 (DRAM_CSR_BASE + 0x2408)
136	#define DRAM_PERF_CTL3 (DRAM_CSR_BASE + 0x3400)
137	#define DRAM_PERF_COUNT3 (DRAM_CSR_BASE + 0x3408)
138
139
140	/* Only 34 regs above are stored in scratch */
141	#define DRAM_SCRATCH_CSR_SIZE 34 * 8
142
143	#define DRAM_DIMM_INIT_REG 0x1a0
144	#define DRAM_INIT_STATUS_REG 0x210
145
146	#define DRAM_DIMM_INIT_ENBL 1
147	#define DRAM_DIMM_INIT_CKE_ENBL 2
148	#define DRAM_DIMM_INIT_CLK_ENBL 4
149
150	/*
151	* DRAM Error Status Register (Count 4 Step 4096)
152	*/
153	#define DRAM_ESR_OFFSET DRAM_ERROR_STATUS_REG
154	#define DRAM_ESR_BASE (DRAM_BASE + DRAM_ESR_OFFSET)
155	#define DRAM_ESR_MEU (1 << 63)
156	#define DRAM_ESR_MEC (1 << 62)
157	#define DRAM_ESR_DAC (1 << 61)
158	#define DRAM_ESR_DAU (1 << 60)
159	#define DRAM_ESR_DSC (1 << 59)
160	#define DRAM_ESR_DSU (1 << 58)
161	#define DRAM_ESR_DBU (1 << 57)
162	#define DRAM_ESR_SYND_MASK 0xffff
163	#define DRAM_ESR_SYND_SHIFT 0
164
165	#define DRAM_ESR_CE_BITS (DRAM_ESR_MEC \| DRAM_ESR_DAC \| DRAM_ESR_DSC)
166	#define DRAM_ESR_UE_BITS (DRAM_ESR_MEU \| DRAM_ESR_DAU \| \
167	DRAM_ESR_DSU \| DRAM_ESR_DBU)
168
169	/*
170	* DRAM Error Address Register (Count 4 Step 4096)
171	*/
172	#define DRAM_EAR_OFFSET DRAM_ERROR_ADDR_REG
173	#define DRAM_EAR_BASE (DRAM_BASE + DRAM_EAR_OFFSET)
174
175	/*
176	* DRAM Error injection register (Count 4 Step 4096)
177	*/
178	#define DRAM_EIR_OFFSET DRAM_ERROR_INJ_REG
179	#define DRAM_EIR_BASE (DRAM_BASE + DRAM_EIR_OFFSET)
180
181	/*
182	* DRAM Error Counter Register (count 4 Step 4096)
183	*/
184	#define DRAM_ECR_OFFSET DRAM_ERROR_COUNTER_REG
185	#define DRAM_ECR_BASE (DRAM_BASE + DRAM_ECR_OFFSET)
186	#define DRAM_ECR_ENB (1 << 17)
187	#define DRAM_ECR_VALID (1 << 16)
188	#define DRAM_ECR_COUNT_MASK 0xffff
189	#define DRAM_ECR_COUNT_SHIFT 0
190
191	/*
192	* DRAM Error Location Register (Count 4 Step 4096)
193	*/
194	#define DRAM_ELR_OFFSET DRAM_ERROR_LOC_REG
195	#define DRAM_ELR_BASE (DRAM_BASE + DRAM_ELR_OFFSET)
196	#define DRAM_ELR_LOC_MASK 0xfffffffff
197
198	/*
199	* DRAM Scrub Enable Register (Count 4 Step 4096)
200	*/
201	#define DRAM_SCRUB_ENABLE_REG_ENAB 1
202
203
204	#ifdef __cplusplus
205	}
206	#endif
207
208	#endif /* _DRAM_H */