[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / common / include / hprivregs.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: hprivregs.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _HPRIVREGS_H
#define	_HPRIVREGS_H

#pragma ident	"@(#)hprivregs.h	1.20	07/05/03 SMI"

#ifdef __cplusplus
extern "C" {
#endif

#include <platform/hprivregs.h>

/*
 * Niagara %ver
 */
#define	VER_MASK_SHIFT		24
#define	VER_MASK_MASK		0xff
#define	VER_MASK_MAJOR_SHIFT	(VER_MASK_SHIFT + 4)
#define	VER_MASK_MAJOR_MASK	0xf

/*
 * Hardware-implemented register windows
 */
#define	NWINDOWS	8

/*
 * Number of unique interrupts per strand
 */
#define	MAXINTR		64

/*
 * Max number of Global levels
 */
#define	MAXGL		3

/*
 * hpstate:
 *
 * +-----------------------------------------------------+
 * | rsvd | ENB | rsvd | RED | rsvd | HPRIV | rsvd | TLZ |
 * +-----------------------------------------------------+
 *  63..12  11   10..6    5    4..3     2       1     0
 */

#define	HPSTATE_TLZ	0x0001
#define	HPSTATE_HPRIV	0x0004
#define	HPSTATE_RED	0x0020
#define	HPSTATE_ENB	0x0800

/*
 * htstate:
 *
 * +-----------------------------------------+
 * | rsvd |  RED | rsvd | HPRIV | rsvd | TLZ |
 * +-----------------------------------------+
 *  63..6     5    4..3     2       1     0
 */

#define	HTSTATE_TLZ	0x0001
#define	HTSTATE_HPRIV	0x0004
#define	HTSTATE_RED	0x0010
#define	HTSTATE_ENB	0x0800

/*
 * hstickpending:
 *
 * +------------+
 * | rsvd | HSP |
 * +------------+
 *  63..1    0
 */

#define	HSTICKPEND_HSP	0x1

/*
 * htba:
 *
 * +---------------------------+
 * |    TBA     | TBATL | rsvd |
 * +---------------------------+
 *     63..15      14    13..0
 */
#define	TBATL		0x4000
#define	TBATL_SHIFT	14

/*
 * TLB demap register bit definitions
 * (ASI_DMMU_DEMAP/ASI_IMMU_DEMAP)
 */
#define	TLB_R_BIT		(0x200)
#define	TLB_DEMAP_PAGE_TYPE	0x00
#define	TLB_DEMAP_CTX_TYPE	0x40
#define	TLB_DEMAP_ALL_TYPE	0x80
#define	TLB_DEMAP_PRIMARY	0x00
#define	TLB_DEMAP_SECONDARY	0x10
#define	TLB_DEMAP_NUCLEUS	0x20

/*
 * LSU Control Register
 */
#define	ASI_LSUCR	0x45
#define	LSUCR_IC	0x000000001	/* I$ enable */
#define	LSUCR_DC	0x000000002	/* D$ enable */
#define	LSUCR_IM	0x000000004	/* IMMU enable */
#define	LSUCR_DM	0x000000008	/* DMMU enable */

/*
 * Misc
 */
#define	L2_CTL_REG	0xa900000000
#define	L2CR_DIS	0x00000001	/* L2$ Disable */
#define	L2CR_DMMODE	0x00000002	/* L2$ Direct-mapped mode */
#define	L2CR_SCRUBEN	0x00000004	/* L2$ Hardware scrub enable */

/*
 * INT_VEC_DIS constants
 */
#define	INT_VEC_DIS_TYPE_SHIFT	16
#define	INT_VEC_DIS_VCID_SHIFT	8
#define	INT_VEC_DIS_TYPE_INT	0x0
#define	INT_VEC_DIS_TYPE_RESET	0x1
#define	INT_VEC_DIS_TYPE_IDLE	0x2
#define	INT_VEC_DIS_TYPE_RESUME	0x3
#define	INT_VEC_DIS_VECTOR_RESET  0x1

/* BEGIN CSTYLED */
/*
 * Interrupt Vector Dispatch Macros
 */
/*
 * INT_VEC_DSPCH_ONE - interrupt vector dispatch one target
 *
 * Sends interrupt TYPE to any strand including the executing one.
 *
 * Delay Slot: no
 */
/* BEGIN CSTYLED */
#define	INT_VEC_DSPCH_ONE(TYPE, tgt, scr1, scr2) \
	setx	IOBBASE + INT_VEC_DIS, scr1, scr2			;\
	set	(TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1			;\
	sllx	tgt, INT_VEC_DIS_VCID_SHIFT, tgt			;\
	or	scr1, tgt, scr1						;\
	stx	scr1, [scr2]
/* END CSTYLED */

/*
 * INT_VEC_DSPCH_ALL - interrupt vector dispatch all
 *
 * Sends interrupt TYPE to all strands whose bit is set in SRC, excluding
 *   the executing one. SRC and DST bitmasks are updated.
 *
 * Delay Slot: no
 */
/* BEGIN CSTYLED */
#define	INT_VEC_DSPCH_ALL(TYPE, SRC, DST, scr1, scr2) \
	.pushlocals							;\
	rd	STR_STATUS_REG, scr2		/* my ID             */	;\
	srlx	scr2, STR_STATUS_CPU_ID_SHIFT, scr2			;\
	and	scr2, STR_STATUS_CPU_ID_MASK, scr2			;\
	mov	1, scr1							;\
	sllx	scr1, scr2, scr1		/* my bit            */	;\
	ldx	[SRC], scr2			/* Source state      */	;\
	stx	scr1, [SRC]			/* new Source        */	;\
	bclr	scr1, scr2			/* clear my bit      */	;\
	ldx	[DST], scr1			/* Destination state */	;\
	bset	scr2, scr1			/* add new bits      */	;\
	stx	scr1, [DST]			/* new To            */	;\
	setx	IOBBASE + INT_VEC_DIS, scr1, DST			;\
	set	(TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1			;\
1:	btst	1, scr2				/* valid strand?     */	;\
	bnz,a,pn %xcc, 2f			/*   yes: store      */	;\
	  stx	scr1, [DST]			/*   no: annul       */	;\
2:	srlx	scr2, 1, scr2			/* next strand bit   */	;\
	brnz	scr2, 1b			/* more to do        */	;\
	  inc	1 << INT_VEC_DIS_VCID_SHIFT, scr1			;\
	.poplocals
/* END CSTYLED */

/*
 * IDLE_ALL_STRAND
 *
 * Sends interrupt IDLE to all strands whose bit is set in CONFIG_STACTIVE,
 * excluding the executing one. CONFIG_STACTIVE, CONFIG_STIDLE are
 * updated.
 *
 * Delay Slot: no
 */
/* BEGIN CSTYLED */
#define	IDLE_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
	ldx	[strand + STRAND_CONFIGP], scr1	/* ->config*/		;\
	add	scr1, CONFIG_STACTIVE, scr3	/* ->active mask */	;\
	add	scr1, CONFIG_STIDLE, scr4	/* ->idle mask   */	;\
	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_IDLE, scr3, scr4, scr1, scr2)
/* END CSTYLED */

/* BEGIN CSTYLED */
#define	RESUME_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
	ldx	[strand + STRAND_CONFIGP], scr1	/* ->config*/		;\
	add	scr1, CONFIG_STIDLE, scr3	/* ->idle mask   */	;\
	add	scr1, CONFIG_STACTIVE, scr4	/* ->active mask */	;\
	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_RESUME, scr3, scr4, scr1, scr2)

#define	IS_STRAND_(state, vcpup, strand, scr1, scr2) \
	mov	1, scr1				/* bit */		;\
	sllx	scr1, strand, scr1		/* 1<<strand */		;\
	VCPU2ROOT_STRUCT(vcpup, scr2)		/* ->config*/		;\
	ldx	[scr2 + state], scr2		/* state mask */	;\
	btst	scr1, scr2			/* set cc */
/* END CSTYLED */

#define	IS_STRAND_ACTIVE(cpup, strand, scr1, scr2) \
	IS_STRAND_(CONFIG_STACTIVE, cpup, strand, scr1, scr2)

#define	IS_STRAND_HALT(cpup, strand, scr1, scr2) \
	IS_STRAND_(CONFIG_STHALT, cpup, strand, scr1, scr2)

#define	IS_STRAND_IDLE(cpup, strand, scr1, scr2) \
	IS_STRAND_(CONFIG_STIDLE, cpup, strand, scr1, scr2)

/* END CSTYLED */

#ifdef __cplusplus
}
#endif

#endif /* _HPRIVREGS_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: hprivregs.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _HPRIVREGS_H
	50	#define _HPRIVREGS_H
	51
	52	#pragma ident "@(#)hprivregs.h 1.20 07/05/03 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	#include <platform/hprivregs.h>
	59
	60	/*
	61	* Niagara %ver
	62	*/
	63	#define VER_MASK_SHIFT 24
	64	#define VER_MASK_MASK 0xff
65	#define VER_MASK_MAJOR_SHIFT (VER_MASK_SHIFT + 4)
66	#define VER_MASK_MAJOR_MASK 0xf
67
68	/*
69	* Hardware-implemented register windows
70	*/
71	#define NWINDOWS 8
72
73	/*
74	* Number of unique interrupts per strand
75	*/
76	#define MAXINTR 64
77
78	/*
79	* Max number of Global levels
80	*/
81	#define MAXGL 3
82
83	/*
84	* hpstate:
85	*
86	* +-----------------------------------------------------+
87	* \| rsvd \| ENB \| rsvd \| RED \| rsvd \| HPRIV \| rsvd \| TLZ \|
88	* +-----------------------------------------------------+
89	* 63..12 11 10..6 5 4..3 2 1 0
90	*/
91
92	#define HPSTATE_TLZ 0x0001
93	#define HPSTATE_HPRIV 0x0004
94	#define HPSTATE_RED 0x0020
95	#define HPSTATE_ENB 0x0800
96
97	/*
98	* htstate:
99	*
100	* +-----------------------------------------+
101	* \| rsvd \| RED \| rsvd \| HPRIV \| rsvd \| TLZ \|
102	* +-----------------------------------------+
103	* 63..6 5 4..3 2 1 0
104	*/
105
106	#define HTSTATE_TLZ 0x0001
107	#define HTSTATE_HPRIV 0x0004
108	#define HTSTATE_RED 0x0010
109	#define HTSTATE_ENB 0x0800
110
111	/*
112	* hstickpending:
113	*
114	* +------------+
115	* \| rsvd \| HSP \|
116	* +------------+
117	* 63..1 0
118	*/
119
120	#define HSTICKPEND_HSP 0x1
121
122	/*
123	* htba:
124	*
125	* +---------------------------+
126	* \| TBA \| TBATL \| rsvd \|
127	* +---------------------------+
128	* 63..15 14 13..0
129	*/
130	#define TBATL 0x4000
131	#define TBATL_SHIFT 14
132
133	/*
134	* TLB demap register bit definitions
135	* (ASI_DMMU_DEMAP/ASI_IMMU_DEMAP)
136	*/
137	#define TLB_R_BIT (0x200)
138	#define TLB_DEMAP_PAGE_TYPE 0x00
139	#define TLB_DEMAP_CTX_TYPE 0x40
140	#define TLB_DEMAP_ALL_TYPE 0x80
141	#define TLB_DEMAP_PRIMARY 0x00
142	#define TLB_DEMAP_SECONDARY 0x10
143	#define TLB_DEMAP_NUCLEUS 0x20
144
145	/*
146	* LSU Control Register
147	*/
148	#define ASI_LSUCR 0x45
149	#define LSUCR_IC 0x000000001 /* I$ enable */
150	#define LSUCR_DC 0x000000002 /* D$ enable */
151	#define LSUCR_IM 0x000000004 /* IMMU enable */
152	#define LSUCR_DM 0x000000008 /* DMMU enable */
153
154	/*
155	* Misc
156	*/
157	#define L2_CTL_REG 0xa900000000
158	#define L2CR_DIS 0x00000001 /* L2$ Disable */
159	#define L2CR_DMMODE 0x00000002 /* L2$ Direct-mapped mode */
160	#define L2CR_SCRUBEN 0x00000004 /* L2$ Hardware scrub enable */
161
162	/*
163	* INT_VEC_DIS constants
164	*/
165	#define INT_VEC_DIS_TYPE_SHIFT 16
166	#define INT_VEC_DIS_VCID_SHIFT 8
167	#define INT_VEC_DIS_TYPE_INT 0x0
168	#define INT_VEC_DIS_TYPE_RESET 0x1
169	#define INT_VEC_DIS_TYPE_IDLE 0x2
170	#define INT_VEC_DIS_TYPE_RESUME 0x3
171	#define INT_VEC_DIS_VECTOR_RESET 0x1
172
173	/* BEGIN CSTYLED */
174	/*
175	* Interrupt Vector Dispatch Macros
176	*/
177	/*
178	* INT_VEC_DSPCH_ONE - interrupt vector dispatch one target
179	*
180	* Sends interrupt TYPE to any strand including the executing one.
181	*
182	* Delay Slot: no
183	*/
184	/* BEGIN CSTYLED */
185	#define INT_VEC_DSPCH_ONE(TYPE, tgt, scr1, scr2) \
186	setx IOBBASE + INT_VEC_DIS, scr1, scr2 ;\
187	set (TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1 ;\
188	sllx tgt, INT_VEC_DIS_VCID_SHIFT, tgt ;\
189	or scr1, tgt, scr1 ;\
190	stx scr1, [scr2]
191	/* END CSTYLED */
192
193	/*
194	* INT_VEC_DSPCH_ALL - interrupt vector dispatch all
195	*
196	* Sends interrupt TYPE to all strands whose bit is set in SRC, excluding
197	* the executing one. SRC and DST bitmasks are updated.
198	*
199	* Delay Slot: no
200	*/
201	/* BEGIN CSTYLED */
202	#define INT_VEC_DSPCH_ALL(TYPE, SRC, DST, scr1, scr2) \
203	.pushlocals ;\
204	rd STR_STATUS_REG, scr2 /* my ID */ ;\
205	srlx scr2, STR_STATUS_CPU_ID_SHIFT, scr2 ;\
206	and scr2, STR_STATUS_CPU_ID_MASK, scr2 ;\
207	mov 1, scr1 ;\
208	sllx scr1, scr2, scr1 /* my bit */ ;\
209	ldx [SRC], scr2 /* Source state */ ;\
210	stx scr1, [SRC] /* new Source */ ;\
211	bclr scr1, scr2 /* clear my bit */ ;\
212	ldx [DST], scr1 /* Destination state */ ;\
213	bset scr2, scr1 /* add new bits */ ;\
214	stx scr1, [DST] /* new To */ ;\
215	setx IOBBASE + INT_VEC_DIS, scr1, DST ;\
216	set (TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1 ;\
217	1: btst 1, scr2 /* valid strand? */ ;\
218	bnz,a,pn %xcc, 2f /* yes: store */ ;\
219	stx scr1, [DST] /* no: annul */ ;\
220	2: srlx scr2, 1, scr2 /* next strand bit */ ;\
221	brnz scr2, 1b /* more to do */ ;\
222	inc 1 << INT_VEC_DIS_VCID_SHIFT, scr1 ;\
223	.poplocals
224	/* END CSTYLED */
225
226	/*
227	* IDLE_ALL_STRAND
228	*
229	* Sends interrupt IDLE to all strands whose bit is set in CONFIG_STACTIVE,
230	* excluding the executing one. CONFIG_STACTIVE, CONFIG_STIDLE are
231	* updated.
232	*
233	* Delay Slot: no
234	*/
235	/* BEGIN CSTYLED */
236	#define IDLE_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
237	ldx [strand + STRAND_CONFIGP], scr1 /* ->config*/ ;\
238	add scr1, CONFIG_STACTIVE, scr3 /* ->active mask */ ;\
239	add scr1, CONFIG_STIDLE, scr4 /* ->idle mask */ ;\
240	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_IDLE, scr3, scr4, scr1, scr2)
241	/* END CSTYLED */
242
243	/* BEGIN CSTYLED */
244	#define RESUME_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
245	ldx [strand + STRAND_CONFIGP], scr1 /* ->config*/ ;\
246	add scr1, CONFIG_STIDLE, scr3 /* ->idle mask */ ;\
247	add scr1, CONFIG_STACTIVE, scr4 /* ->active mask */ ;\
248	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_RESUME, scr3, scr4, scr1, scr2)
249
250	#define IS_STRAND_(state, vcpup, strand, scr1, scr2) \
251	mov 1, scr1 /* bit */ ;\
252	sllx scr1, strand, scr1 /* 1<<strand */ ;\
253	VCPU2ROOT_STRUCT(vcpup, scr2) /* ->config*/ ;\
254	ldx [scr2 + state], scr2 /* state mask */ ;\
255	btst scr1, scr2 /* set cc */
256	/* END CSTYLED */
257
258	#define IS_STRAND_ACTIVE(cpup, strand, scr1, scr2) \
259	IS_STRAND_(CONFIG_STACTIVE, cpup, strand, scr1, scr2)
260
261	#define IS_STRAND_HALT(cpup, strand, scr1, scr2) \
262	IS_STRAND_(CONFIG_STHALT, cpup, strand, scr1, scr2)
263
264	#define IS_STRAND_IDLE(cpup, strand, scr1, scr2) \
265	IS_STRAND_(CONFIG_STIDLE, cpup, strand, scr1, scr2)
266
267	/* END CSTYLED */
268
269	#ifdef __cplusplus
270	}
271	#endif
272
273	#endif /* _HPRIVREGS_H */