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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / common / include / vdev_ops.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: vdev_ops.h
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49#ifndef _VDEV_OPS_H
50#define _VDEV_OPS_H
51
52#pragma ident "@(#)vdev_ops.h 1.7 07/05/03 SMI"
53
54#ifdef __cplusplus
55extern "C" {
56#endif
57
58#include <platform/vdev_ops.h>
59
60#define NULL_iommu_map 0
61#define NULL_iommu_map_v2 0
62#define NULL_iommu_getmap 0
63#define NULL_iommu_getmap_v2 0
64#define NULL_iommu_unmap 0
65#define NULL_iommu_getbypass 0
66#define NULL_config_get 0
67#define NULL_config_put 0
68#define NULL_io_peek 0
69#define NULL_io_poke 0
70#define NULL_dma_sync 0
71#define NULL_devino2vino 0
72#define NULL_mondo_receive 0
73#define NULL_intr_getvalid 0
74#define NULL_intr_setvalid 0
75#define NULL_intr_settarget 0
76#define NULL_intr_gettarget 0
77#define NULL_intr_getstate 0
78#define NULL_intr_setstate 0
79#define NULL_vintr_getcookie 0
80#define NULL_vintr_setcookie 0
81#define NULL_vintr_getvalid 0
82#define NULL_vintr_setvalid 0
83#define NULL_vintr_gettarget 0
84#define NULL_vintr_settarget 0
85#define NULL_vintr_getstate 0
86#define NULL_vintr_setstate 0
87#define NULL_msiq_conf 0
88#define NULL_msiq_info 0
89#define NULL_msiq_getvalid 0
90#define NULL_msiq_setvalid 0
91#define NULL_msiq_getstate 0
92#define NULL_msiq_setstate 0
93#define NULL_msiq_gethead 0
94#define NULL_msiq_sethead 0
95#define NULL_msiq_gettail 0
96#define NULL_msi_getvalid 0
97#define NULL_msi_setvalid 0
98#define NULL_msi_getstate 0
99#define NULL_msi_setstate 0
100#define NULL_msi_getmsiq 0
101#define NULL_msi_setmsiq 0
102#define NULL_msi_msg_getmsiq 0
103#define NULL_msi_msg_setmsiq 0
104#define NULL_msi_msg_getvalid 0
105#define NULL_msi_msg_setvalid 0
106#define NULL_get_perf_reg 0
107#define NULL_set_perf_reg 0
108
109#define INTR_OPS(device) \
110 .devino2vino = device##_devino2vino
111
112#define MONDO_OPS(device) \
113 .mondo_receive = device##_mondo_receive
114
115#define PERF_OPS(device) \
116 .getperfreg = device##_get_perf_reg, \
117 .setperfreg = device##_set_perf_reg
118
119#define VINO_OPS(device) \
120 .getvalid = device##_intr_getvalid, \
121 .setvalid = device##_intr_setvalid, \
122 .getstate = device##_intr_getstate, \
123 .setstate = device##_intr_setstate, \
124 .gettarget = device##_intr_gettarget, \
125 .settarget = device##_intr_settarget
126
127#define VINTR_OPS(device) \
128 .vgetcookie = device##_vintr_getcookie, \
129 .vsetcookie = device##_vintr_setcookie, \
130 .vgetvalid = device##_vintr_getvalid, \
131 .vsetvalid = device##_vintr_setvalid, \
132 .vgettarget = device##_vintr_gettarget, \
133 .vsettarget = device##_vintr_settarget, \
134 .vgetstate = device##_vintr_getstate, \
135 .vsetstate = device##_vintr_setstate
136
137#define VPCI_OPS(bridge) \
138 .map = bridge##_iommu_map, \
139 .getmap = bridge##_iommu_getmap, \
140 .map_v2 = bridge##_iommu_map_v2, \
141 .getmap_v2 = bridge##_iommu_getmap_v2, \
142 .unmap = bridge##_iommu_unmap, \
143 .getbypass = bridge##_iommu_getbypass, \
144 .configget = bridge##_config_get, \
145 .configput = bridge##_config_put, \
146 .peek = bridge##_io_peek, \
147 .poke = bridge##_io_poke, \
148 .dmasync = bridge##_dma_sync
149
150#define MSI_OPS(bridge) \
151 .msiq_conf = bridge##_msiq_conf, \
152 .msiq_info = bridge##_msiq_info, \
153 .msiq_getvalid = bridge##_msiq_getvalid, \
154 .msiq_setvalid = bridge##_msiq_setvalid, \
155 .msiq_getstate = bridge##_msiq_getstate, \
156 .msiq_setstate = bridge##_msiq_setstate, \
157 .msiq_gethead = bridge##_msiq_gethead, \
158 .msiq_sethead = bridge##_msiq_sethead, \
159 .msiq_gettail = bridge##_msiq_gettail, \
160 .msi_getvalid = bridge##_msi_getvalid, \
161 .msi_setvalid = bridge##_msi_setvalid, \
162 .msi_getstate = bridge##_msi_getstate, \
163 .msi_setstate = bridge##_msi_setstate, \
164 .msi_getmsiq = bridge##_msi_getmsiq, \
165 .msi_setmsiq = bridge##_msi_setmsiq, \
166 .msi_msg_getmsiq = bridge##_msi_msg_getmsiq, \
167 .msi_msg_setmsiq = bridge##_msi_msg_setmsiq, \
168 .msi_msg_getvalid = bridge##_msi_msg_getvalid, \
169 .msi_msg_setvalid = bridge##_msi_msg_setvalid
170
171/*
172 * "null" nexus
173 */
174#define NULL_DEV_OPS \
175 INTR_OPS(NULL), VINO_OPS(NULL), VPCI_OPS(NULL), \
176 MSI_OPS(NULL), PERF_OPS(NULL), VINTR_OPS(NULL)
177
178
179/*
180 * Virtual device (vdev) nexus
181 */
182#define VINO_HANDLER_VDEV \
183 DEVOPS_VDEV, DEVOPS_VDEV, /* 00 - 01 */ \
184 DEVOPS_VDEV, DEVOPS_VDEV, /* 02 - 03 */ \
185 DEVOPS_VDEV, DEVOPS_VDEV, /* 04 - 05 */ \
186 DEVOPS_VDEV, DEVOPS_VDEV, /* 06 - 07 */ \
187 DEVOPS_VDEV, DEVOPS_VDEV, /* 08 - 09 */ \
188 DEVOPS_VDEV, DEVOPS_VDEV, /* 10 - 11 */ \
189 DEVOPS_VDEV, DEVOPS_VDEV, /* 12 - 13 */ \
190 DEVOPS_VDEV, DEVOPS_VDEV, /* 14 - 15 */ \
191 DEVOPS_VDEV, DEVOPS_VDEV, /* 16 - 17 */ \
192 DEVOPS_VDEV, DEVOPS_VDEV, /* 18 - 19 */ \
193 DEVOPS_VDEV, DEVOPS_VDEV, /* 20 - 21 */ \
194 DEVOPS_VDEV, DEVOPS_VDEV, /* 22 - 23 */ \
195 DEVOPS_VDEV, DEVOPS_VDEV, /* 24 - 25 */ \
196 DEVOPS_VDEV, DEVOPS_VDEV, /* 26 - 27 */ \
197 DEVOPS_VDEV, DEVOPS_VDEV, /* 28 - 29 */ \
198 DEVOPS_VDEV, DEVOPS_VDEV, /* 30 - 31 */ \
199 DEVOPS_VDEV, DEVOPS_VDEV, /* 32 - 33 */ \
200 DEVOPS_VDEV, DEVOPS_VDEV, /* 34 - 35 */ \
201 DEVOPS_VDEV, DEVOPS_VDEV, /* 36 - 37 */ \
202 DEVOPS_VDEV, DEVOPS_VDEV, /* 38 - 39 */ \
203 DEVOPS_VDEV, DEVOPS_VDEV, /* 40 - 41 */ \
204 DEVOPS_VDEV, DEVOPS_VDEV, /* 42 - 33 */ \
205 DEVOPS_VDEV, DEVOPS_VDEV, /* 44 - 45 */ \
206 DEVOPS_VDEV, DEVOPS_VDEV, /* 46 - 47 */ \
207 DEVOPS_VDEV, DEVOPS_VDEV, /* 48 - 49 */ \
208 DEVOPS_VDEV, DEVOPS_VDEV, /* 50 - 51 */ \
209 DEVOPS_VDEV, DEVOPS_VDEV, /* 52 - 53 */ \
210 DEVOPS_VDEV, DEVOPS_VDEV, /* 54 - 55 */ \
211 DEVOPS_VDEV, DEVOPS_VDEV, /* 56 - 57 */ \
212 DEVOPS_VDEV, DEVOPS_VDEV, /* 58 - 59 */ \
213 DEVOPS_VDEV, DEVOPS_VDEV, /* 60 - 61 */ \
214 DEVOPS_VDEV, DEVOPS_VDEV /* 62 - 63 */
215
216#define VDEV_OPS \
217 INTR_OPS(vdev), MONDO_OPS(NULL), VINO_OPS(vdev), \
218 VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL), VINTR_OPS(NULL)
219
220
221/*
222 * LDom Channel nexus
223 */
224#define VINO_HANDLER_CDEV \
225 DEVOPS_CDEV, DEVOPS_CDEV, /* 00 - 01 */ \
226 DEVOPS_CDEV, DEVOPS_CDEV, /* 02 - 03 */ \
227 DEVOPS_CDEV, DEVOPS_CDEV, /* 04 - 05 */ \
228 DEVOPS_CDEV, DEVOPS_CDEV, /* 06 - 07 */ \
229 DEVOPS_CDEV, DEVOPS_CDEV, /* 08 - 09 */ \
230 DEVOPS_CDEV, DEVOPS_CDEV, /* 10 - 11 */ \
231 DEVOPS_CDEV, DEVOPS_CDEV, /* 12 - 13 */ \
232 DEVOPS_CDEV, DEVOPS_CDEV, /* 14 - 15 */ \
233 DEVOPS_CDEV, DEVOPS_CDEV, /* 16 - 17 */ \
234 DEVOPS_CDEV, DEVOPS_CDEV, /* 18 - 19 */ \
235 DEVOPS_CDEV, DEVOPS_CDEV, /* 20 - 21 */ \
236 DEVOPS_CDEV, DEVOPS_CDEV, /* 22 - 23 */ \
237 DEVOPS_CDEV, DEVOPS_CDEV, /* 24 - 25 */ \
238 DEVOPS_CDEV, DEVOPS_CDEV, /* 26 - 27 */ \
239 DEVOPS_CDEV, DEVOPS_CDEV, /* 28 - 29 */ \
240 DEVOPS_CDEV, DEVOPS_CDEV, /* 30 - 31 */ \
241 DEVOPS_CDEV, DEVOPS_CDEV, /* 32 - 33 */ \
242 DEVOPS_CDEV, DEVOPS_CDEV, /* 34 - 35 */ \
243 DEVOPS_CDEV, DEVOPS_CDEV, /* 36 - 37 */ \
244 DEVOPS_CDEV, DEVOPS_CDEV, /* 38 - 39 */ \
245 DEVOPS_CDEV, DEVOPS_CDEV, /* 40 - 41 */ \
246 DEVOPS_CDEV, DEVOPS_CDEV, /* 42 - 33 */ \
247 DEVOPS_CDEV, DEVOPS_CDEV, /* 44 - 45 */ \
248 DEVOPS_CDEV, DEVOPS_CDEV, /* 46 - 47 */ \
249 DEVOPS_CDEV, DEVOPS_CDEV, /* 48 - 49 */ \
250 DEVOPS_CDEV, DEVOPS_CDEV, /* 50 - 51 */ \
251 DEVOPS_CDEV, DEVOPS_CDEV, /* 52 - 53 */ \
252 DEVOPS_CDEV, DEVOPS_CDEV, /* 54 - 55 */ \
253 DEVOPS_CDEV, DEVOPS_CDEV, /* 56 - 57 */ \
254 DEVOPS_CDEV, DEVOPS_CDEV, /* 58 - 59 */ \
255 DEVOPS_CDEV, DEVOPS_CDEV, /* 60 - 61 */ \
256 DEVOPS_CDEV, DEVOPS_CDEV /* 62 - 63 */
257
258#define CDEV_OPS \
259 INTR_OPS(NULL), MONDO_OPS(NULL), VINO_OPS(NULL), \
260 VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL), VINTR_OPS(ldc)
261
262
263
264#ifndef _ASM
265
266typedef struct devopsvec devopsvec_t;
267struct devopsvec {
268 void (*devino2vino)();
269
270 void (*mondo_receive)();
271 void (*getvalid)();
272 void (*setvalid)();
273 void (*getstate)();
274 void (*setstate)();
275 void (*gettarget)();
276 void (*settarget)();
277
278 void (*map)();
279 void (*map_v2)();
280 void (*getmap)();
281 void (*getmap_v2)();
282 void (*unmap)();
283 void (*getbypass)();
284 void (*configget)();
285 void (*configput)();
286 void (*peek)();
287 void (*poke)();
288 void (*dmasync)();
289 void (*msiq_conf)();
290 void (*msiq_info)();
291 void (*msiq_getvalid)();
292 void (*msiq_setvalid)();
293 void (*msiq_getstate)();
294 void (*msiq_setstate)();
295 void (*msiq_gethead)();
296 void (*msiq_sethead)();
297 void (*msiq_gettail)();
298 void (*msi_getvalid)();
299 void (*msi_setvalid)();
300 void (*msi_getstate)();
301 void (*msi_setstate)();
302 void (*msi_getmsiq)();
303 void (*msi_setmsiq)();
304 void (*msi_msg_getmsiq)();
305 void (*msi_msg_setmsiq)();
306 void (*msi_msg_getvalid)();
307 void (*msi_msg_setvalid)();
308
309 void (*getperfreg)();
310 void (*setperfreg)();
311
312 void (*vgetcookie)();
313 void (*vsetcookie)();
314 void (*vgetvalid)();
315 void (*vsetvalid)();
316 void (*vgettarget)();
317 void (*vsettarget)();
318 void (*vgetstate)();
319 void (*vsetstate)();
320};
321
322#endif /* !_ASM */
323
324#ifdef __cplusplus
325}
326#endif
327
328#endif /* _VDEV_OPS_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.