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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / common / src / vpci_msi.s
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920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: vpci_msi.s
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49 .ident "@(#)vpci_msi.s 1.5 07/07/17 SMI"
50
51 .file "vpci_msi.s"
52
53/*
54 * VPCI MSI hcalls
55 */
56
57#include <sys/asm_linkage.h>
58#include <hypervisor.h>
59#include <sparcv9/misc.h>
60#include <sun4v/vpci.h>
61#include <asi.h>
62#include <hprivregs.h>
63#include <vdev_intr.h>
64#include <offsets.h>
65#include <guest.h>
66#include <util.h>
67
68
69/*
70 * msiq_conf
71 *
72 * arg0 dev config pa (%o0)
73 * arg1 MSI EQ id (%o1)
74 * arg2 EQ base RA (%o2)
75 * arg3 #entries (%o3)
76 * --
77 * ret0 status (%o0)
78 */
79 ENTRY_NP(hcall_msiq_conf)
80 /* XXX validate RA (arg2) + size (arg3) here */
81 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_CONF, %g1, %g2,
82 %g3, herr_inval)
83 SET_SIZE(hcall_msiq_conf)
84
85
86/*
87 * msiq_info
88 *
89 * arg0 dev config pa (%o0)
90 * arg1 MSI EQ id (%o1)
91 * --
92 * ret0 status (%o0)
93 * ret1 ra (%o1)
94 * ret2 #entries (%o2)
95 */
96 ENTRY_NP(hcall_msiq_info)
97 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_INFO, %g1, %g2,
98 %g3, herr_inval)
99 SET_SIZE(hcall_msiq_info)
100
101
102/*
103 * msiq_getvalid
104 *
105 * arg0 dev config pa (%o0)
106 * arg1 MSI EQ id (%o1)
107 * --
108 * ret0 status (%o0)
109 * ret1 EQ valid (0: Invalid 1: Valid) (%o1)
110 */
111 ENTRY_NP(hcall_msiq_getvalid)
112 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_GETVALID, %g1, %g2,
113 %g3, herr_inval)
114 SET_SIZE(hcall_msiq_getvalid)
115
116
117/*
118 * msiq_setvalid
119 *
120 * arg0 dev config pa (%o0)
121 * arg1 MSI EQ id (%o1)
122 * arg2 EQ valid (0: Invalid 1: Valid) (%o2)
123 * --
124 * ret0 status (%o0)
125 */
126 ENTRY_NP(hcall_msiq_setvalid)
127 cmp %o2, INTR_ENABLED_MAX_VALUE
128 bgu,pn %xcc, herr_inval
129 nop
130 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_SETVALID, %g1, %g2,
131 %g3, herr_inval)
132 SET_SIZE(hcall_msiq_setvalid)
133
134
135/*
136 * msiq_getstate
137 *
138 * arg0 dev config pa (%o0)
139 * arg1 MSI EQ id (%o1)
140 * --
141 * ret0 status (%o0)
142 * ret1 EQ state (0: Idle 1: Error) (%o1)
143 */
144 ENTRY_NP(hcall_msiq_getstate)
145 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_GETSTATE, %g1, %g2,
146 %g3, herr_inval)
147 SET_SIZE(hcall_msiq_getstate)
148
149
150/*
151 * msiq_setstate
152 *
153 * arg0 dev config pa (%o0)
154 * arg1 MSI EQ id (%o1)
155 * arg2 EQ state (0: Idle 1: Error) (%o2)
156 * --
157 * ret0 status (%o0)
158 */
159 ENTRY_NP(hcall_msiq_setstate)
160 cmp %o2, HVIO_MSIQSTATE_MAX_VALUE
161 bgu,pn %xcc, herr_inval
162 nop
163 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_SETSTATE, %g1, %g2,
164 %g3, herr_inval)
165 SET_SIZE(hcall_msiq_setstate)
166
167
168/*
169 * msiq_gethead
170 *
171 * arg0 dev config pa (%o0)
172 * arg1 MSI EQ id (%o1)
173 * --
174 * ret0 status (%o0)
175 * ret1 head index (%o1)
176 */
177 ENTRY_NP(hcall_msiq_gethead)
178 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_GETHEAD, %g1, %g2,
179 %g3, herr_inval)
180 SET_SIZE(hcall_msiq_gethead)
181
182/*
183 * msiq_sethead
184 *
185 * arg0 dev config pa (%o0)
186 * arg1 MSI EQ id (%o1)
187 * arg2 head offset (%o2)
188 * --
189 * ret0 status (%o0)
190 */
191 ENTRY_NP(hcall_msiq_sethead)
192 btst MSIEQ_REC_SIZE_MASK, %o2
193 bnz,pn %xcc, herr_inval
194 nop
195 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_SETHEAD, %g1, %g2,
196 %g3, herr_inval)
197 SET_SIZE(hcall_msiq_sethead)
198
199
200/*
201 * msiq_gettail
202 *
203 * arg0 dev config pa (%o0)
204 * arg1 MSI EQ id (%o1)
205 * --
206 * ret0 status (%o0)
207 * ret1 tail index (%o1)
208 */
209 ENTRY_NP(hcall_msiq_gettail)
210 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSIQ_GETTAIL, %g1, %g2,
211 %g3, herr_inval)
212 SET_SIZE(hcall_msiq_gettail)
213
214
215/*
216 * msi_getvalid
217 *
218 * arg0 dev config pa (%o0)
219 * arg1 MSI number (%o1)
220 * --
221 * ret0 status (%o0)
222 * ret1 MSI status (0: Invalid 1: Valid) (%o1)
223 */
224 ENTRY_NP(hcall_msi_getvalid)
225 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_GETVALID, %g1, %g2,
226 %g3, herr_inval)
227 SET_SIZE(hcall_msi_getvalid)
228
229
230/*
231 * msi_setvalid
232 *
233 * arg0 dev config pa (%o0)
234 * arg1 MSI number (%o1)
235 * arg2 MSI status (0: Invalid 1: Valid) (%o2)
236 * --
237 * ret0 status (%o0)
238 */
239 ENTRY_NP(hcall_msi_setvalid)
240 cmp %o2, HVIO_MSI_VALID_MAX_VALUE
241 bgu,pn %xcc, herr_inval
242 nop
243 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_SETVALID, %g1, %g2,
244 %g3, herr_inval)
245 SET_SIZE(hcall_msi_setvalid)
246
247
248/*
249 * msi_getstate
250 *
251 * arg0 dev config pa (%o0)
252 * arg1 MSI number (%o1)
253 * --
254 * ret0 status (%o0)
255 * ret1 MSI state (0: Idle 1: Delivered) (%o1)
256 */
257 ENTRY_NP(hcall_msi_getstate)
258 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_GETSTATE, %g1, %g2,
259 %g3, herr_inval)
260 SET_SIZE(hcall_msi_getstate)
261
262
263/*
264 * msi_setstate
265 *
266 * arg0 dev config pa (%o0)
267 * arg1 MSI number (%o1)
268 * arg2 MSI state (0: Idle) (%o2)
269 * --
270 * ret0 status (%o0)
271 */
272 ENTRY_NP(hcall_msi_setstate)
273 /* XXX only idle or is that just fire? bounds-check here */
274 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_SETSTATE, %g1, %g2,
275 %g3, herr_inval)
276 SET_SIZE(hcall_msi_setstate)
277
278
279/*
280 * msi_getmsiq
281 *
282 * arg0 dev config pa (%o0)
283 * arg1 MSI number (%o1)
284 * --
285 * ret0 status (%o0)
286 * ret1 MSI EQ id (%o1)
287 */
288 ENTRY_NP(hcall_msi_getmsiq)
289 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_GETMSIQ, %g1, %g2,
290 %g3, herr_inval)
291 SET_SIZE(hcall_msi_getmsiq)
292
293
294/*
295 * msi_setmsiq
296 *
297 * arg0 dev config pa (%o0)
298 * arg1 MSI number (%o1)
299 * arg2 MSI EQ id (%o2)
300 * arg3 MSI type (MSI32=0 MSI64=1) (%o3)
301 * --
302 * ret0 status (%o0)
303 */
304 ENTRY_NP(hcall_msi_setmsiq)
305 cmp %o3, MSIQTYPE_MAX_VALUE
306 bgu,pn %xcc, herr_inval
307 nop
308 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_SETMSIQ, %g1, %g2,
309 %g3, herr_inval)
310 SET_SIZE(hcall_msi_setmsiq)
311
312
313/*
314 * msi_msg_getmsiq
315 *
316 * arg0 dev config pa (%o0)
317 * arg1 MSI msg type (%o1)
318 * --
319 * ret0 status (%o0)
320 * ret1 MSI EQ id (%o1)
321 */
322 ENTRY_NP(hcall_msi_msg_getmsiq)
323 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_MSG_GETMSIQ, %g1, %g2,
324 %g3, herr_inval)
325 SET_SIZE(hcall_msi_msg_getmsiq)
326
327
328/*
329 * msi_msg_setmsiq
330 *
331 * arg0 dev config pa (%o0)
332 * arg1 MSI msg type (%o1)
333 * arg2 MSI EQ id (%o2)
334 * --
335 * ret0 status (%o0)
336 */
337
338 ENTRY_NP(hcall_msi_msg_setmsiq)
339 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_MSG_SETMSIQ, %g1, %g2,
340 %g3, herr_inval)
341 SET_SIZE(hcall_msi_msg_setmsiq)
342
343
344/*
345 * msi_msg_getvalid
346 *
347 * arg0 dev config pa (%o0)
348 * arg1 MSI msg type (%o1)
349 * --
350 * ret0 status (%o0)
351 * ret1 MSI msg valid state (%o1)
352 */
353 ENTRY_NP(hcall_msi_msg_getvalid)
354 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_MSG_GETVALID, %g1, %g2,
355 %g3, herr_inval)
356 SET_SIZE(hcall_msi_msg_getvalid)
357
358
359/*
360 * msi_msg_setvalid
361 *
362 * arg0 dev config pa (%o0)
363 * arg1 MSI msg type (%o1)
364 * arg2 MSI msg valid state (%o2)
365 * --
366 * ret0 status (%o0)
367 */
368 ENTRY_NP(hcall_msi_msg_setvalid)
369 cmp %o2, HVIO_PCIE_MSG_VALID_MAX_VALUE
370 bgu,pn %xcc, herr_inval
371 nop
372 JMPL_DEVHANDLE2DEVOP(%o0, DEVOPSVEC_MSI_MSG_SETVALID, %g1, %g2,
373 %g3, herr_inval)
374 SET_SIZE(hcall_msi_msg_setvalid)
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.