[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / cmp.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: cmp.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _NIAGARA2_CMP_H
#define	_NIAGARA2_CMP_H

#pragma ident	"@(#)cmp.h	1.2	07/07/27 SMI"

#ifdef __cplusplus
extern "C" {
#endif

#include "config.h"

/*
 * Idle/Resume all strands
 */
/* BEGIN CSTYLED */

#define SPINLOCK_ENTER_SS_LOCK(scr1, scr2, scr3) 		\
	LOCK_ADDR(CONFIG_SINGLE_STRAND_LOCK, scr1)	/* ->lock */	;\
	SPINLOCK_ENTER(scr1, scr2, scr3)

#define SPINLOCK_EXIT_SS_LOCK(scr1) 				\
	LOCK_ADDR(CONFIG_SINGLE_STRAND_LOCK, scr1)	/* ->lock */	;\
	SPINLOCK_EXIT(scr1)

/*
 * ASI_CMT_STRAND_ID (ASI 0x63, VA 0x10) bits[5:0]
 */
#define	CMT_STRAND_ID_MASK			0x3f

#define	PHYS_STRAND_ID(scr)						\
	mov	CMP_CORE_ID, scr					;\
	ldxa	[scr]ASI_CMP_CORE, scr	/* current cpu */		;\
	and	scr, CMT_STRAND_ID_MASK, scr

#define	PARK_ALL_STRANDS(scr1, scr2, scr3, scr4)			\
	.pushlocals							;\
	SPINLOCK_ENTER_SS_LOCK(scr1, scr2, scr3)			;\
	mov	CMP_CORE_ID, scr2					;\
	ldxa	[scr2]ASI_CMP_CORE, scr2	/* current cpu */	;\
	and	scr2, (NSTRANDS - 1), scr2				;\
	mov	1, scr3							;\
        sllx    scr3, scr2, scr3					;\
	VCPU_STRUCT(scr1)						;\
	VCPU2ROOT_STRUCT(scr1, scr2)		/* ->config*/		;\
	add     scr2, CONFIG_STACTIVE, scr4	/* ->active mask */	;\
	ldx	[scr4], scr1			/* active CPUs */	;\
	andn	scr1, scr3, scr1					;\
	stx	scr3, [scr4]			/* curcpu ACTIVE */	;\
	add	scr2, CONFIG_STIDLE, scr2	/* ->idle mask */	;\
	stx	scr1, [scr2]						;\
	mov	CMP_CORE_RUNNING_W1C, scr2				;\
	stxa	scr1, [scr2]ASI_CMP_CHIP	/* park all cpus */	;\
	mov	CMP_CORE_RUNNING_STATUS, scr2				;\
1:	ldxa	[scr2]ASI_CMP_CHIP, scr1				;\
	cmp	scr1, scr3						;\
	bne,pn	%xcc, 1b		/* wait until stopped */	;\
	nop								;\
	SPINLOCK_EXIT_SS_LOCK(scr1)					;\
	.poplocals
/* END CSTYLED */

/*
 * Resume all strands
 */
/* BEGIN CSTYLED */
#define	RESUME_ALL_STRANDS(scr1, scr2, scr3, scr4)			\
	.pushlocals							;\
	SPINLOCK_ENTER_SS_LOCK(scr1, scr2, scr3)			;\
	mov	CMP_CORE_ID, scr2					;\
	ldxa	[scr2]ASI_CMP_CORE, scr2	/* current cpu */	;\
	and	scr2, (NSTRANDS - 1), scr2				;\
	mov	1, scr3							;\
        sllx    scr3, scr2, scr3					;\
	VCPU_STRUCT(scr1)						;\
	VCPU2ROOT_STRUCT(scr1, scr2)		/* ->config*/		;\
	add     scr2, CONFIG_STIDLE, scr4	/* ->idle mask */	;\
	ldx	[scr4], scr1						;\
	stx	%g0, [scr4]			/* no idle CPUs */	;\
	add	scr2, CONFIG_STACTIVE, scr4	/* ->active mask */	;\
	ldx	[scr4], scr2			/* current active */	;\
	or	scr3, scr2, scr3		/* active + curcpu */	;\
	or	scr1, scr3, scr1		/* + idle */		;\
	stx	scr1, [scr4]			/* all active */	;\
	mov	CMP_CORE_RUNNING_W1S, scr2				;\
	stxa	scr1, [scr2]ASI_CMP_CHIP	/* start all cpus */	;\
	mov	CMP_CORE_RUNNING_STATUS, scr2				;\
1:	ldxa	[scr2]ASI_CMP_CHIP, scr3				;\
	cmp	scr1, scr3						;\
	bne,pn	%xcc, 1b		/* wait until started */	;\
	nop								;\
	SPINLOCK_EXIT_SS_LOCK(scr1)					;\
	.poplocals
/* END CSTYLED */

#define	halt		.word	0xbd980000	/* wrhpr	%g0, %hpreg30 */
#define	read_halt	.word	0x814f8000	/* rdhpr	%hpreg30, %g0 */

#ifdef	SUPPORT_NIAGARA2_1x

/*
 * Niagara2 1.x: Try to slow down the progress of this thread by
 * performing long-latency loads.  Furthermore, spread out the loads
 * to different queueing FIFOs by core number.
 */
/* BEGIN CSTYLED */
#ifndef	DEBUG_LEGION			

#define	READ_REGS_FOR_HALT(paddr)			\
	ldx	[paddr], %g0	/* read paddr */	;\
	ldx	[paddr], %g0	/* read paddr */	;\
	ldx	[paddr], %g0	/* read paddr */	;\
	ldx	[paddr], %g0	/* read paddr */	;\
	ldx	[paddr], %g0	/* read paddr */	;\
	ldx	[paddr], %g0	/* read paddr */	;\
	ldx	[paddr], %g0	/* read paddr */	;\
	ldx	[paddr], %g0	/* read paddr */
#else

#define	READ_REGS_FOR_HALT(paddr)				\
	nop

#endif /* !DEBUG_LEGION */

#define	HALT_STRAND_NIAGARA2_1x()				\
	.pushlocals						;\
	setx	niagara2_cpu_yield_paddr_table, %g1, %g4	;\
	RELOC_OFFSET(%g2, %g1)					;\
	sub	%g4, %g1, %g1 /* %g1 table base */		;\
	mov	CMP_CORE_ID, %g3				;\
	ldxa	[%g3]ASI_CMP_CORE, %g3				;\
	and	%g3, NSTRANDS_PER_CORE_MASK, %g3		;\
	sllx	%g3, 3, %g3 /* %g3 offset into table */		;\
	add	%g1, %g3, %g1 /* %g1 addr of table entry */	;\
	ldx	[%g1], %g2 /* %g2 reg paddr */			;\
	READ_REGS_FOR_HALT(%g2)					;\
	.poplocals
#endif

/*
 * Niagara2 > 1.x: use the "halt" instruction.
 */
#define	HALT_STRAND_NIAGARA2()					\
	halt


#ifdef SUPPORT_NIAGARA2_1x
#define	HALT_STRAND()					\
	.pushlocals						;\
	rdhpr   %hver, %g1				;\
	srlx    %g1, VER_MASK_MAJOR_SHIFT, %g1		;\
	and     %g1, VER_MASK_MAJOR_MASK, %g1		;\
	cmp     %g1, 1	/* Check for Niagara2 1.x */	;\
	bleu,pt %xcc, 8f				;\
	nop						;\
	halt						;\
	ba	%xcc, 9f				;\
	nop						;\
8:							;\
	HALT_STRAND_NIAGARA2_1x()			;\
9:							;\
	.poplocals
#else
#define	HALT_STRAND	HALT_STRAND_NIAGARA2
#endif

/* END CSTYLED */

#ifdef __cplusplus
}
#endif

#endif /* _NIAGARA2_CMP_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: cmp.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _NIAGARA2_CMP_H
	50	#define _NIAGARA2_CMP_H
	51
	52	#pragma ident "@(#)cmp.h 1.2 07/07/27 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	#include "config.h"
	59
	60	/*
	61	* Idle/Resume all strands
	62	*/
	63	/* BEGIN CSTYLED */
	64
65	#define SPINLOCK_ENTER_SS_LOCK(scr1, scr2, scr3) \
66	LOCK_ADDR(CONFIG_SINGLE_STRAND_LOCK, scr1) /* ->lock */ ;\
67	SPINLOCK_ENTER(scr1, scr2, scr3)
68
69	#define SPINLOCK_EXIT_SS_LOCK(scr1) \
70	LOCK_ADDR(CONFIG_SINGLE_STRAND_LOCK, scr1) /* ->lock */ ;\
71	SPINLOCK_EXIT(scr1)
72
73	/*
74	* ASI_CMT_STRAND_ID (ASI 0x63, VA 0x10) bits[5:0]
75	*/
76	#define CMT_STRAND_ID_MASK 0x3f
77
78	#define PHYS_STRAND_ID(scr) \
79	mov CMP_CORE_ID, scr ;\
80	ldxa [scr]ASI_CMP_CORE, scr /* current cpu */ ;\
81	and scr, CMT_STRAND_ID_MASK, scr
82
83	#define PARK_ALL_STRANDS(scr1, scr2, scr3, scr4) \
84	.pushlocals ;\
85	SPINLOCK_ENTER_SS_LOCK(scr1, scr2, scr3) ;\
86	mov CMP_CORE_ID, scr2 ;\
87	ldxa [scr2]ASI_CMP_CORE, scr2 /* current cpu */ ;\
88	and scr2, (NSTRANDS - 1), scr2 ;\
89	mov 1, scr3 ;\
90	sllx scr3, scr2, scr3 ;\
91	VCPU_STRUCT(scr1) ;\
92	VCPU2ROOT_STRUCT(scr1, scr2) /* ->config*/ ;\
93	add scr2, CONFIG_STACTIVE, scr4 /* ->active mask */ ;\
94	ldx [scr4], scr1 /* active CPUs */ ;\
95	andn scr1, scr3, scr1 ;\
96	stx scr3, [scr4] /* curcpu ACTIVE */ ;\
97	add scr2, CONFIG_STIDLE, scr2 /* ->idle mask */ ;\
98	stx scr1, [scr2] ;\
99	mov CMP_CORE_RUNNING_W1C, scr2 ;\
100	stxa scr1, [scr2]ASI_CMP_CHIP /* park all cpus */ ;\
101	mov CMP_CORE_RUNNING_STATUS, scr2 ;\
102	1: ldxa [scr2]ASI_CMP_CHIP, scr1 ;\
103	cmp scr1, scr3 ;\
104	bne,pn %xcc, 1b /* wait until stopped */ ;\
105	nop ;\
106	SPINLOCK_EXIT_SS_LOCK(scr1) ;\
107	.poplocals
108	/* END CSTYLED */
109
110	/*
111	* Resume all strands
112	*/
113	/* BEGIN CSTYLED */
114	#define RESUME_ALL_STRANDS(scr1, scr2, scr3, scr4) \
115	.pushlocals ;\
116	SPINLOCK_ENTER_SS_LOCK(scr1, scr2, scr3) ;\
117	mov CMP_CORE_ID, scr2 ;\
118	ldxa [scr2]ASI_CMP_CORE, scr2 /* current cpu */ ;\
119	and scr2, (NSTRANDS - 1), scr2 ;\
120	mov 1, scr3 ;\
121	sllx scr3, scr2, scr3 ;\
122	VCPU_STRUCT(scr1) ;\
123	VCPU2ROOT_STRUCT(scr1, scr2) /* ->config*/ ;\
124	add scr2, CONFIG_STIDLE, scr4 /* ->idle mask */ ;\
125	ldx [scr4], scr1 ;\
126	stx %g0, [scr4] /* no idle CPUs */ ;\
127	add scr2, CONFIG_STACTIVE, scr4 /* ->active mask */ ;\
128	ldx [scr4], scr2 /* current active */ ;\
129	or scr3, scr2, scr3 /* active + curcpu */ ;\
130	or scr1, scr3, scr1 /* + idle */ ;\
131	stx scr1, [scr4] /* all active */ ;\
132	mov CMP_CORE_RUNNING_W1S, scr2 ;\
133	stxa scr1, [scr2]ASI_CMP_CHIP /* start all cpus */ ;\
134	mov CMP_CORE_RUNNING_STATUS, scr2 ;\
135	1: ldxa [scr2]ASI_CMP_CHIP, scr3 ;\
136	cmp scr1, scr3 ;\
137	bne,pn %xcc, 1b /* wait until started */ ;\
138	nop ;\
139	SPINLOCK_EXIT_SS_LOCK(scr1) ;\
140	.poplocals
141	/* END CSTYLED */
142
143	#define halt .word 0xbd980000 /* wrhpr %g0, %hpreg30 */
144	#define read_halt .word 0x814f8000 /* rdhpr %hpreg30, %g0 */
145
146	#ifdef SUPPORT_NIAGARA2_1x
147
148	/*
149	* Niagara2 1.x: Try to slow down the progress of this thread by
150	* performing long-latency loads. Furthermore, spread out the loads
151	* to different queueing FIFOs by core number.
152	*/
153	/* BEGIN CSTYLED */
154	#ifndef DEBUG_LEGION
155
156	#define READ_REGS_FOR_HALT(paddr) \
157	ldx [paddr], %g0 /* read paddr */ ;\
158	ldx [paddr], %g0 /* read paddr */ ;\
159	ldx [paddr], %g0 /* read paddr */ ;\
160	ldx [paddr], %g0 /* read paddr */ ;\
161	ldx [paddr], %g0 /* read paddr */ ;\
162	ldx [paddr], %g0 /* read paddr */ ;\
163	ldx [paddr], %g0 /* read paddr */ ;\
164	ldx [paddr], %g0 /* read paddr */
165	#else
166
167	#define READ_REGS_FOR_HALT(paddr) \
168	nop
169
170	#endif /* !DEBUG_LEGION */
171
172	#define HALT_STRAND_NIAGARA2_1x() \
173	.pushlocals ;\
174	setx niagara2_cpu_yield_paddr_table, %g1, %g4 ;\
175	RELOC_OFFSET(%g2, %g1) ;\
176	sub %g4, %g1, %g1 /* %g1 table base */ ;\
177	mov CMP_CORE_ID, %g3 ;\
178	ldxa [%g3]ASI_CMP_CORE, %g3 ;\
179	and %g3, NSTRANDS_PER_CORE_MASK, %g3 ;\
180	sllx %g3, 3, %g3 /* %g3 offset into table */ ;\
181	add %g1, %g3, %g1 /* %g1 addr of table entry */ ;\
182	ldx [%g1], %g2 /* %g2 reg paddr */ ;\
183	READ_REGS_FOR_HALT(%g2) ;\
184	.poplocals
185	#endif
186
187	/*
188	* Niagara2 > 1.x: use the "halt" instruction.
189	*/
190	#define HALT_STRAND_NIAGARA2() \
191	halt
192
193
194	#ifdef SUPPORT_NIAGARA2_1x
195	#define HALT_STRAND() \
196	.pushlocals ;\
197	rdhpr %hver, %g1 ;\
198	srlx %g1, VER_MASK_MAJOR_SHIFT, %g1 ;\
199	and %g1, VER_MASK_MAJOR_MASK, %g1 ;\
200	cmp %g1, 1 /* Check for Niagara2 1.x */ ;\
201	bleu,pt %xcc, 8f ;\
202	nop ;\
203	halt ;\
204	ba %xcc, 9f ;\
205	nop ;\
206	8: ;\
207	HALT_STRAND_NIAGARA2_1x() ;\
208	9: ;\
209	.poplocals
210	#else
211	#define HALT_STRAND HALT_STRAND_NIAGARA2
212	#endif
213
214	/* END CSTYLED */
215
216	#ifdef __cplusplus
217	}
218	#endif
219
220	#endif /* _NIAGARA2_CMP_H */