[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / platform / fpga.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: fpga.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _HURON_PLATFORM_FPGA_H_
#define	_HURON_PLATFORM_FPGA_H_

#pragma ident	"@(#)fpga.h	1.5	07/08/16 SMI"

#ifdef __cplusplus
extern "C" {
#endif

#define	HOST_REGS_BASE(x)	(FPGA_BASE + (MByte(13) + (x)))
#define	FPGA_SRAM_BASE		MByte(14)
#define	FPGA_INTR_BASE		HOST_REGS_BASE(0x18000)

#define	FPGA_Q_SEND		0x18
#define	FPGA_Q_STATUS		0x20

/* Interrupt control */
#define	FPGA_MBOX_INTR_STATUS   0x0
#define	FPGA_MBOX_INTR_ENABLE   0x8
#define	FPGA_MBOX_INTR_DISABLE  0x10
#define	FPGA_OTHER_INTR_STATUS  0x1
#define	FPGA_OTHER_INTR_ENABLE  0x9
#define	FPGA_OTHER_INTR_DISABLE 0x11

#define	FPGA_INT_UART_BIT	0x7

/* MMU IO bypass */
#define	FPGA_UART_BASE		(FPGA_BASE + 0xca0000)
#define	FPGA_UART_LIMIT		(FPGA_UART_BASE + 0x2000)

#define	UART_CLOCK_MULTIPLIER	1 /* For "interim" Niagara1-esque FPGA */

/* BEGIN CSTYLED */
#define FPGA_CLEAR_LDC_INTERRUPTS(scr1, scr2)			\
	setx	FPGA_LDCIN_BASE, scr1, scr2			;\
	ld	[scr2 + FPGA_LDC_RECV_REG], scr1		;\
	st	scr1, [scr2 + FPGA_LDC_RECV_REG]
/* END CSTYLED */

/*
 * FPGA ID register
 */
#define	FPGA_DEVICE_ID			HOST_REGS_BASE(0x0)

#define	FPGA_ID_MINOR_ID_SHIFT		0
#define	FPGA_ID_MINOR_ID_MASK		0x1f
#define	FPGA_ID_MAJOR_ID_SHIFT		5
#define	FPGA_ID_MAJOR_ID_MASK		0x7
#define	FPGA_ID_PLATFORM_ID_SHIFT	8
#define	FPGA_ID_PLATFORM_ID_MASK	0xf
#define	FPGA_ID_DEBUG_ID_SHIFT		12
#define	FPGA_ID_DEBUG_ID_MASK		0x7
#define	FPGA_MIN_MAJOR_ID_RESET_SUPPORT	0x3	/* minimum major value for */
						/* ldoms fpga reset support */

/*
 * FPGA Platform-specific Registers
 * GPIO pcie reset control registers (see 0.7 FPGA PRM)
 */
#define	FPGA_PLATFORM_REGS		(FPGA_BASE + 0xcb0000)

#define	FPGA_LDOM_RESET_CONTROL_OFFSET		0x30
#define	FPGA_LDOM_SLOT_RESET_CONTROL_OFFSET	0x31
#define	FPGA_DEVICE_PRESENT_OFFSET		0x40

#define	FPGA_LDOM_RESET_CONTROL		(FPGA_PLATFORM_REGS + \
					    FPGA_LDOM_RESET_CONTROL_OFFSET)
#define	FPGA_LDOM_SLOT_RESET_CONTROL	(FPGA_PLATFORM_REGS + \
					    FPGA_LDOM_SLOT_RESET_CONTROL_OFFSET)
#define	FPGA_DEVICE_PRESENT		(FPGA_PLATFORM_REGS + \
					    FPGA_DEVICE_PRESENT_OFFSET)
/*
 * Reset control register mask is 8 bits
 * The bit defines are as follows
 *
 * bit name for Huron
 *
 *  0   8533 Reset (switch 0)
 *  1   8533 Reset (switch 1)
 *  2   8533 Reset (switch 2)
 *  3   1068 SAS Reset
 *  4   8111 PCI-e to PCI
 *  5   82571 GBE Reset (device 0)
 *  6   82571 GBE Reset (device 1)
 *  7   USB Reset
 *
 */
#define	FPGA_LDOM_RESET_CONTROL_MASK	0xff
#define	FPGA_LDOM_RESET_CONTROL_DEV_0	(1 << 0)
#define	FPGA_LDOM_RESET_CONTROL_DEV_1	(1 << 1)


/*
 * Reset control 'slot' register mask is 8 bits
 * The bits defines are as follows
 *
 * bit	name for Huron
 *  0	PCI-E Slot 1
 *  1	PCI-E Slot 2
 *  2	PCI-E Slot 3
 *  3	PCI-E Slot 4
 *  4	PCI-E Slot 5
 *  5	PCI-E Slot 6
 *  6	XAUI 0
 *  7	XAUI 1
 */
#define	FPGA_PCIE_SLOT_RESET_CTRL_MASK	0x3f
#define	FPGA_XAUI_SLOT_RESET_CTRL_MASK	0xc0

#ifndef _ASM

struct fpga_cookie {
	uint64_t	status;		/* Interrupt status register */
	uint64_t	enable;		/* Interrupt enable register */
	uint64_t	disable;	/* Interrupt disable register */
	uint8_t		valid;		/* Enabled / Disabled */
	uint8_t		state;		/* Idle / Received / Delivered */
	uint8_t		target;		/* Physical CPU number */
};

extern void fpga_uart_mondo_receive(void);
extern void fpga_uart_intr_getvalid(void);
extern void fpga_uart_intr_setvalid(void);
extern void fpga_uart_intr_getstate(void);
extern void fpga_uart_intr_setstate(void);
extern void fpga_uart_intr_gettarget(void);
extern void fpga_uart_intr_settarget(void);

#endif /* !_ASM */

#ifdef __cplusplus
}
#endif

#endif /* _HURON_PLATFORM_FPGA_H_ */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: fpga.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _HURON_PLATFORM_FPGA_H_
	50	#define _HURON_PLATFORM_FPGA_H_
	51
	52	#pragma ident "@(#)fpga.h 1.5 07/08/16 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	#define HOST_REGS_BASE(x) (FPGA_BASE + (MByte(13) + (x)))
	59	#define FPGA_SRAM_BASE MByte(14)
	60	#define FPGA_INTR_BASE HOST_REGS_BASE(0x18000)
	61
	62	#define FPGA_Q_SEND 0x18
	63	#define FPGA_Q_STATUS 0x20
	64
65	/* Interrupt control */
66	#define FPGA_MBOX_INTR_STATUS 0x0
67	#define FPGA_MBOX_INTR_ENABLE 0x8
68	#define FPGA_MBOX_INTR_DISABLE 0x10
69	#define FPGA_OTHER_INTR_STATUS 0x1
70	#define FPGA_OTHER_INTR_ENABLE 0x9
71	#define FPGA_OTHER_INTR_DISABLE 0x11
72
73	#define FPGA_INT_UART_BIT 0x7
74
75	/* MMU IO bypass */
76	#define FPGA_UART_BASE (FPGA_BASE + 0xca0000)
77	#define FPGA_UART_LIMIT (FPGA_UART_BASE + 0x2000)
78
79	#define UART_CLOCK_MULTIPLIER 1 /* For "interim" Niagara1-esque FPGA */
80
81	/* BEGIN CSTYLED */
82	#define FPGA_CLEAR_LDC_INTERRUPTS(scr1, scr2) \
83	setx FPGA_LDCIN_BASE, scr1, scr2 ;\
84	ld [scr2 + FPGA_LDC_RECV_REG], scr1 ;\
85	st scr1, [scr2 + FPGA_LDC_RECV_REG]
86	/* END CSTYLED */
87
88	/*
89	* FPGA ID register
90	*/
91	#define FPGA_DEVICE_ID HOST_REGS_BASE(0x0)
92
93	#define FPGA_ID_MINOR_ID_SHIFT 0
94	#define FPGA_ID_MINOR_ID_MASK 0x1f
95	#define FPGA_ID_MAJOR_ID_SHIFT 5
96	#define FPGA_ID_MAJOR_ID_MASK 0x7
97	#define FPGA_ID_PLATFORM_ID_SHIFT 8
98	#define FPGA_ID_PLATFORM_ID_MASK 0xf
99	#define FPGA_ID_DEBUG_ID_SHIFT 12
100	#define FPGA_ID_DEBUG_ID_MASK 0x7
101	#define FPGA_MIN_MAJOR_ID_RESET_SUPPORT 0x3 /* minimum major value for */
102	/* ldoms fpga reset support */
103
104	/*
105	* FPGA Platform-specific Registers
106	* GPIO pcie reset control registers (see 0.7 FPGA PRM)
107	*/
108	#define FPGA_PLATFORM_REGS (FPGA_BASE + 0xcb0000)
109
110	#define FPGA_LDOM_RESET_CONTROL_OFFSET 0x30
111	#define FPGA_LDOM_SLOT_RESET_CONTROL_OFFSET 0x31
112	#define FPGA_DEVICE_PRESENT_OFFSET 0x40
113
114	#define FPGA_LDOM_RESET_CONTROL (FPGA_PLATFORM_REGS + \
115	FPGA_LDOM_RESET_CONTROL_OFFSET)
116	#define FPGA_LDOM_SLOT_RESET_CONTROL (FPGA_PLATFORM_REGS + \
117	FPGA_LDOM_SLOT_RESET_CONTROL_OFFSET)
118	#define FPGA_DEVICE_PRESENT (FPGA_PLATFORM_REGS + \
119	FPGA_DEVICE_PRESENT_OFFSET)
120	/*
121	* Reset control register mask is 8 bits
122	* The bit defines are as follows
123	*
124	* bit name for Huron
125	*
126	* 0 8533 Reset (switch 0)
127	* 1 8533 Reset (switch 1)
128	* 2 8533 Reset (switch 2)
129	* 3 1068 SAS Reset
130	* 4 8111 PCI-e to PCI
131	* 5 82571 GBE Reset (device 0)
132	* 6 82571 GBE Reset (device 1)
133	* 7 USB Reset
134	*
135	*/
136	#define FPGA_LDOM_RESET_CONTROL_MASK 0xff
137	#define FPGA_LDOM_RESET_CONTROL_DEV_0 (1 << 0)
138	#define FPGA_LDOM_RESET_CONTROL_DEV_1 (1 << 1)
139
140
141	/*
142	* Reset control 'slot' register mask is 8 bits
143	* The bits defines are as follows
144	*
145	* bit name for Huron
146	* 0 PCI-E Slot 1
147	* 1 PCI-E Slot 2
148	* 2 PCI-E Slot 3
149	* 3 PCI-E Slot 4
150	* 4 PCI-E Slot 5
151	* 5 PCI-E Slot 6
152	* 6 XAUI 0
153	* 7 XAUI 1
154	*/
155	#define FPGA_PCIE_SLOT_RESET_CTRL_MASK 0x3f
156	#define FPGA_XAUI_SLOT_RESET_CTRL_MASK 0xc0
157
158	#ifndef _ASM
159
160	struct fpga_cookie {
161	uint64_t status; /* Interrupt status register */
162	uint64_t enable; /* Interrupt enable register */
163	uint64_t disable; /* Interrupt disable register */
164	uint8_t valid; /* Enabled / Disabled */
165	uint8_t state; /* Idle / Received / Delivered */
166	uint8_t target; /* Physical CPU number */
167	};
168
169	extern void fpga_uart_mondo_receive(void);
170	extern void fpga_uart_intr_getvalid(void);
171	extern void fpga_uart_intr_setvalid(void);
172	extern void fpga_uart_intr_getstate(void);
173	extern void fpga_uart_intr_setstate(void);
174	extern void fpga_uart_intr_gettarget(void);
175	extern void fpga_uart_intr_settarget(void);
176
177	#endif /* !_ASM */
178
179	#ifdef __cplusplus
180	}
181	#endif
182
183	#endif /* _HURON_PLATFORM_FPGA_H_ */