[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / platform / ldc.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: ldc.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _PLATFORM_LDC_H
#define	_PLATFORM_LDC_H

#pragma ident	"@(#)ldc.h	1.3	07/05/17 SMI"

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Location of the SRAM queues
 * XXX - Eventually, we probably want to read this out of the SRAM.
 * For now it is hardcoded between HV and vbsc.
 */
#define	LDC_SRAM_CHANNEL_TXBASE	FPGA_BASE + FPGA_SRAM_BASE + 0x460
#define	LDC_SRAM_CHANNEL_RXBASE	FPGA_BASE + FPGA_SRAM_BASE + 0x19a0

/*
 * FPGA mailbox for LDC
 */
#define	FPGA_LDCIN_BASE		FPGA_Q1IN_BASE
#define	FPGA_LDCOUT_BASE	FPGA_Q1OUT_BASE

#define	FPGA_LDC_RECV_REG		0x0
#define	FPGA_LDC_MASK_REG		0x10

/*
 * FPGA_LDC_RECV_REG[14:0]	space available for channel
 *				corresponding to bit
 *
 * FPGA_LDC_RECV_REG[30:16]	data available for channel
 *				corresponding to bit
 *
 * bit[15] unused, reserved for future use
 *
 *
 * FPGA_LDC_RECV_REG[31]	reset all channels
 */
#define	FPGA_LDC_RECV_TX_CHANNELS	15
#define	FPGA_LDC_RECV_TX_CHANNEL_MASK	0x7fff
#define	FPGA_LDC_RECV_TX_CHANNEL_SHIFT	0
#define	FPGA_LDC_RECV_RX_CHANNELS	30
#define	FPGA_LDC_RECV_RX_CHANNEL_MASK	0x7fff0000
#define	FPGA_LDC_RECV_RX_CHANNEL_SHIFT	16

#define	FPGA_LDC_RECV_STATE_CHG_MASK	0x80000000	/* bit 31 */

/*
 * FPGA Interrupts for LDC
 */
#define	IRQ_LDC_OUT	(IRQ1_QUEUE_OUT | IRQ1_QUEUE_IN)

/*
 * Send the SP an interrupt on the LDC IN channel.
 *
 * target_endpt		target endpoint, preserved
 * tmp1, tmp2		clobbered
 * status_bit		interrupt type
 */
/* BEGIN CSTYLED */
#define	LDC_SEND_SP_INTR(target_endpt, tmp1, tmp2, status_bit)	\
	.pushlocals							;\
	setx	FPGA_LDCOUT_BASE, tmp1, tmp2				;\
	mov	status_bit, tmp1					;\
									;\
	cmp	tmp1, SP_LDC_STATE_CHG					;\
	be,a,pn	%xcc, 3f						;\
	  set	FPGA_LDC_RECV_STATE_CHG_MASK, tmp1			;\
									;\
	cmp	tmp1, SP_LDC_DATA					;\
	be,pt	%xcc, 2f						;\
	ldub	[target_endpt + LDC_CHANNEL_IDX], target_endpt		;\
									;\
	/* space available */						;\
	mov	1, tmp1							;\
	add	target_endpt, FPGA_LDC_RECV_TX_CHANNEL_SHIFT, target_endpt	;\
	ba,pt	%xcc, 3f						;\
	sllx	tmp1, target_endpt, tmp1				;\
2:									;\
	/* data available */						;\
	mov	1, tmp1							;\
	add	target_endpt, FPGA_LDC_RECV_RX_CHANNEL_SHIFT, target_endpt	;\
	sllx	tmp1, target_endpt, tmp1				;\
3:									;\
	st	tmp1, [tmp2 + FPGA_LDC_RECV_REG]			;\
	.poplocals
/* END CSTYLED */

#ifndef _ASM

#ifdef CONFIG_SPLIT_SRAM_ERRATUM

typedef struct sp_ldc_sram_ptrs {
	uint64_t	inq_offset;
	uint64_t	inq_data_offset;
	uint64_t	inq_num_packets;
	uint64_t	outq_offset;
	uint64_t	outq_data_offset;
	uint64_t	outq_num_packets;
} sp_ldc_sram_ptrs_t;

#endif	/* CONFIG_SPLIT_SRAM_ERRATUM */

#endif /* !_ASM */

#ifdef __cplusplus
}
#endif

#endif /* _PLATFORM_LDC_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: ldc.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _PLATFORM_LDC_H
	50	#define _PLATFORM_LDC_H
	51
	52	#pragma ident "@(#)ldc.h 1.3 07/05/17 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	/*
	59	* Location of the SRAM queues
	60	* XXX - Eventually, we probably want to read this out of the SRAM.
	61	* For now it is hardcoded between HV and vbsc.
	62	*/
	63	#define LDC_SRAM_CHANNEL_TXBASE FPGA_BASE + FPGA_SRAM_BASE + 0x460
	64	#define LDC_SRAM_CHANNEL_RXBASE FPGA_BASE + FPGA_SRAM_BASE + 0x19a0
65
66	/*
67	* FPGA mailbox for LDC
68	*/
69	#define FPGA_LDCIN_BASE FPGA_Q1IN_BASE
70	#define FPGA_LDCOUT_BASE FPGA_Q1OUT_BASE
71
72	#define FPGA_LDC_RECV_REG 0x0
73	#define FPGA_LDC_MASK_REG 0x10
74
75	/*
76	* FPGA_LDC_RECV_REG[14:0] space available for channel
77	* corresponding to bit
78	*
79	* FPGA_LDC_RECV_REG[30:16] data available for channel
80	* corresponding to bit
81	*
82	* bit[15] unused, reserved for future use
83	*
84	*
85	* FPGA_LDC_RECV_REG[31] reset all channels
86	*/
87	#define FPGA_LDC_RECV_TX_CHANNELS 15
88	#define FPGA_LDC_RECV_TX_CHANNEL_MASK 0x7fff
89	#define FPGA_LDC_RECV_TX_CHANNEL_SHIFT 0
90	#define FPGA_LDC_RECV_RX_CHANNELS 30
91	#define FPGA_LDC_RECV_RX_CHANNEL_MASK 0x7fff0000
92	#define FPGA_LDC_RECV_RX_CHANNEL_SHIFT 16
93
94	#define FPGA_LDC_RECV_STATE_CHG_MASK 0x80000000 /* bit 31 */
95
96	/*
97	* FPGA Interrupts for LDC
98	*/
99	#define IRQ_LDC_OUT (IRQ1_QUEUE_OUT \| IRQ1_QUEUE_IN)
100
101	/*
102	* Send the SP an interrupt on the LDC IN channel.
103	*
104	* target_endpt target endpoint, preserved
105	* tmp1, tmp2 clobbered
106	* status_bit interrupt type
107	*/
108	/* BEGIN CSTYLED */
109	#define LDC_SEND_SP_INTR(target_endpt, tmp1, tmp2, status_bit) \
110	.pushlocals ;\
111	setx FPGA_LDCOUT_BASE, tmp1, tmp2 ;\
112	mov status_bit, tmp1 ;\
113	;\
114	cmp tmp1, SP_LDC_STATE_CHG ;\
115	be,a,pn %xcc, 3f ;\
116	set FPGA_LDC_RECV_STATE_CHG_MASK, tmp1 ;\
117	;\
118	cmp tmp1, SP_LDC_DATA ;\
119	be,pt %xcc, 2f ;\
120	ldub [target_endpt + LDC_CHANNEL_IDX], target_endpt ;\
121	;\
122	/* space available */ ;\
123	mov 1, tmp1 ;\
124	add target_endpt, FPGA_LDC_RECV_TX_CHANNEL_SHIFT, target_endpt ;\
125	ba,pt %xcc, 3f ;\
126	sllx tmp1, target_endpt, tmp1 ;\
127	2: ;\
128	/* data available */ ;\
129	mov 1, tmp1 ;\
130	add target_endpt, FPGA_LDC_RECV_RX_CHANNEL_SHIFT, target_endpt ;\
131	sllx tmp1, target_endpt, tmp1 ;\
132	3: ;\
133	st tmp1, [tmp2 + FPGA_LDC_RECV_REG] ;\
134	.poplocals
135	/* END CSTYLED */
136
137	#ifndef _ASM
138
139	#ifdef CONFIG_SPLIT_SRAM_ERRATUM
140
141	typedef struct sp_ldc_sram_ptrs {
142	uint64_t inq_offset;
143	uint64_t inq_data_offset;
144	uint64_t inq_num_packets;
145	uint64_t outq_offset;
146	uint64_t outq_data_offset;
147	uint64_t outq_num_packets;
148	} sp_ldc_sram_ptrs_t;
149
150	#endif /* CONFIG_SPLIT_SRAM_ERRATUM */
151
152	#endif /* !_ASM */
153
154	#ifdef __cplusplus
155	}
156	#endif
157
158	#endif /* _PLATFORM_LDC_H */