[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / platform / mau.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: mau.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _PLATFORM_MAU_H
#define	_PLATFORM_MAU_H

#pragma ident	"@(#)mau.h	1.3	07/07/27 SMI"

/*
 * Niagara2 MAU definitions
 */

#ifdef __cplusplus
extern "C" {
#endif

#include <resource.h>
#include <config.h>
#include <rng.h>


/*
 * MA Control Register
 *	Field	Bits	R/W
 *	-----	----	---
 *	HWE	22	RO
 *	INVOP	21	RO
 *	STRAND	20:18	R/W
 *	INTR	17	R/W
 *	BUSY	16	RO
 *	OP	12:8	R/W
 *	LENGTH	7:0	R/W
 */
#define	MA_CTL_HWE_SHIFT	22
#define	MA_CTL_HWE_MASK		0x1
#define	MA_CTL_INVOP_SHIFT	21
#define	MA_CTL_INVOP_MASK	0x1
#define	MA_CTL_STRAND_SHIFT	18
#define	MA_CTL_BUSY_SHIFT	16
#define	MA_CTL_INTR_SHIFT	17
#define	MA_CTL_INTR_MASK	0x1
#define	MA_CTL_OP_SHIFT		8
#define	MA_CTL_OP_MASK		0x1f
#define	MA_CTL_LENGTH_MASK	0xff


#ifdef _ASM

/* BEGIN CSTYLED */

/* Range check and real to phys conversion macro */
#define	REAL_TO_PHYS(raddr, size, paddr, fail_label, gstruct, scr2)	\
	GUEST_STRUCT(gstruct)						;\
	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2)	;\
	RA2PA_CONV(gstruct, raddr, paddr, scr2)

#define	REAL_TO_PHYS_G(raddr, size, paddr, fail_label, gstruct, scr2)	\
	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2)	;\
	RA2PA_CONV(gstruct, raddr, paddr, scr2)

/*
 * MAU_LOAD preps and loads MAU registers.
 * If a Load or Store operation is being performed, then the
 * MA address is translated to a physical address.
 * Leaves an errno result in 'ret' if there is an
 * alignment issue with the MA address.
 *
 * membar #Sync prior to storing Control register
 * is due to NIAGARA_ERRATUM_41.
 */
#define	MAU_LOAD1(mau_struct, nhd, tid, ret, intr, errlbl, chklbl, scr1, scr2, scr3)	\
	.pushlocals					; \
	ldx	[nhd + MR_CTL], scr1			; \
	srlx	scr1, MA_CTL_OP_SHIFT, scr2		; \
	and	scr2, MA_CTL_OP_MASK, scr2		; \
	cmp	scr2, MA_OP_STORE			; \
	bne	%xcc, 2f				; \
	 nop						;\
/* #ifdef	ERRATA_192 */ \
	andn	mau_struct, 7, scr1			; \
	mov	1, scr3					; \
	stx	scr3, [scr1 + MAU_STORE_IN_PROGR]	; \
	ba	0f					; \
	 nop						; \
/* #endif  */\
2:							; \
	cmp	scr2, MA_OP_LOAD			; \
	bne,a	%xcc, 1f				; \
	 ldx	[nhd + MR_MPA], scr1			; \
0:							; \
	and	scr1, MA_CTL_LENGTH_MASK, scr1		; \
	inc	scr1					; \
	sllx	scr1, MA_WORDS2BYTES_SHIFT, scr2	; \
	ldx	[nhd + MR_MPA], scr1			; \
	btst	NCS_PTR_ALIGN - 1, scr1			; \
	bnz,a,pn %xcc, chklbl				; \
	 mov	EINVAL, ret				; \
	REAL_TO_PHYS(scr1, scr2, scr1, errlbl, scr3, ret)       ; \
1:							; \
	mov	ASI_MAU_MPA, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_MA], scr1			; \
	mov	ASI_MAU_ADDR, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_NP], scr1			; \
	mov	ASI_MAU_NP, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
/*#ifdef	ERRATA_192 */ \
	andn	mau_struct, 7, scr1			; \
	ldx	[scr1 + MAU_STORE_IN_PROGR], scr3	; \
	sub	scr3, 1, scr3				; \
	brnz,pn	scr3, 3f				; \
	 nop						; \
/*** stop the cwq if it is not stopped ***/ \
	mov	ASI_SPU_CWQ_CSR, scr1			; \
	ldxa	[scr1]ASI_STREAM, scr2			; \
	stxa	%g0, [scr1]ASI_STREAM			;  \
	and	scr2, 1, scr2				; \
	andn	mau_struct, 7, scr1			; \
	stx	scr2, [scr1 + MAU_ENABLE_CWQ]		; \
	mov	ASI_SPU_CWQ_SYNC, scr1			; \
	ldxa	[scr1]ASI_STREAM, %g0			; \
3:							; \
/*#endif */ \
	ldx	[nhd + MR_CTL], scr1			; \
	sll	tid, MA_CTL_STRAND_SHIFT, scr2		; \
	or	scr1, scr2, scr1			; \
	mov	ASI_MAU_CONTROL, scr2			; \
	membar	#Sync					; \
	mov	MA_CTL_INTR_MASK, scr3			; \
	sllx	scr3, MA_CTL_INTR_SHIFT, scr3		; \
	andn	scr1, scr3, scr1			; \
	mov	intr, scr3				; \
	and	scr3, MA_CTL_INTR_MASK, scr3		; \
	sllx	scr3, MA_CTL_INTR_SHIFT, scr3		; \
	or	scr1, scr3, scr1			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	.poplocals

#define	MAU_LOAD(nhd, tid, ret, intr, errlbl, chklbl, scr1, scr2, scr3)	\
	.pushlocals					; \
	ldx	[nhd + MR_CTL], scr1			; \
	srlx	scr1, MA_CTL_OP_SHIFT, scr2		; \
	and	scr2, MA_CTL_OP_MASK, scr2		; \
	cmp	scr2, MA_OP_LOAD			; \
	be	%xcc, 0f				; \
	cmp	scr2, MA_OP_STORE			; \
	bne,a	%xcc, 1f				; \
	  ldx	[nhd + MR_MPA], scr1			; \
0:							; \
	and	scr1, MA_CTL_LENGTH_MASK, scr1		; \
	inc	scr1					; \
	sllx	scr1, MA_WORDS2BYTES_SHIFT, scr2	; \
	ldx	[nhd + MR_MPA], scr1			; \
	btst	NCS_PTR_ALIGN - 1, scr1			; \
	bnz,a,pn %xcc, chklbl				; \
	  mov	EINVAL, ret				; \
	REAL_TO_PHYS(scr1, scr2, scr1, errlbl, scr3, ret)       ; \
1:							; \
	mov	ASI_MAU_MPA, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_MA], scr1			; \
	mov	ASI_MAU_ADDR, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_NP], scr1			; \
	mov	ASI_MAU_NP, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_CTL], scr1			; \
	sll	tid, MA_CTL_STRAND_SHIFT, scr2		; \
	or	scr1, scr2, scr1			; \
	mov	ASI_MAU_CONTROL, scr2			; \
	membar	#Sync					; \
	mov	MA_CTL_INTR_MASK, scr3			; \
	sllx	scr3, MA_CTL_INTR_SHIFT, scr3		; \
	andn	scr1, scr3, scr1			; \
	mov	intr, scr3				; \
	and	scr3, MA_CTL_INTR_MASK, scr3		; \
	sllx	scr3, MA_CTL_INTR_SHIFT, scr3		; \
	or	scr1, scr3, scr1			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	.poplocals


/*
 * MAU_CHECK_ERR checks the contents of the Control
 * register following a MAU operation.  The HWE and
 * INVOP bits indicate if the operation was successully
 * performed or not.
 * Leaves an errno result in 'ret'.
 */
#define	MAU_CHECK_ERR(ret, scr1, scr2)			\
	.pushlocals					; \
	mov	ND_ERR_OK, ret				; \
	mov	ASI_MAU_CONTROL, scr1			; \
	ldxa	[scr1]ASI_STREAM, scr1			; \
	srlx	scr1, MA_CTL_HWE_SHIFT, scr2		; \
	btst	MA_CTL_HWE_MASK, scr2			; \
	bnz,a,pn %xcc, 0f				; \
	  or	ret, ND_ERR_HWE, ret			; \
0:							; \
	srlx	scr1, MA_CTL_INVOP_SHIFT, scr2		; \
	btst	MA_CTL_INVOP_MASK, scr2			; \
	bnz,a,pn %xcc, 1f				; \
	  or	ret, ND_ERR_INVOP, ret			; \
1:							; \
	.poplocals

#ifndef	NCS_HANDLE_DEFS
#define	NCS_HANDLE_DEFS

#define	HANDLE_SIGMASK		0xfff
#define	HANDLE_IDMASK		0xfff
#define	HANDLE_IDSHIFT		16
#define	HANDLE2ID(hdl, idx)			\
	srlx	hdl, HANDLE_IDSHIFT, idx	; \
	and	idx, HANDLE_IDMASK, idx
#define	ID2HANDLE(idx, sig, hdl)		\
	and	idx, HANDLE_IDMASK, hdl		; \
	sllx	hdl, HANDLE_IDSHIFT, hdl	; \
	or	hdl, sig, hdl

#endif	/* NCS_HANDLE_DEFS */

#define	MAU_HANDLE_SIG		0x0864
#define	HANDLE_IS_MAU(hdl, scr)			\
	and	hdl, HANDLE_SIGMASK, scr	; \
	cmp	scr, MAU_HANDLE_SIG
/*
 * MAU_HANDLE2ID_VERIFY
 *	Translates and verifies a MAU specific handle
 *	for a valid signature and ID.
 */
#define	MAU_HANDLE2ID_VERIFY(hdl, lbl, id)	\
	HANDLE_IS_MAU(hdl, id)			; \
	bne,pn	%xcc, lbl			; \
	nop					; \
	HANDLE2ID(hdl, id)			; \
	cmp	id, NMAUS			; \
	bgeu,pn	%xcc, lbl			; \
	nop

#ifdef ERRATA_192
#define	MAU_CLEAR_QSTATE(mau)			\
	stx	%g0, [mau + MAU_STORE_IN_PROGR]		; \
	stx	%g0, [mau + MAU_ENABLE_CWQ]		; \
	stx	%g0, [mau + MAU_QUEUE + MQ_LOCK]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_BASE_RA]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_BASE]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_END]		; \
	stx	%g0, [mau + MAU_QUEUE + MQ_HEAD]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_HEAD_MARKER]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_TAIL]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_NENTRIES]	; \
	st	%g0, [mau + MAU_QUEUE + MQ_BUSY]
#else
#define	MAU_CLEAR_QSTATE(mau)			\
	stx	%g0, [mau + MAU_QUEUE + MQ_LOCK]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_BASE_RA]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_BASE]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_END]		; \
	stx	%g0, [mau + MAU_QUEUE + MQ_HEAD]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_HEAD_MARKER]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_TAIL]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_NENTRIES]	; \
	st	%g0, [mau + MAU_QUEUE + MQ_BUSY]
#endif

#define	GUEST_MID_GETMAU(guest, id, mau)	\
	sllx	id, GUEST_MAUS_SHIFT, mau	; \
	add	mau, GUEST_MAUS, mau		; \
	ldx	[guest + mau], mau

#define	GUEST_MID_SETMAU(guest, id, mau, scr)	\
	sllx	id, GUEST_MAUS_SHIFT, scr	; \
	add	scr, GUEST_MAUS, scr		; \
	stx	mau, [guest + scr]

#define	MAU_LOCK_ENTER(mau, lck, scr1, scr2)	\
	add	mau, MAU_QUEUE, lck		; \
	add	lck, MQ_LOCK, lck		; \
	SPINLOCK_ENTER(lck, scr1, scr2)
#define	MAU_LOCK_EXIT(mau, lck)			\
	add	mau, MAU_QUEUE, lck		; \
	add	lck, MQ_LOCK, lck		; \
	SPINLOCK_EXIT(lck)
#define	MAU_LOCK_EXIT_L(lck)			\
	SPINLOCK_EXIT(lck)

/*
 *	We wait for the MAU to stop by doing a sync-load.
 *	If the MAU is currently busy running a job on behalf
 *	of the current strand (cpu) being stopped then the
 *	sync-load will wait for it to complete.  If the MAU
 *	is busy running a job for a different strand (cpu)
 *	then the sync-load will immediately return.  Since
 *	the job being executed is on behalf of a different
 *	cpu then the immediate return is okay since we only
 *	care about the local cpu being stopped.
 *
 * 	Reading the %halt hyper-privileged register has the
 * 	side-effect of clearing any pending CWQ/MAU interrupts
 */
#define	CRYPTO_STOP(scr1, scr2)				\
	.pushlocals					;\
	rdhpr   %hver, scr1				;\
	srlx    scr1, VER_MASK_MAJOR_SHIFT, scr1	;\
	and     scr1, VER_MASK_MAJOR_MASK, scr1		;\
	cmp     scr1, 1	/* Check for Niagara2 1.x */	;\
	bleu,pt %xcc, 1f				;\
	nop						;\
	read_halt					;\
1:							;\
	/*						;\
	 * Do a synchronous load to wait for 		;\
	 * MAU to idle.					;\
	 */						;\
	mov	ASI_MAU_SYNC, scr2			;\
	ldxa	[scr2]ASI_STREAM, %g0			;\
							;\
	.poplocals


#endif	/* _ASM */

/* END CSTYLED */

#ifdef __cplusplus
}
#endif

#endif /* _PLATFORM_MAU_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: mau.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _PLATFORM_MAU_H
	50	#define _PLATFORM_MAU_H
	51
	52	#pragma ident "@(#)mau.h 1.3 07/07/27 SMI"
	53
	54	/*
	55	* Niagara2 MAU definitions
	56	*/
	57
	58	#ifdef __cplusplus
	59	extern "C" {
	60	#endif
	61
	62	#include <resource.h>
	63	#include <config.h>
	64	#include <rng.h>
65
66
67	/*
68	* MA Control Register
69	* Field Bits R/W
70	* ----- ---- ---
71	* HWE 22 RO
72	* INVOP 21 RO
73	* STRAND 20:18 R/W
74	* INTR 17 R/W
75	* BUSY 16 RO
76	* OP 12:8 R/W
77	* LENGTH 7:0 R/W
78	*/
79	#define MA_CTL_HWE_SHIFT 22
80	#define MA_CTL_HWE_MASK 0x1
81	#define MA_CTL_INVOP_SHIFT 21
82	#define MA_CTL_INVOP_MASK 0x1
83	#define MA_CTL_STRAND_SHIFT 18
84	#define MA_CTL_BUSY_SHIFT 16
85	#define MA_CTL_INTR_SHIFT 17
86	#define MA_CTL_INTR_MASK 0x1
87	#define MA_CTL_OP_SHIFT 8
88	#define MA_CTL_OP_MASK 0x1f
89	#define MA_CTL_LENGTH_MASK 0xff
90
91
92	#ifdef _ASM
93
94	/* BEGIN CSTYLED */
95
96	/* Range check and real to phys conversion macro */
97	#define REAL_TO_PHYS(raddr, size, paddr, fail_label, gstruct, scr2) \
98	GUEST_STRUCT(gstruct) ;\
99	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2) ;\
100	RA2PA_CONV(gstruct, raddr, paddr, scr2)
101
102	#define REAL_TO_PHYS_G(raddr, size, paddr, fail_label, gstruct, scr2) \
103	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2) ;\
104	RA2PA_CONV(gstruct, raddr, paddr, scr2)
105
106	/*
107	* MAU_LOAD preps and loads MAU registers.
108	* If a Load or Store operation is being performed, then the
109	* MA address is translated to a physical address.
110	* Leaves an errno result in 'ret' if there is an
111	* alignment issue with the MA address.
112	*
113	* membar #Sync prior to storing Control register
114	* is due to NIAGARA_ERRATUM_41.
115	*/
116	#define MAU_LOAD1(mau_struct, nhd, tid, ret, intr, errlbl, chklbl, scr1, scr2, scr3) \
117	.pushlocals ; \
118	ldx [nhd + MR_CTL], scr1 ; \
119	srlx scr1, MA_CTL_OP_SHIFT, scr2 ; \
120	and scr2, MA_CTL_OP_MASK, scr2 ; \
121	cmp scr2, MA_OP_STORE ; \
122	bne %xcc, 2f ; \
123	nop ;\
124	/* #ifdef ERRATA_192 */ \
125	andn mau_struct, 7, scr1 ; \
126	mov 1, scr3 ; \
127	stx scr3, [scr1 + MAU_STORE_IN_PROGR] ; \
128	ba 0f ; \
129	nop ; \
130	/* #endif */\
131	2: ; \
132	cmp scr2, MA_OP_LOAD ; \
133	bne,a %xcc, 1f ; \
134	ldx [nhd + MR_MPA], scr1 ; \
135	0: ; \
136	and scr1, MA_CTL_LENGTH_MASK, scr1 ; \
137	inc scr1 ; \
138	sllx scr1, MA_WORDS2BYTES_SHIFT, scr2 ; \
139	ldx [nhd + MR_MPA], scr1 ; \
140	btst NCS_PTR_ALIGN - 1, scr1 ; \
141	bnz,a,pn %xcc, chklbl ; \
142	mov EINVAL, ret ; \
143	REAL_TO_PHYS(scr1, scr2, scr1, errlbl, scr3, ret) ; \
144	1: ; \
145	mov ASI_MAU_MPA, scr2 ; \
146	stxa scr1, [scr2]ASI_STREAM ; \
147	ldx [nhd + MR_MA], scr1 ; \
148	mov ASI_MAU_ADDR, scr2 ; \
149	stxa scr1, [scr2]ASI_STREAM ; \
150	ldx [nhd + MR_NP], scr1 ; \
151	mov ASI_MAU_NP, scr2 ; \
152	stxa scr1, [scr2]ASI_STREAM ; \
153	/#ifdef ERRATA_192 / \
154	andn mau_struct, 7, scr1 ; \
155	ldx [scr1 + MAU_STORE_IN_PROGR], scr3 ; \
156	sub scr3, 1, scr3 ; \
157	brnz,pn scr3, 3f ; \
158	nop ; \
159	/* stop the cwq if it is not stopped */ \
160	mov ASI_SPU_CWQ_CSR, scr1 ; \
161	ldxa [scr1]ASI_STREAM, scr2 ; \
162	stxa %g0, [scr1]ASI_STREAM ; \
163	and scr2, 1, scr2 ; \
164	andn mau_struct, 7, scr1 ; \
165	stx scr2, [scr1 + MAU_ENABLE_CWQ] ; \
166	mov ASI_SPU_CWQ_SYNC, scr1 ; \
167	ldxa [scr1]ASI_STREAM, %g0 ; \
168	3: ; \
169	/#endif / \
170	ldx [nhd + MR_CTL], scr1 ; \
171	sll tid, MA_CTL_STRAND_SHIFT, scr2 ; \
172	or scr1, scr2, scr1 ; \
173	mov ASI_MAU_CONTROL, scr2 ; \
174	membar #Sync ; \
175	mov MA_CTL_INTR_MASK, scr3 ; \
176	sllx scr3, MA_CTL_INTR_SHIFT, scr3 ; \
177	andn scr1, scr3, scr1 ; \
178	mov intr, scr3 ; \
179	and scr3, MA_CTL_INTR_MASK, scr3 ; \
180	sllx scr3, MA_CTL_INTR_SHIFT, scr3 ; \
181	or scr1, scr3, scr1 ; \
182	stxa scr1, [scr2]ASI_STREAM ; \
183	.poplocals
184
185	#define MAU_LOAD(nhd, tid, ret, intr, errlbl, chklbl, scr1, scr2, scr3) \
186	.pushlocals ; \
187	ldx [nhd + MR_CTL], scr1 ; \
188	srlx scr1, MA_CTL_OP_SHIFT, scr2 ; \
189	and scr2, MA_CTL_OP_MASK, scr2 ; \
190	cmp scr2, MA_OP_LOAD ; \
191	be %xcc, 0f ; \
192	cmp scr2, MA_OP_STORE ; \
193	bne,a %xcc, 1f ; \
194	ldx [nhd + MR_MPA], scr1 ; \
195	0: ; \
196	and scr1, MA_CTL_LENGTH_MASK, scr1 ; \
197	inc scr1 ; \
198	sllx scr1, MA_WORDS2BYTES_SHIFT, scr2 ; \
199	ldx [nhd + MR_MPA], scr1 ; \
200	btst NCS_PTR_ALIGN - 1, scr1 ; \
201	bnz,a,pn %xcc, chklbl ; \
202	mov EINVAL, ret ; \
203	REAL_TO_PHYS(scr1, scr2, scr1, errlbl, scr3, ret) ; \
204	1: ; \
205	mov ASI_MAU_MPA, scr2 ; \
206	stxa scr1, [scr2]ASI_STREAM ; \
207	ldx [nhd + MR_MA], scr1 ; \
208	mov ASI_MAU_ADDR, scr2 ; \
209	stxa scr1, [scr2]ASI_STREAM ; \
210	ldx [nhd + MR_NP], scr1 ; \
211	mov ASI_MAU_NP, scr2 ; \
212	stxa scr1, [scr2]ASI_STREAM ; \
213	ldx [nhd + MR_CTL], scr1 ; \
214	sll tid, MA_CTL_STRAND_SHIFT, scr2 ; \
215	or scr1, scr2, scr1 ; \
216	mov ASI_MAU_CONTROL, scr2 ; \
217	membar #Sync ; \
218	mov MA_CTL_INTR_MASK, scr3 ; \
219	sllx scr3, MA_CTL_INTR_SHIFT, scr3 ; \
220	andn scr1, scr3, scr1 ; \
221	mov intr, scr3 ; \
222	and scr3, MA_CTL_INTR_MASK, scr3 ; \
223	sllx scr3, MA_CTL_INTR_SHIFT, scr3 ; \
224	or scr1, scr3, scr1 ; \
225	stxa scr1, [scr2]ASI_STREAM ; \
226	.poplocals
227
228
229	/*
230	* MAU_CHECK_ERR checks the contents of the Control
231	* register following a MAU operation. The HWE and
232	* INVOP bits indicate if the operation was successully
233	* performed or not.
234	* Leaves an errno result in 'ret'.
235	*/
236	#define MAU_CHECK_ERR(ret, scr1, scr2) \
237	.pushlocals ; \
238	mov ND_ERR_OK, ret ; \
239	mov ASI_MAU_CONTROL, scr1 ; \
240	ldxa [scr1]ASI_STREAM, scr1 ; \
241	srlx scr1, MA_CTL_HWE_SHIFT, scr2 ; \
242	btst MA_CTL_HWE_MASK, scr2 ; \
243	bnz,a,pn %xcc, 0f ; \
244	or ret, ND_ERR_HWE, ret ; \
245	0: ; \
246	srlx scr1, MA_CTL_INVOP_SHIFT, scr2 ; \
247	btst MA_CTL_INVOP_MASK, scr2 ; \
248	bnz,a,pn %xcc, 1f ; \
249	or ret, ND_ERR_INVOP, ret ; \
250	1: ; \
251	.poplocals
252
253	#ifndef NCS_HANDLE_DEFS
254	#define NCS_HANDLE_DEFS
255
256	#define HANDLE_SIGMASK 0xfff
257	#define HANDLE_IDMASK 0xfff
258	#define HANDLE_IDSHIFT 16
259	#define HANDLE2ID(hdl, idx) \
260	srlx hdl, HANDLE_IDSHIFT, idx ; \
261	and idx, HANDLE_IDMASK, idx
262	#define ID2HANDLE(idx, sig, hdl) \
263	and idx, HANDLE_IDMASK, hdl ; \
264	sllx hdl, HANDLE_IDSHIFT, hdl ; \
265	or hdl, sig, hdl
266
267	#endif /* NCS_HANDLE_DEFS */
268
269	#define MAU_HANDLE_SIG 0x0864
270	#define HANDLE_IS_MAU(hdl, scr) \
271	and hdl, HANDLE_SIGMASK, scr ; \
272	cmp scr, MAU_HANDLE_SIG
273	/*
274	* MAU_HANDLE2ID_VERIFY
275	* Translates and verifies a MAU specific handle
276	* for a valid signature and ID.
277	*/
278	#define MAU_HANDLE2ID_VERIFY(hdl, lbl, id) \
279	HANDLE_IS_MAU(hdl, id) ; \
280	bne,pn %xcc, lbl ; \
281	nop ; \
282	HANDLE2ID(hdl, id) ; \
283	cmp id, NMAUS ; \
284	bgeu,pn %xcc, lbl ; \
285	nop
286
287	#ifdef ERRATA_192
288	#define MAU_CLEAR_QSTATE(mau) \
289	stx %g0, [mau + MAU_STORE_IN_PROGR] ; \
290	stx %g0, [mau + MAU_ENABLE_CWQ] ; \
291	stx %g0, [mau + MAU_QUEUE + MQ_LOCK] ; \
292	stx %g0, [mau + MAU_QUEUE + MQ_BASE_RA] ; \
293	stx %g0, [mau + MAU_QUEUE + MQ_BASE] ; \
294	stx %g0, [mau + MAU_QUEUE + MQ_END] ; \
295	stx %g0, [mau + MAU_QUEUE + MQ_HEAD] ; \
296	stx %g0, [mau + MAU_QUEUE + MQ_HEAD_MARKER] ; \
297	stx %g0, [mau + MAU_QUEUE + MQ_TAIL] ; \
298	stx %g0, [mau + MAU_QUEUE + MQ_NENTRIES] ; \
299	st %g0, [mau + MAU_QUEUE + MQ_BUSY]
300	#else
301	#define MAU_CLEAR_QSTATE(mau) \
302	stx %g0, [mau + MAU_QUEUE + MQ_LOCK] ; \
303	stx %g0, [mau + MAU_QUEUE + MQ_BASE_RA] ; \
304	stx %g0, [mau + MAU_QUEUE + MQ_BASE] ; \
305	stx %g0, [mau + MAU_QUEUE + MQ_END] ; \
306	stx %g0, [mau + MAU_QUEUE + MQ_HEAD] ; \
307	stx %g0, [mau + MAU_QUEUE + MQ_HEAD_MARKER] ; \
308	stx %g0, [mau + MAU_QUEUE + MQ_TAIL] ; \
309	stx %g0, [mau + MAU_QUEUE + MQ_NENTRIES] ; \
310	st %g0, [mau + MAU_QUEUE + MQ_BUSY]
311	#endif
312
313	#define GUEST_MID_GETMAU(guest, id, mau) \
314	sllx id, GUEST_MAUS_SHIFT, mau ; \
315	add mau, GUEST_MAUS, mau ; \
316	ldx [guest + mau], mau
317
318	#define GUEST_MID_SETMAU(guest, id, mau, scr) \
319	sllx id, GUEST_MAUS_SHIFT, scr ; \
320	add scr, GUEST_MAUS, scr ; \
321	stx mau, [guest + scr]
322
323	#define MAU_LOCK_ENTER(mau, lck, scr1, scr2) \
324	add mau, MAU_QUEUE, lck ; \
325	add lck, MQ_LOCK, lck ; \
326	SPINLOCK_ENTER(lck, scr1, scr2)
327	#define MAU_LOCK_EXIT(mau, lck) \
328	add mau, MAU_QUEUE, lck ; \
329	add lck, MQ_LOCK, lck ; \
330	SPINLOCK_EXIT(lck)
331	#define MAU_LOCK_EXIT_L(lck) \
332	SPINLOCK_EXIT(lck)
333
334	/*
335	* We wait for the MAU to stop by doing a sync-load.
336	* If the MAU is currently busy running a job on behalf
337	* of the current strand (cpu) being stopped then the
338	* sync-load will wait for it to complete. If the MAU
339	* is busy running a job for a different strand (cpu)
340	* then the sync-load will immediately return. Since
341	* the job being executed is on behalf of a different
342	* cpu then the immediate return is okay since we only
343	* care about the local cpu being stopped.
344	*
345	* Reading the %halt hyper-privileged register has the
346	* side-effect of clearing any pending CWQ/MAU interrupts
347	*/
348	#define CRYPTO_STOP(scr1, scr2) \
349	.pushlocals ;\
350	rdhpr %hver, scr1 ;\
351	srlx scr1, VER_MASK_MAJOR_SHIFT, scr1 ;\
352	and scr1, VER_MASK_MAJOR_MASK, scr1 ;\
353	cmp scr1, 1 /* Check for Niagara2 1.x */ ;\
354	bleu,pt %xcc, 1f ;\
355	nop ;\
356	read_halt ;\
357	1: ;\
358	/* ;\
359	* Do a synchronous load to wait for ;\
360	* MAU to idle. ;\
361	*/ ;\
362	mov ASI_MAU_SYNC, scr2 ;\
363	ldxa [scr2]ASI_STREAM, %g0 ;\
364	;\
365	.poplocals
366
367
368	#endif /* _ASM */
369
370	/* END CSTYLED */
371
372	#ifdef __cplusplus
373	}
374	#endif
375
376	#endif /* _PLATFORM_MAU_H */