[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / platform / vdev_ops.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: vdev_ops.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _PLATFORM_VDEV_OPS_H
#define	_PLATFORM_VDEV_OPS_H

#pragma ident	"@(#)vdev_ops.h	1.1	07/05/03 SMI"

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Devops assignments to various nexii
 */

#define	DEVOPS_RESERVED		0

#ifdef CONFIG_PIU
#define	DEVOPS_PIU(n)		1
#define	DEVOPS_INT_PIU(n)	2
#define	DEVOPS_MSI_PIU(n)	3
#define	DEVOPS_ERR_PIU(n)	4
#else /* CONFIG_PIU */
#define	DEVOPS_PIU(n)		DEVOPS_RESERVED
#define	DEVOPS_INT_PIU(n)	DEVOPS_RESERVED
#define	DEVOPS_MSI_PIU(n)	DEVOPS_RESERVED
#define	DEVOPS_ERR_PIU(n)	DEVOPS_RESERVED
#endif /* CONFIG_PIU */

#define	DEVOPS_NIU		5
#define	DEVOPS_VDEV		6
#define	DEVOPS_CDEV		7

#ifdef	CONFIG_FPGA_UART
#define	DEVOPS_FPGA		8
#else	/* !CONFIG_FPGA_UART */
#define	DEVOPS_FPGA		DEVOPS_RESERVED
#endif	/* !CONFIG_FPGA_UART */

/*
 * NIU nexus
 */
#define	NIU_COOKIE	((void *)&niu_dev)

#define	VINO_HANDLER_NIU \
	DEVOPS_NIU, DEVOPS_NIU,	/* 00 - 01 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 02 - 03 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 04 - 05 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 06 - 07 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 08 - 09 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 10 - 11 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 12 - 13 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 14 - 15 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 16 - 17 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 18 - 19 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 20 - 21 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 22 - 23 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 24 - 25 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 26 - 27 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 28 - 29 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 30 - 31 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 32 - 33 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 34 - 35 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 36 - 37 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 38 - 39 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 40 - 41 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 42 - 33 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 44 - 45 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 46 - 47 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 48 - 49 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 50 - 51 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 52 - 53 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 54 - 55 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 56 - 57 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 58 - 59 */ \
	DEVOPS_NIU, DEVOPS_NIU,	/* 60 - 61 */ \
	DEVOPS_NIU, DEVOPS_NIU	/* 62 - 63 */

#define	NIU_OPS \
	INTR_OPS(niu), MONDO_OPS(NULL), VINO_OPS(niu),	\
		VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)


/*
 * Piu nexus
 */
#ifdef CONFIG_PIU

#define	PIU_LEAF(n)	PIU_AID
#define	PIU_DEV_COOKIE(n) (struct piu_cookie *)&piu_dev[PIU_LEAF(n)]
#define	PIU_MSI_COOKIE(n) (struct piu_msi_cookie *)&piu_msi[PIU_LEAF(n)]
#define	PIU_ERR_COOKIE(n) (struct piu_err_cookie *)&piu_err[PIU_LEAF(n)]

/*
 * Functions with first arg as devhandle
 */
#define	PIU_DEV_OPS \
	INTR_OPS(piu), MONDO_OPS(NULL), VINO_OPS(NULL), \
		VPCI_OPS(piu), MSI_OPS(piu), PERF_OPS(piu)

/*
 * Functions with first arg as vINO
 */
#define	PIU_INT_OPS \
	INTR_OPS(NULL), MONDO_OPS(piu), VINO_OPS(piu), \
		VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)

/*
 * MSI functions
 */
#define	PIU_MSI_OPS \
		INTR_OPS(NULL), MONDO_OPS(piu_msi), VINO_OPS(piu), \
		VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)

/*
 * Piu Error INOs
 */
#define	PIU_ERR_OPS \
	INTR_OPS(NULL), MONDO_OPS(piu_err), VINO_OPS(piu_err), \
		VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)

/*
 * FPGA INOs
 */
#ifdef CONFIG_FPGA_UART

#define	FPGA_UART_COOKIE	(struct fpga_uart_cookie *)&fpga_uart_dev

#define	FPGA_UART_OPS \
	INTR_OPS(NULL), MONDO_OPS(fpga_uart), VINO_OPS(fpga_uart), \
		VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)

#else /* !CONFIG_FPGA_UART */

#define	FPGA_UART_OPS	NULL_DEV_OPS

#define	FPGA_UART_COOKIE	0

#endif /* !CONFIG_FPGA_UART */

#define	VINO_HANDLER_PIU(n) \
	/* Standard INOs from devices */		      \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 00 - 01 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 02 - 03 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 04 - 05 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 06 - 07 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 08 - 09 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 10 - 11 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 12 - 13 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 14 - 15 */ \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 16 - 17 */ \
	DEVOPS_RESERVED, DEVOPS_FPGA,		/* 18 - 19 */ \
	/* INTx emulation */				      \
	DEVOPS_INT_PIU(n), DEVOPS_INT_PIU(n),	/* 20 - 21 */ \
	DEVOPS_INT_PIU(n), DEVOPS_INT_PIU(n),	/* 22 - 23 */ \
	/* MSI QUEUEs */				      \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 24 - 25 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 26 - 27 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 28 - 29 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 30 - 31 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 32 - 33 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 34 - 35 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 36 - 37 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 38 - 39 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 40 - 41 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 42 - 43 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 44 - 45 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 46 - 47 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 48 - 49 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 50 - 51 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 52 - 53 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 54 - 55 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 56 - 57 */ \
	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n),	/* 58 - 59 */ \
	/* I2C Interrupts */				      \
	DEVOPS_RESERVED, DEVOPS_RESERVED,	/* 60 - 61 */ \
	/* Error Interrupts */				      \
	DEVOPS_ERR_PIU(n), DEVOPS_ERR_PIU(n)	/* 62 - 63 */


#else /* !CONFIG_PIU */

#define	PIU_DEV_COOKIE(n) 0
#define	PIU_MSI_COOKIE(n) 0
#define	PIU_ERR_COOKIE(n) 0
#define	PIU_DEV_OPS	NULL_DEV_OPS
#define	PIU_INT_OPS	NULL_DEV_OPS
#define	PIU_MSI_OPS	NULL_DEV_OPS
#define	PIU_ERR_OPS	NULL_DEV_OPS

#endif /* !CONFIG_PIU */

#ifdef __cplusplus
}
#endif

#endif /* _PLATFORM_VDEV_OPS_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: vdev_ops.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _PLATFORM_VDEV_OPS_H
	50	#define _PLATFORM_VDEV_OPS_H
	51
	52	#pragma ident "@(#)vdev_ops.h 1.1 07/05/03 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	/*
	59	* Devops assignments to various nexii
	60	*/
	61
	62	#define DEVOPS_RESERVED 0
	63
	64	#ifdef CONFIG_PIU
65	#define DEVOPS_PIU(n) 1
66	#define DEVOPS_INT_PIU(n) 2
67	#define DEVOPS_MSI_PIU(n) 3
68	#define DEVOPS_ERR_PIU(n) 4
69	#else /* CONFIG_PIU */
70	#define DEVOPS_PIU(n) DEVOPS_RESERVED
71	#define DEVOPS_INT_PIU(n) DEVOPS_RESERVED
72	#define DEVOPS_MSI_PIU(n) DEVOPS_RESERVED
73	#define DEVOPS_ERR_PIU(n) DEVOPS_RESERVED
74	#endif /* CONFIG_PIU */
75
76	#define DEVOPS_NIU 5
77	#define DEVOPS_VDEV 6
78	#define DEVOPS_CDEV 7
79
80	#ifdef CONFIG_FPGA_UART
81	#define DEVOPS_FPGA 8
82	#else /* !CONFIG_FPGA_UART */
83	#define DEVOPS_FPGA DEVOPS_RESERVED
84	#endif /* !CONFIG_FPGA_UART */
85
86	/*
87	* NIU nexus
88	*/
89	#define NIU_COOKIE ((void *)&niu_dev)
90
91	#define VINO_HANDLER_NIU \
92	DEVOPS_NIU, DEVOPS_NIU, /* 00 - 01 */ \
93	DEVOPS_NIU, DEVOPS_NIU, /* 02 - 03 */ \
94	DEVOPS_NIU, DEVOPS_NIU, /* 04 - 05 */ \
95	DEVOPS_NIU, DEVOPS_NIU, /* 06 - 07 */ \
96	DEVOPS_NIU, DEVOPS_NIU, /* 08 - 09 */ \
97	DEVOPS_NIU, DEVOPS_NIU, /* 10 - 11 */ \
98	DEVOPS_NIU, DEVOPS_NIU, /* 12 - 13 */ \
99	DEVOPS_NIU, DEVOPS_NIU, /* 14 - 15 */ \
100	DEVOPS_NIU, DEVOPS_NIU, /* 16 - 17 */ \
101	DEVOPS_NIU, DEVOPS_NIU, /* 18 - 19 */ \
102	DEVOPS_NIU, DEVOPS_NIU, /* 20 - 21 */ \
103	DEVOPS_NIU, DEVOPS_NIU, /* 22 - 23 */ \
104	DEVOPS_NIU, DEVOPS_NIU, /* 24 - 25 */ \
105	DEVOPS_NIU, DEVOPS_NIU, /* 26 - 27 */ \
106	DEVOPS_NIU, DEVOPS_NIU, /* 28 - 29 */ \
107	DEVOPS_NIU, DEVOPS_NIU, /* 30 - 31 */ \
108	DEVOPS_NIU, DEVOPS_NIU, /* 32 - 33 */ \
109	DEVOPS_NIU, DEVOPS_NIU, /* 34 - 35 */ \
110	DEVOPS_NIU, DEVOPS_NIU, /* 36 - 37 */ \
111	DEVOPS_NIU, DEVOPS_NIU, /* 38 - 39 */ \
112	DEVOPS_NIU, DEVOPS_NIU, /* 40 - 41 */ \
113	DEVOPS_NIU, DEVOPS_NIU, /* 42 - 33 */ \
114	DEVOPS_NIU, DEVOPS_NIU, /* 44 - 45 */ \
115	DEVOPS_NIU, DEVOPS_NIU, /* 46 - 47 */ \
116	DEVOPS_NIU, DEVOPS_NIU, /* 48 - 49 */ \
117	DEVOPS_NIU, DEVOPS_NIU, /* 50 - 51 */ \
118	DEVOPS_NIU, DEVOPS_NIU, /* 52 - 53 */ \
119	DEVOPS_NIU, DEVOPS_NIU, /* 54 - 55 */ \
120	DEVOPS_NIU, DEVOPS_NIU, /* 56 - 57 */ \
121	DEVOPS_NIU, DEVOPS_NIU, /* 58 - 59 */ \
122	DEVOPS_NIU, DEVOPS_NIU, /* 60 - 61 */ \
123	DEVOPS_NIU, DEVOPS_NIU /* 62 - 63 */
124
125	#define NIU_OPS \
126	INTR_OPS(niu), MONDO_OPS(NULL), VINO_OPS(niu), \
127	VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)
128
129
130	/*
131	* Piu nexus
132	*/
133	#ifdef CONFIG_PIU
134
135	#define PIU_LEAF(n) PIU_AID
136	#define PIU_DEV_COOKIE(n) (struct piu_cookie *)&piu_dev[PIU_LEAF(n)]
137	#define PIU_MSI_COOKIE(n) (struct piu_msi_cookie *)&piu_msi[PIU_LEAF(n)]
138	#define PIU_ERR_COOKIE(n) (struct piu_err_cookie *)&piu_err[PIU_LEAF(n)]
139
140	/*
141	* Functions with first arg as devhandle
142	*/
143	#define PIU_DEV_OPS \
144	INTR_OPS(piu), MONDO_OPS(NULL), VINO_OPS(NULL), \
145	VPCI_OPS(piu), MSI_OPS(piu), PERF_OPS(piu)
146
147	/*
148	* Functions with first arg as vINO
149	*/
150	#define PIU_INT_OPS \
151	INTR_OPS(NULL), MONDO_OPS(piu), VINO_OPS(piu), \
152	VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)
153
154	/*
155	* MSI functions
156	*/
157	#define PIU_MSI_OPS \
158	INTR_OPS(NULL), MONDO_OPS(piu_msi), VINO_OPS(piu), \
159	VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)
160
161	/*
162	* Piu Error INOs
163	*/
164	#define PIU_ERR_OPS \
165	INTR_OPS(NULL), MONDO_OPS(piu_err), VINO_OPS(piu_err), \
166	VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)
167
168	/*
169	* FPGA INOs
170	*/
171	#ifdef CONFIG_FPGA_UART
172
173	#define FPGA_UART_COOKIE (struct fpga_uart_cookie *)&fpga_uart_dev
174
175	#define FPGA_UART_OPS \
176	INTR_OPS(NULL), MONDO_OPS(fpga_uart), VINO_OPS(fpga_uart), \
177	VPCI_OPS(NULL), MSI_OPS(NULL), PERF_OPS(NULL)
178
179	#else /* !CONFIG_FPGA_UART */
180
181	#define FPGA_UART_OPS NULL_DEV_OPS
182
183	#define FPGA_UART_COOKIE 0
184
185	#endif /* !CONFIG_FPGA_UART */
186
187	#define VINO_HANDLER_PIU(n) \
188	/* Standard INOs from devices */ \
189	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 00 - 01 */ \
190	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 02 - 03 */ \
191	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 04 - 05 */ \
192	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 06 - 07 */ \
193	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 08 - 09 */ \
194	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 10 - 11 */ \
195	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 12 - 13 */ \
196	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 14 - 15 */ \
197	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 16 - 17 */ \
198	DEVOPS_RESERVED, DEVOPS_FPGA, /* 18 - 19 */ \
199	/* INTx emulation */ \
200	DEVOPS_INT_PIU(n), DEVOPS_INT_PIU(n), /* 20 - 21 */ \
201	DEVOPS_INT_PIU(n), DEVOPS_INT_PIU(n), /* 22 - 23 */ \
202	/* MSI QUEUEs */ \
203	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 24 - 25 */ \
204	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 26 - 27 */ \
205	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 28 - 29 */ \
206	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 30 - 31 */ \
207	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 32 - 33 */ \
208	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 34 - 35 */ \
209	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 36 - 37 */ \
210	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 38 - 39 */ \
211	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 40 - 41 */ \
212	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 42 - 43 */ \
213	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 44 - 45 */ \
214	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 46 - 47 */ \
215	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 48 - 49 */ \
216	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 50 - 51 */ \
217	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 52 - 53 */ \
218	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 54 - 55 */ \
219	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 56 - 57 */ \
220	DEVOPS_MSI_PIU(n), DEVOPS_MSI_PIU(n), /* 58 - 59 */ \
221	/* I2C Interrupts */ \
222	DEVOPS_RESERVED, DEVOPS_RESERVED, /* 60 - 61 */ \
223	/* Error Interrupts */ \
224	DEVOPS_ERR_PIU(n), DEVOPS_ERR_PIU(n) /* 62 - 63 */
225
226
227	#else /* !CONFIG_PIU */
228
229	#define PIU_DEV_COOKIE(n) 0
230	#define PIU_MSI_COOKIE(n) 0
231	#define PIU_ERR_COOKIE(n) 0
232	#define PIU_DEV_OPS NULL_DEV_OPS
233	#define PIU_INT_OPS NULL_DEV_OPS
234	#define PIU_MSI_OPS NULL_DEV_OPS
235	#define PIU_ERR_OPS NULL_DEV_OPS
236
237	#endif /* !CONFIG_PIU */
238
239	#ifdef __cplusplus
240	}
241	#endif
242
243	#endif /* _PLATFORM_VDEV_OPS_H */