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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / vpiu_errs.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: vpiu_errs.h
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49#ifndef _NIAGARA_VPIU_ERRS_H
50#define _NIAGARA_VPIU_ERRS_H
51
52#pragma ident "@(#)vpiu_errs.h 1.6 07/07/30 SMI"
53
54#ifdef __cplusplus
55extern "C" {
56#endif
57
58/*
59 * Macro to generate unique error handle
60 * and load some of the diag ereport and sun4v erpt
61 * entries that are common to mondo 0x62 and 0x63.
62 * %g1 - piu cookie
63 * %g2 - r_piu_e_rpt
64 * %g3 - IGN
65 * %g4 - INO
66 * %g5 - scratch
67 * %g6 - scratch
68 * %g7 - data0
69 */
70
71/* BEGIN CSTYLED */
72#define GEN_ERR_HNDL_SETUP_ERPTS(PIU_COOKIE, PIU_rpt, IGN, INO, scr1, \
73 scr2, DATA0) \
74 .pushlocals ;\
75 set PIU_COOKIE_DMU_ERPT, scr1 ;\
76 set DMU_INTERNAL_INT, scr2 ;\
77 cmp scr2, INO ;\
78 beq,a,pt %xcc, 1f ;\
79 set PIU_COOKIE_PEU_ERPT, scr1 ;\
801: ;\
81 add PIU_COOKIE, scr1, PIU_rpt ;\
82 GEN_SEQ_NUMBER(scr1, scr2); ;\
83 /* store the error handle in the error report */ ;\
84 stx scr1, [PIU_rpt + PCIERPT_EHDL] /* store ehdlin erpt */ ;\
85 stx scr1, [PIU_rpt + PCIERPT_SUN4V_EHDL] ;\
86 stx DATA0, [PIU_rpt + PCIERPT_SYSINO] ;\
87 st INO, [PIU_rpt + PCIERPT_MONDO_NUM] ;\
88 st IGN, [PIU_rpt + PCIERPT_AGENTID] ;\
89 /* save the TOD/STICK count */ ;\
90 ROOT_STRUCT(scr1) ;\
91 ldx [scr1 + CONFIG_TOD], scr1 ;\
92 brnz,a,pn scr1, 1f ;\
93 ldx [scr1], scr1 /* aborted if no TOD */ ;\
941: rd STICK, scr2 /* stick */ ;\
95 stx scr1, [PIU_rpt + PCIERPT_FPGA_TOD] ;\
96 stx scr2, [PIU_rpt + PCIERPT_STICK] ;\
97 stx scr2, [PIU_rpt + PCIERPT_SUN4V_STICK] ;\
98 rdhpr %hver, scr1 /* read cpu version */ ;\
99 stx scr1, [PIU_rpt + PCIERPT_CPUVER] ;\
100 set ERPT_TYPE_VPCI, scr2 ;\
101 stx scr2, [PIU_rpt + PCIERPT_REPORT_TYPE_62] ;\
102 .poplocals ;\
103
104#define CLEAR_PIU_INTERRUPT(PIU_COOKIE, MONDO, reg1) \
105 ldx [PIU_COOKIE + PIU_COOKIE_INTCLR], reg1 ;\
106 stx %g0, [reg1 + (MONDO<<3)]
107
108#define GENERATE_FMA_REPORT \
109 mov r_piu_e_rpt, %g1 ;\
110 ba,a generate_fma_report ;\
111 .empty
112
113
114#define PEU_ERR_MONDO_OFFSET 8
115#define DMU_ERR_MONDO_OFFSET 0
116
117/* mondo 63 */
118#define PEU_ERR_MONDO_EREPORT(PIU_COOKIE, PIU_rpt, reg1, reg2) \
119 ldx [PIU_COOKIE + PIU_COOKIE_VIRTUAL_INTMAP], reg2 ;\
120 add reg2, PEU_ERR_MONDO_OFFSET, reg2 ;\
121 ldub [reg2], reg1 ;\
122 brnz reg1, generate_guest_report /* yes, send a ereport*/;\
123 nop
124
125/* mondo 62 */
126#define DMU_ERR_MONDO_EREPORT(PIU_COOKIE, PIU_rpt, reg1, reg2) \
127 ldx [PIU_COOKIE + PIU_COOKIE_VIRTUAL_INTMAP], reg2 ;\
128 add reg2, DMU_ERR_MONDO_OFFSET, reg2 ;\
129 ldub [reg2], reg1 ;\
130 brnz reg1, generate_guest_report /* yes, send a ereport*/;\
131 nop
132
133/* DESC.BLOCK bits 31:28 */
134#define HOSTBUS (1LL << 28)
135#define MMU (2LL << 28)
136#define INTR (3LL << 28)
137#define PCI (4LL << 28)
138#define BLK_UNKOWN (0xeLL << 28)
139
140/* HOSTBUS.op */
141#define PIO (1LL << 24)
142#define DMA (2LL << 24)
143#define OP_UNKNOWN (0xeLL << 24)
144
145/* MMU.op */
146#define TRANSLATION (1LL << 24)
147#define BYPASS (2LL << 24)
148#define TABLEWALK (3LL << 24)
149
150/* INTR.op */
151#define MSI32 (1LL << 24)
152#define MSI64 (2LL << 24)
153#define MSIQ (3LL << 24)
154#define PCIEMSG (4LL << 24)
155#define INT_OP_UNKNOWN (0xeLL << 24)
156
157/* phase */
158#define ADDR (1LL << 20)
159#define PDATA (2LL << 20)
160#define PHASE_UNKNOWN (0xeLL << 20)
161#define PHASE_IRRELEVANT (0xfLL << 20)
162
163/* conditions */
164#define ILL (1LL << 16)
165#define UNMAP (2LL << 16)
166#define INT (3LL << 16)
167#define UE (4LL << 16)
168#define PROT (5LL << 16)
169#define INV (6LL << 16)
170#define OV (5LL << 16)
171#define TO (5LL << 16)
172#define COND_UNKNOWN (0xeLL << 16)
173#define COND_IRRELEVENT (0xfLL << 16)
174
175/* directions */
176#define READ (1LL << 12)
177#define WRITE (2LL << 12)
178#define RDRW (3LL << 12)
179#define INGRESS (4LL << 12)
180#define EGRESS (5LL << 12)
181#define LINK (6LL << 12)
182#define DIR_UNKNOWN (0xeLL << 12)
183#define DIR_IRRELEVANT (0xfLL << 12)
184
185/* flags */
186#define SIZE (1LL << 0) /* size of the memory region affected */
187#define P (1LL << 0) /* PCI Status Register */
188#define M (1LL << 1) /* address field contains memory addr (RA) */
189#define E (1LL << 1) /* PCIe Status Register */
190#define D (1LL << 2) /* address field is a DMA virtual address */
191#define U (1LL << 2) /* UE Status reg */
192#define RST (1LL << 3) /* restartable */
193#define C (1LL << 3) /* reserved(note: CE Status Register */
194#define H (1LL << 4) /* contain PCIE headers or HDR1 */
195#define I (1LL << 5) /* HDR2 */
196#define R (1LL << 6) /* Root error status reg */
197#define S (1LL << 7) /* error source reg */
198#define Z (1LL << 8) /* error requires clearing before re-arm */
199#define STOP (1LL << 11) /* HV detects that error info is lost, ask guest to panic */
200
201
202/* PCI Express epkt bits */
203/* UE bits */
204#define TRAINING_ERROR (1LL << 0)
205#define DATA_LINK_ERROR (1LL << 4)
206#define POISONED_TLP (1LL << 12)
207#define FLOW_CONTROL_ERROR (1LL << 13)
208#define COMPLETION_TIMEOUT (1LL << 14)
209#define COMPLETER_ABORT (1LL << 15)
210#define UNEXPECTED_COMPLETION (1LL << 16)
211#define RECEIVER_OVERFLOW (1LL << 17)
212#define MALFORMED_TLP (1LL << 18)
213#define ECRC_ERROR (1LL << 19)
214#define UNSUPPORTED_REQUEST (1LL << 20)
215
216/* CE bits */
217#define RECEIVER_ERROR (1LL << 0)
218#define BAD_TLP (1LL << 6)
219#define BAD_DLLP (1LL << 7)
220#define REPLAY_NUM_ROLLOVER (1LL << 8)
221#define REPLAY_TIMER_TIMEOUT (1LL << 12)
222
223/* UE/CE bits */
224#define IS (1LL << 3) /* Interrupt Status */
225#define MDP (1LL << 8) /* Master Data Parity Error */
226#define ST (1LL << 11) /* Signaled Target Abort */
227#define RT (1LL << 12) /* Received Target Abort */
228#define RM (1LL << 13) /* Received Master Abort */
229#define SS (1LL << 14) /* Signaled System Error */
230#define DP (1LL << 15) /* Detected Parity Error */
231
232/*
233 * test bits for the IMU Interrupt Status Register
234 * (0x631010)
235 */
236
237#define IMU_SPARE_1_S (1LL << 43)
238#define IMU_SPARE_0_S (1LL << 42)
239#define IMU_EQ_OVER_S (1LL << 41)
240#define IMU_EQ_NOT_EN_S (1LL << 40)
241#define IMU_MSI_MAL_ERR_S (1LL << 39)
242#define IMU_MSI_PAR_ERR_S (1LL << 38)
243#define IMU_PMEACK_MES_NOT_EN_S (1LL << 37)
244#define IMU_PMPME_MES_NOT_EN_S (1LL << 36)
245#define IMU_FATAL_MES_NOT_EN_S (1LL << 35)
246#define IMU_NONFATAL_MES_NOT_EN_S (1LL << 34)
247#define IMU_COR_MES_NOT_EN_S (1LL << 33)
248#define IMU_MSI_NOT_EN_S (1LL << 32)
249#define IMU_SPARE_1_P (1LL << 11)
250#define IMU_SPARE_0_P (1LL << 10)
251#define IMU_EQ_OVER_P (1LL << 9)
252#define IMU_EQ_NOT_EN_P (1LL << 8)
253#define IMU_MSI_MAL_ERR_P (1LL << 7)
254#define IMU_MSI_PAR_ERR_P (1LL << 6)
255#define IMU_PMEACK_MES_NOT_EN_P (1LL << 5)
256#define IMU_PMPME_MES_NOT_EN_P (1LL << 4)
257#define IMU_FATAL_MES_NOT_EN_P (1LL << 3)
258#define IMU_NONFATAL_MES_NOT_EN_P (1LL << 2)
259#define IMU_COR_MES_NOT_EN_P (1LL << 1)
260#define IMU_MSI_NOT_EN_P (1LL << 0)
261
262/* test bits for the MMUInterrupt Status Register (0x00641010) */
263#define MMU_SUN4V_KEY_ERR_S (1LL << 52)
264#define MMU_VA_ADJ_UF_S (1LL << 51)
265#define MMU_VA_OOR_S (1LL << 50)
266#define MMU_IOTSBDESC_DPE_S (1LL << 49)
267#define MMU_IOTSBDESC_INV_S (1LL << 48)
268#define MMU_TBW_DPE_S (1LL << 47)
269#define MMU_TBW_ERR_S (1LL << 46)
270#define MMU_TBW_UDE_S (1LL << 45)
271#define MMU_TBW_DME_S (1LL << 44)
272#define MMU_SPARE3_S (1LL << 43)
273#define MMU_SPARE2_S (1LL << 42)
274#define MMU_TTC_CAE_S (1LL << 41)
275#define MMU_TTC_DPE_S (1LL << 40)
276#define MMU_TTE_PRT_S (1LL << 39)
277#define MMU_TTEINV_S (1LL << 38)
278#define MMU_TRN_OOR_S (1LL << 37)
279#define MMU_TRN_ERR_S (1LL << 36)
280#define MMU_SPARE1_S (1LL << 35)
281#define MMU_INV_PG_SZ_S (1LL << 34)
282#define MMU_BYP_OOR_S (1LL << 33)
283#define MMU_BYP_ERR_S (1LL << 32)
284#define MMU_SUN4V_KEY_ERR_P (1LL << 20)
285#define MMU_VA_ADJ_UF_P (1LL << 19)
286#define MMU_VA_OOR_P (1LL << 18)
287#define MMU_IOTSBDESC_DPE_P (1LL << 17)
288#define MMU_IOTSBDESC_INV_P (1LL << 16)
289#define MMU_TBW_DPE_P (1LL << 15)
290#define MMU_TBW_ERR_P (1LL << 14)
291#define MMU_TBW_UDE_P (1LL << 13)
292#define MMU_TBW_DME_P (1LL << 12)
293#define MMU_SPARE3_P (1LL << 11)
294#define MMU_SPARE2_P (1LL << 10)
295#define MMU_TTC_CAE_P (1LL << 9)
296#define MMU_TTC_DPE_P (1LL << 8)
297#define MMU_TTE_PRT_P (1LL << 7)
298#define MMU_TTE_INV_P (1LL << 6)
299#define MMU_TRN_OOR_P (1LL << 5)
300#define MMU_TRN_ERR_P (1LL << 4)
301#define MMU_SPARE1_P (1LL << 3)
302#define MMU_INV_PG_SZ_P (1LL << 2)
303#define MMU_BYP_OOR_P (1LL << 1)
304#define MMU_BYP_ERR_P (1LL << 0)
305
306/* ILU Interrupt Status Register (0x00651010, 0x00751010) */
307#define ILU_SPARE3_S (1LL << 39)
308#define ILU_SPARE2_S (1LL << 38)
309#define ILU_SPARE1_S (1LL << 37)
310#define ILU_IHB_PE_S (1LL << 36)
311#define ILU_SPARE3_P (1LL << 7)
312#define ILU_SPARE2_P (1LL << 6)
313#define ILU_SPARE1_P (1LL << 5)
314#define ILU_IHB_PE_P (1LL << 4)
315
316/* DMU Core and Block Error Status Register (0x00631808 / 0x0) */
317#define MMU_BIT (1LL << 1)
318#define IMU_BIT (1LL << 0)
319
320/* PEU Core and Block Interrupt Status Register (0x00651808 / 0x0) */
321#define ILU_BIT (1LL << 3)
322#define UE_BIT (1LL << 2)
323#define CE_BIT (1LL << 1)
324#define OE_BIT (1LL << 0)
325
326/* PEU Uncorrectable Error Status Clear Register (0x00691018, 0x00791018) */
327#define PEU_UR_S (1LL << 52)
328#define PEU_MFP_S (1LL << 50)
329#define PEU_ROF_S (1LL << 49)
330#define PEU_UC_S (1LL << 48)
331#define PEU_SPARE1_S (1LL << 47)
332#define PEU_CTO_S (1LL << 46)
333#define PEU_FCP_S (1LL << 45)
334#define PEU_PP_S (1LL << 44)
335#define PEU_DLP_S (1LL << 36)
336#define PEU_SPARE0_S (1LL << 32)
337#define PEU_UR_P (1LL << 20)
338#define PEU_MFP_P (1LL << 18)
339#define PEU_ROF_P (1LL << 17)
340#define PEU_UC_P (1LL << 16)
341#define PEU_SPARE1_P (1LL << 15)
342#define PEU_CTO_P (1LL << 14)
343#define PEU_FCP_P (1LL << 13)
344#define PEU_PP_P (1LL << 12)
345#define PEU_DLP_P (1LL << 4)
346#define PEU_SPARE0_P (1LL << 0)
347
348/* PEU Correctable Error Status Reg (0x6a1018, 0x7a1018) */
349#define PEU_CE_RTO_S (1LL << 44)
350#define PEU_CE_RNR_S (1LL << 40)
351#define PEU_CE_BDP_S (1LL << 39)
352#define PEU_CE_BTP_S (1LL << 38)
353#define PEU_CE_RE_S (1LL << 32)
354#define PEU_CE_RTO_P (1LL << 12)
355#define PEU_CE_RNR_P (1LL << 8)
356#define PEU_CE_BDP_P (1LL << 7)
357#define PEU_CE_BTP_P (1LL << 6)
358#define PEU_CE_RE_P (1LL << 0)
359
360/* PEU Other Events Status Register (0x681010, 0x781010) */
361#define PEU_O_SPARE_S (1LL << 55)
362#define PEU_O_MFC_S (1LL << 54)
363#define PEU_O_CTO_S (1LL << 53)
364#define PEU_O_NFP_S (1LL << 52)
365#define PEU_O_LWC_S (1LL << 51)
366#define PEU_O_MRC_S (1LL << 50)
367#define PEU_O_WUC_S (1LL << 49)
368#define PEU_O_RUC_S (1LL << 48)
369#define PEU_O_CRS_S (1LL << 47)
370#define PEU_O_IIP_S (1LL << 46)
371#define PEU_O_EDP_S (1LL << 45)
372#define PEU_O_EHP_S (1LL << 44)
373#define PEU_O_LRS_S (1LL << 42)
374#define PEU_O_LDN_S (1LL << 41)
375#define PEU_O_LUP_S (1LL << 40)
376#define PEU_O_LPU_S (3LL << 38)
377#define PEU_O_ERU_S (1LL << 37)
378#define PEU_O_ERO_S (1LL << 36)
379#define PEU_O_EMP_S (1LL << 35)
380#define PEU_O_EPE_S (1LL << 34)
381#define PEU_O_ERP_S (1LL << 33)
382#define PEU_O_EIP_S (1LL << 32)
383#define PEU_O_SPARE_P (1LL << 23)
384#define PEU_O_MFC_P (1LL << 22)
385#define PEU_O_CTO_P (1LL << 21)
386#define PEU_O_NFP_P (1LL << 20)
387#define PEU_O_LWC_P (1LL << 19)
388#define PEU_O_MRC_P (1LL << 18)
389#define PEU_O_WUC_P (1LL << 17)
390#define PEU_O_RUC_P (1LL << 16)
391#define PEU_O_CRS_P (1LL << 15)
392#define PEU_O_IIP_P (1LL << 14)
393#define PEU_O_EDP_P (1LL << 13)
394#define PEU_O_EHP_P (1LL << 12)
395#define PEU_O_LIN (1LL << 11)
396#define PEU_O_LRS_P (1LL << 10)
397#define PEU_O_LDN_P (1LL << 9)
398#define PEU_O_LUP_P (1LL << 8)
399#define PEU_O_LPU_P (3LL << 6)
400#define PEU_O_ERU_P (1LL << 5)
401#define PEU_O_ERO_P (1LL << 4)
402#define PEU_O_EMP_P (1LL << 3)
403#define PEU_O_EPE_P (1LL << 2)
404#define PEU_O_ERP_P (1LL << 1)
405#define PEU_O_EIP_P (1LL << 0)
406
407/* CXPL Interrupt Status Register (0x6e2118) */
408#define CXPL_EVT_RCV_EN_LB (1LL << 31)
409#define CXPL_EVT_RCV_DIS_LINK (1LL << 30)
410#define CXPL_EVT_RCV_HOT_RST (1LL << 29)
411#define CXPL_EVT_RCV_EIDLE_EXIT (1LL << 28)
412#define CXPL_EVT_RCV_EIDLE (1LL << 27)
413#define CXPL_EVT_RCV_TS1 (1LL << 26)
414#define CXPL_EVT_RCV_TS2 (1LL << 25)
415#define CXPL_EVT_SEND_SKP_B2B (1LL << 24)
416#define CXPL_ERR_OUTSTANDING_SKIP (1LL << 17)
417#define CXPL_ERR_ELASTIC_FIFO_UNDRFLW (1LL << 16)
418#define CXPL_ERR_ELSTC_FIFO_OVRFLW (1LL << 15)
419#define CXPL_ERR_ALIGN (1LL << 14)
420#define CXPL_ERR_KCHAR_DLLP_TLP (1LL << 13)
421#define CXPL_ERR_ILL_END_POS (1LL << 12)
422#define CXPL_ERR_SYNC (1LL << 11)
423#define CXPL_ERR_END_NO_STP_SDP (1LL << 10)
424#define CXPL_ERR_SDP_NO_END (1LL << 9)
425#define CXPL_ERR_STP_NO_END_EDB (1LL << 8)
426#define CXPL_ERR_ILL_PAD_POS (1LL << 7)
427#define CXPL_ERR_MULTI_SDP (1LL << 6)
428#define CXPL_ERR_MULTI_STP (1LL << 5)
429#define CXPL_ERR_ILL_SDP_POS (1LL << 4)
430#define CXPL_ERR_ILL_STP_POS (1LL << 3)
431#define CXPL_ERR_UNSUP_DLLP (1LL << 2)
432#define CXPL_ERR_SRC_TLP (1LL << 1)
433#define CXPL_ERR_SDS_LOS (1LL << 0)
434
435#define PRIMARY_ERRORS_MASK 0xffffffff
436#define SECONDARY_ERRORS_MASK 0xffffffff00000000LL
437#define PRIMARY_TO_SECONDARY_SHIFT_SZ (32)
438#define SECONDARY_TO_PRIMARY_SHIFT_SZ PRIMARY_TO_SECONDARY_SHIFT_SZ
439#define ALIGN_TO_64 (32)
440
441#define PEU_CE_GROUP (PEU_CE_RTO_S | PEU_CE_RNR_S | PEU_CE_BDP_S | \
442 PEU_CE_BTP_S | PEU_CE_RE_S | PEU_CE_RTO_P | \
443 PEU_CE_RNR_P | PEU_CE_BDP_P | PEU_CE_BTP_P | \
444 PEU_CE_RE_P)
445
446#define PEU_CE_GROUP_P (PEU_CE_GROUP & PRIMARY_ERRORS_MASK)
447#define PEU_CE_GROUP_S (PEU_CE_GROUP & SECONDARY_ERRORS_MASK)
448
449#define PEU_OE_RECEIVE_GROUP_P (PEU_O_MFC_P | PEU_O_MRC_P | PEU_O_WUC_P | \
450 PEU_O_CTO_P | PEU_O_RUC_P | PEU_O_CRS_P)
451
452#define PEU_OE_TRANS_GROUP_P (PEU_O_MFC_P | PEU_O_CTO_P | PEU_O_WUC_P | \
453 PEU_O_RUC_P | PEU_O_CRS_P)
454
455#define PEU_OE_NO_DUP_GROUP_P (PEU_O_SPARE_P | PEU_O_MFC_P | PEU_O_CTO_P | \
456 PEU_O_NFP_P | PEU_O_LWC_P | PEU_O_IIP_P | \
457 PEU_O_EDP_P | PEU_O_EHP_P | PEU_O_LRS_P | \
458 PEU_O_LDN_P | PEU_O_LUP_P | PEU_O_LPU_P)
459
460#define PEU_OE_DUP_LLI_P (PEU_O_ERU_P | PEU_O_ERO_P | PEU_O_EMP_P | \
461 PEU_O_EPE_P | PEU_O_ERP_P | PEU_O_EIP_P)
462
463#define PEU_OE_NO_DUP_SVVS_RPT_MSK (PEU_O_IIP_P | PEU_O_EDP_P | \
464 PEU_O_EHP_P)
465
466
467#define PEU_OE_LINK_INTERRUPT_GROUP_P (PEU_O_LIN)
468
469#define PEU_OE_RECV_SVVS_RPT_MSK (PEU_O_MFC_P)
470
471#define PEU_OE_TRANS_SVVS_RPT_MSK (PEU_O_WUC_P | PEU_O_RUC_P)
472
473#define IMU_EQ_NOT_EN_GROUP (IMU_EQ_NOT_EN_P | IMU_EQ_NOT_EN_S)
474
475#define IMU_EQ_OVER_GROUP (IMU_EQ_OVER_P | IMU_EQ_OVER_S)
476
477#define IMU_MSI_MES_GROUP (IMU_MSI_MAL_ERR_P | IMU_MSI_MAL_ERR_S | \
478 IMU_MSI_PAR_ERR_P | IMU_MSI_PAR_ERR_S | \
479 IMU_PMEACK_MES_NOT_EN_P | \
480 IMU_PMEACK_MES_NOT_EN_S | \
481 IMU_PMPME_MES_NOT_EN_P | \
482 IMU_PMPME_MES_NOT_EN_S | \
483 IMU_FATAL_MES_NOT_EN_P | \
484 IMU_FATAL_MES_NOT_EN_S | \
485 IMU_NONFATAL_MES_NOT_EN_P | \
486 IMU_NONFATAL_MES_NOT_EN_S | \
487 IMU_COR_MES_NOT_EN_P | \
488 IMU_COR_MES_NOT_EN_S | \
489 IMU_MSI_NOT_EN_P | IMU_MSI_NOT_EN_S)
490
491#define IMU_EQ_NOT_EN_GROUP_P (IMU_EQ_NOT_EN_GROUP & PRIMARY_ERRORS_MASK)
492#define IMU_EQ_OVER_GROUP_P (IMU_EQ_OVER_GROUP & PRIMARY_ERRORS_MASK)
493#define IMU_MSI_MES_GROUP_P (IMU_MSI_MES_GROUP & PRIMARY_ERRORS_MASK)
494
495#define IMU_EQ_NOT_EN_GROUP_S (IMU_EQ_NOT_EN_GROUP & SECONDARY_ERRORS_MASK)
496#define IMU_EQ_OVER_GROUP_S (IMU_EQ_OVER_GROUP & SECONDARY_ERRORS_MASK)
497#define IMU_MSI_MES_GROUP_S (IMU_MSI_MES_GROUP & SECONDARY_ERRORS_MASK)
498
499#define MMU_ERR_GROUP (MMU_TBW_DPE_S | MMU_TBW_ERR_S | \
500 MMU_TBW_UDE_S | MMU_TBW_DME_S | \
501 MMU_SPARE3_S | MMU_SPARE2_S | \
502 MMU_TTC_CAE_S | MMU_TTC_DPE_S | \
503 MMU_TTE_PRT_S | MMU_TTEINV_S | \
504 MMU_TRN_OOR_S | MMU_TRN_ERR_S | \
505 MMU_SPARE1_S | MMU_INV_PG_SZ_S | \
506 MMU_BYP_OOR_S | MMU_BYP_ERR_S | \
507 MMU_TBW_DPE_P | MMU_TBW_ERR_P | \
508 MMU_TBW_UDE_P | MMU_TBW_DME_P | \
509 MMU_SPARE3_P | MMU_SPARE2_P | \
510 MMU_TTC_CAE_P | MMU_TTC_DPE_P | \
511 MMU_TTE_PRT_P | MMU_TTE_INV_P | \
512 MMU_TRN_OOR_P | MMU_TRN_ERR_P | \
513 MMU_SPARE1_P | MMU_INV_PG_SZ_P | \
514 MMU_BYP_OOR_P | MMU_BYP_ERR_P | \
515 MMU_SUN4V_KEY_ERR_P | MMU_VA_ADJ_UF_P | \
516 MMU_VA_OOR_P | MMU_IOTSBDESC_DPE_P | \
517 MMU_IOTSBDESC_INV_P | MMU_TBW_DPE_P | \
518 MMU_SUN4V_KEY_ERR_S | MMU_VA_ADJ_UF_S | \
519 MMU_VA_OOR_S | MMU_IOTSBDESC_DPE_S | \
520 MMU_IOTSBDESC_INV_S | MMU_TBW_DPE_S)
521
522
523#define MMU_ERR_GROUP_P (MMU_ERR_GROUP & PRIMARY_ERRORS_MASK)
524#define MMU_ERR_GROUP_S (MMU_ERR_GROUP & SECONDARY_ERRORS_MASK)
525
526#define PEU_UE_RECV_GROUP (PEU_UR_P | PEU_UR_S | PEU_MFP_P | PEU_MFP_S | \
527 PEU_ROF_P | PEU_ROF_S | PEU_UC_P | PEU_UC_S | \
528 PEU_PP_P | PEU_PP_S)
529
530#define PEU_UE_TRANS_GROUP (PEU_CTO_P | PEU_CTO_S)
531
532#define PEU_UE_RECV_GROUP_P (PEU_UE_RECV_GROUP & PRIMARY_ERRORS_MASK)
533#define PEU_UE_RECV_GROUP_S (PEU_UE_RECV_GROUP & SECONDARY_ERRORS_MASK)
534#define PEU_UE_TRANS_GROUP_P (PEU_UE_TRANS_GROUP & PRIMARY_ERRORS_MASK)
535#define PEU_UE_TRANS_GROUP_S (PEU_UE_TRANS_GROUP & SECONDARY_ERRORS_MASK)
536
537#define IMU_RDS_ERROR_BITS (IMU_MSI_MAL_ERR_P | IMU_MSI_PAR_ERR_P | \
538 IMU_PMEACK_MES_NOT_EN_P | \
539 IMU_PMPME_MES_NOT_EN_P | \
540 IMU_FATAL_MES_NOT_EN_P | \
541 IMU_NONFATAL_MES_NOT_EN_P | \
542 IMU_COR_MES_NOT_EN_P | IMU_MSI_NOT_EN_P)
543
544#define ILU_GROUP (ILU_SPARE3_P | ILU_SPARE2_P | \
545 ILU_SPARE1_P | ILU_IHB_PE_P | \
546 ILU_SPARE3_S | ILU_SPARE2_S | \
547 ILU_SPARE1_S | ILU_IHB_PE_S)
548
549#define ILU_GROUP_P (ILU_GROUP & PRIMARY_ERRORS_MASK)
550#define ILU_GROUP_S (ILU_GROUP & SECONDARY_ERRORS_MASK)
551
552/* mondo guest epkt macro's */
553#define EPKT_FILL_HEADER(PIU_E_rpt, scr) \
554 ldx [PIU_E_rpt + PCIERPT_EHDL], scr ;\
555 stx scr, [PIU_E_rpt + PCIERPT_SUN4V_EHDL] ;\
556 ldx [PIU_E_rpt + PCIERPT_STICK], scr ;\
557 stx scr, [PIU_E_rpt + PCIERPT_SUN4V_STICK]
558
559/* Mondo 62 related macro's */
560#define LOG_DMC_IMU_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
561 set PIU_DLC_IMU_ICS_IMU_INT_EN_REG, tmp2 ;\
562 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
563 stx tmp1, [PIU_rpt + PCIERPT_IMU_INTERRUPT_ENABLE] ;\
564 set PIU_DLC_IMU_ICS_IMU_ERROR_LOG_EN_REG, tmp1 ;\
565 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
566 stx tmp1, [PIU_rpt + PCIERPT_IMU_ERR_LOG_ENABLE] ;\
567 set PCI_E_IMU_ERR_STAT_SET_ADDR, tmp2 ;\
568 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
569 stx tmp1, [PIU_rpt + PCIERPT_IMU_ERR_STATUS_SET]
570
571
572#define LOG_IMU_SCS_ERROR_LOG_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
573 tmp2) \
574 set PIU_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR, tmp2 ;\
575 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
576 stx tmp1, [PIU_rpt + PCIERPT_IMU_SCS_ERR_LOG]
577
578#define CLEAR_IMU_EQ_NOT_EN_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1,\
579 tmp2) \
580 set PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
581 tmp2 ;\
582 set IMU_EQ_NOT_EN_GROUP_P, tmp1 ;\
583 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
584
585#define CLEAR_IMU_EQ_NOT_EN_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1,\
586 tmp2) \
587 set PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
588 tmp2 ;\
589 set IMU_EQ_NOT_EN_GROUP_P, tmp1 ;\
590 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
591 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
592
593#define CLEAR_IMU_SCS_ERROR_LOG_REGS_S(PIU_rpt, PIU_LEAF_BASE_ADDR, \
594 tmp1, tmp2) \
595 set PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
596 tmp2 ;\
597 set IMU_EQ_NOT_EN_GROUP_P, tmp1 ;\
598 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ , tmp1 ;\
599 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
600
601#define LOG_IMU_EQS_ERROR_LOG_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
602 tmp2) \
603 set PIU_DLC_IMU_ICS_IMU_EQS_ERROR_LOG_REG, tmp2 ;\
604 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
605 stx tmp1, [PIU_rpt + PCIERPT_IMU_EQS_ERR_LOG]
606
607#define CLEAR_IMU_EQ_OVER_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
608 tmp2) \
609 set PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
610 tmp2 ;\
611 set IMU_EQ_OVER_GROUP_P, tmp1 ;\
612 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
613
614#define CLEAR_IMU_EQ_OVER_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
615 tmp2) \
616 set PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
617 tmp2 ;\
618 set IMU_EQ_OVER_GROUP_P, tmp1 ;\
619 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
620 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
621
622#define LOG_IMU_RDS_ERROR_LOG_REG(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
623 tmp2) \
624 set PIU_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, tmp2 ;\
625 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
626 stx tmp1, [PIU_rpt + PCIERPT_IMU_RDS_ERR_LOG]
627
628#define CLEAR_IMU_MSI_MES_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
629 tmp2) \
630 set PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
631 tmp2 ;\
632 set IMU_MSI_MES_GROUP_P, tmp1 ;\
633 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
634
635#define CLEAR_IMU_MSI_MES_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
636 tmp2) \
637 set PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
638 tmp2 ;\
639 set IMU_MSI_MES_GROUP_P, tmp1 ;\
640 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
641 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
642
643#define LOG_DMC_MMU_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
644 set PIU_DLC_MMU_CSR_A_LOG_ADDR, tmp2 ;\
645 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
646 stx tmp1, [PIU_rpt + PCIERPT_MMU_ERR_LOG_ENABLE] ;\
647 set PIU_DLC_MMU_INT_EN, tmp2 ;\
648 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
649 stx tmp1, [PIU_rpt + PCIERPT_MMU_INTR_ENABLE] ;\
650 set PCI_E_MMU_ERR_STAT_SET_ADDR, tmp2 ;\
651 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
652 stx tmp1, [PIU_rpt + PCIERPT_MMU_ERR_STATUS_SET]
653
654#define LOG_MMU_TRANS_FAULT_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
655 tmp2) \
656 set PCI_E_MMU_TRANS_FAULT_ADDR, tmp2 ;\
657 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
658 stx tmp1, [PIU_rpt + PCIERPT_MMU_TRANSLATION_FAULT_ADDRESS];\
659 set PIU_DLC_MMU_CSR_A_FLTS_ADDR, tmp2 ;\
660 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
661 stx tmp1, [PIU_rpt + PCIERPT_MMU_TRANSLATION_FAULT_STATUS]
662
663#define CLEAR_MMU_ERR_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
664 .pushlocals ;\
665 /* check for table walk parity error, scrub cache */ ;\
666 set PCI_E_MMU_INT_STAT_ADDR, tmp2 ;\
667 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
668 btst MMU_TTC_DPE_P, tmp1 ;\
669 bnz %xcc, 1f ;\
670 mov -1, tmp2 ;\
671 set PIU_DLC_MMU_INV, tmp1 ;\
672 stx tmp2, [PIU_LEAF_BASE_ADDR + tmp1] ;\
6731: ;\
674 set PCI_E_MMU_ERR_STAT_CL_ADDR, tmp2 ;\
675 set MMU_ERR_GROUP_P, tmp1 ;\
676 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2] ;\
677 .poplocals
678
679#define CLEAR_MMU_ERR_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
680 .pushlocals ;\
681 /* check for table walk parity error, scrub cache */ ;\
682 set PCI_E_MMU_INT_STAT_ADDR, tmp2 ;\
683 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
684 srlx tmp1, SECONDARY_TO_PRIMARY_SHIFT_SZ, tmp1 ;\
685 btst MMU_TTC_DPE_P, tmp1 ;\
686 bnz %xcc, 1f ;\
687 mov -1, tmp2 ;\
688 set PIU_DLC_MMU_INV, tmp1 ;\
689 stx tmp2, [PIU_LEAF_BASE_ADDR + tmp1] ;\
6901: ;\
691 setx MMU_ERR_GROUP_P, tmp2, tmp1 ;\
692 set PCI_E_MMU_ERR_STAT_CL_ADDR, tmp2 ;\
693 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
694 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2] ;\
695 .poplocals
696
697#define LOG_ILU_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
698 set PCI_E_ILU_INT_STAT_ADDR, tmp2 ;\
699 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
700 stx tmp1, [PIU_rpt + PCIERPT_ILU_ERR_LOG_ENABLE] ;\
701 set PCI_E_ILU_INT_ENB_ADDR, tmp2 ;\
702 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
703 stx tmp1, [PIU_rpt + PCIERPT_ILU_INTR_ENABLE] ;\
704 set PCI_E_ILU_ERR_STAT_SET_ADDR, tmp2 ;\
705 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
706 stx tmp1, [PIU_rpt + PCIERPT_ILU_ERR_STATUS_SET]
707
708#define CLEAR_ILU_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
709 set PCI_E_ILU_ERR_STAT_CL_ADDR, tmp2 ;\
710 set ILU_GROUP_P, tmp1 ;\
711 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
712
713/* ILU_IHB_PE_P */
714#define LOG_ILU_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
715 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
716 set (PCI | INGRESS | U), tmp1 ;\
717 sllx tmp1, ALIGN_TO_64, tmp1 ;\
718 add tmp1, IS, tmp1 ;\
719 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
720 set DATA_LINK_ERROR, tmp1 ;\
721 stx tmp1, [PIU_rpt + PCIERPT_WORD4]
722
723#define LOG_ILU_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
724 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
725 set (PCI | INGRESS | U | STOP), tmp1 ;\
726 sllx tmp1, ALIGN_TO_64, tmp1 ;\
727 add tmp1, IS, tmp1 ;\
728 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
729 set DATA_LINK_ERROR, tmp1 ;\
730 stx tmp1, [PIU_rpt + PCIERPT_WORD4]
731
732#define CLEAR_ILU_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
733 set PCI_E_ILU_ERR_STAT_CL_ADDR, tmp2 ;\
734 set ILU_GROUP_P, tmp1 ;\
735 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
736 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
737
738#define LOG_PEU_UE_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
739 set PIU_PLC_TLU_CTB_TLR_UE_LOG, tmp2 ;\
740 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
741 stx tmp1, [PIU_rpt + \
742 PCIERPT_PEU_UE_LOG_ENABLE] ;\
743 set PCI_E_PEU_UE_INT_ENB_ADDR, tmp2 ;\
744 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
745 stx tmp1, [PIU_rpt + \
746 PCIERPT_PEU_UE_INTERRUPT_ENABLE] ;\
747 set PCI_E_PEU_UE_STAT_SET_ADDR, tmp2 ;\
748 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
749 stx tmp1, [PIU_rpt + \
750 PCIERPT_PEU_UE_STATUS_SET]
751
752#define LOG_PEU_UE_RCV_HDR_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
753 tmp2) \
754 set PCI_E_PEU_RUE_HDR1_ADDR, tmp2 ;\
755 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
756 stx tmp1, [PIU_rpt + PCIERPT_PEU_RECEIVE_UE_HEADER1_LOG] ;\
757 set PCI_E_PEU_RUE_HDR2_ADDR, tmp2 ;\
758 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
759 stx tmp1, [PIU_rpt + PCIERPT_PEU_RECEIVE_UE_HEADER2_LOG]
760
761/*
762 * bit 14, PEU_CTO_P PCI | READ | U | H | I
763 * UE/CE Regs = Conpletion Timeout, PCIe Status = IS
764 */
765#define LOG_PEU_UE_TRANS_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
766 tmp2) \
767 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
768 set PCI_E_PEU_UE_INT_STAT_ADDR, tmp2 ;\
769 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
770 .pushlocals ;\
771 set PEU_CTO_P, tmp2 ;\
772 btst tmp2, tmp1 ;\
773 bnz,a,pt %xcc, 1f ;\
774 clr tmp1 ;\
775 ba,a 9f ;\
7761: ;\
777 set (PCI | READ | U | H | I), tmp1 ;\
778 sllx tmp1, ALIGN_TO_64, tmp1 ;\
779 add tmp1, IS, tmp1 ;\
780 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
781 set COMPLETION_TIMEOUT, tmp1 ;\
782 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
783 set PCI_E_PEU_TUE_HDR1_ADDR, tmp2 ;\
784 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
785 stx tmp1, [PIU_rpt + PCIERPT_HDR1] ;\
786 set PCI_E_PEU_TUE_HDR2_ADDR, tmp2 ;\
787 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
7889: ;\
789 .poplocals ;\
790 stx tmp1, [PIU_rpt + PCIERPT_HDR2]
791
792
793#define LOG_PEU_UE_TRANS_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
794 tmp2) \
795 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
796 set PCI_E_PEU_UE_INT_STAT_ADDR, tmp2 ;\
797 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
798 .pushlocals ;\
799 set PEU_CTO_P, tmp2 ;\
800 btst tmp2, tmp1 ;\
801 bnz,a,pn %xcc, 1f ;\
802 clr tmp1 ;\
803 ba,a 8f ;\
8041: ;\
805 set (PCI | READ | U | STOP), tmp1 ;\
806 sllx tmp1, ALIGN_TO_64, tmp1 ;\
807 add tmp1, IS, tmp1 ;\
808 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
809 set COMPLETION_TIMEOUT, tmp1 ;\
810 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
8118: ;\
812 .poplocals
813
814
815#define LOG_PEU_UE_FCP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
816 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
817 set (PCI | LINK | U), tmp1 ;\
818 sllx tmp1, ALIGN_TO_64, tmp1 ;\
819 add tmp1, IS, tmp1 ;\
820 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
821 set FLOW_CONTROL_ERROR, tmp1 ;\
822 stx tmp1, [PIU_rpt + PCIERPT_WORD4]
823
824#define LOG_PEU_UE_FCP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
825 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
826 set (PCI | LINK | U | STOP), tmp1 ;\
827 sllx tmp1, ALIGN_TO_64, tmp1 ;\
828 add tmp1, IS, tmp1 ;\
829 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
830 set FLOW_CONTROL_ERROR, tmp1 ;\
831 stx tmp1, [PIU_rpt + PCIERPT_WORD4]
832
833#define LOG_PEU_UE_DLP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
834 tmp2) \
835 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
836 set (PCI | LINK | U), tmp1 ;\
837 sllx tmp1, ALIGN_TO_64, tmp1 ;\
838 add tmp1, IS, tmp1 ;\
839 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
840 set DATA_LINK_ERROR, tmp1 ;\
841 stx tmp1, [PIU_rpt + PCIERPT_WORD4]
842
843
844#define LOG_PEU_UE_DLP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
845 tmp2) \
846 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
847 set (PCI | LINK | U | STOP), tmp1 ;\
848 sllx tmp1, ALIGN_TO_64, tmp1 ;\
849 add tmp1, IS, tmp1 ;\
850 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
851 set DATA_LINK_ERROR, tmp1 ;\
852 stx tmp1, [PIU_rpt + PCIERPT_WORD4]
853
854#define CLEAR_PEU_UE_FCP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
855 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
856 set PEU_FCP_P, tmp1 ;\
857 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
858
859#define CLEAR_PEU_UE_FCP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
860 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
861 set PEU_FCP_P, tmp1 ;\
862 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
863 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
864
865#define CLEAR_PEU_UE_DLP_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
866 tmp2) \
867 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
868 set PEU_DLP_P, tmp1 ;\
869 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
870
871#define CLEAR_PEU_UE_DLP_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
872 tmp2) ;\
873 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
874 set PEU_DLP_P, tmp1 ;\
875 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
876 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
877
878#define CLEAR_PEU_UE_RECV_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
879 tmp2) ;\
880 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
881 set PEU_UE_RECV_GROUP_P, tmp1 ;\
882 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
883
884#define CLEAR_PEU_UE_RECV_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
885 tmp2) \
886 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
887 set PEU_UE_RECV_GROUP_P, tmp1 ;\
888 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
889 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
890
891#define LOG_PEU_UE_TRANS_HDR_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
892 tmp2) \
893 set PCI_E_PEU_TUE_HDR1_ADDR, tmp2 ;\
894 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
895 stx tmp1, [PIU_rpt + \
896 PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG] ;\
897 set PCI_E_PEU_TUE_HDR2_ADDR, tmp2 ;\
898 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
899 stx tmp1, [PIU_rpt + \
900 PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG]
901
902
903#define CLEAR_PEU_UE_TRANS_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
904 tmp2) \
905 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
906 set PEU_UE_TRANS_GROUP_P, tmp1 ;\
907 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
908
909#define CLEAR_PEU_UE_TRANS_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
910 tmp2) \
911 set PCI_E_PEU_UE_STAT_CL_ADDR, tmp2 ;\
912 set PEU_UE_TRANS_GROUP_P, tmp1 ;\
913 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
914 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
915
916/*
917 * IMU RDS Error Log Register:Offset: 0x00631028
918 *
919 * T [63:58] The lowest 6 bits of the Type of the errored
920 * transaction as seen by the IMU in the RDS pipe stage
921 * L [57:48] The length of the errored transaction.
922 * R [47:32] The REQ ID of the errored transaction.
923 * t [31:24] The TLP tag of the errored transaction.
924 * B [23:16] The Message code of the error, if the error is a message
925 * otherwise the First and Last Byte Enabled if the error is a MSI
926 * x [15:0] the first 2 bytes MSI data if the error is a MSI, (byte 1,
927 * byte 0)
928 *
929 *
930 * 6 5 4 3 2 1 0
931 * 3210987654321098765432109876543210987654321098765432109876543210
932 * TTTTTTLLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBBxxxxxxxxxxxxxxxx
933 *
934 * RDS above, convert to HDR1 below
935 *
936 * 00TTTTTT00000000000000LLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBB
937 *
938 */
939
940
941/*
942 *
943 * IMU SCS Error Log Register:Offset: 0x00631030
944 *
945 * T [63:58] Low 6 bits of the Type of Error transaction as seen
946 * by the IMU SCS.
947 * L [57:48] The length of the errored transaction.
948 * R [47:32] The REQ ID of the errored transaction.
949 * t [31:24] The TLP tag of the errored transaction.
950 * B [23:16] The Message code of the error, if the error is a message
951 * otherwise the First and Last Byte Enabled if the error is a MSI
952 * x [5:0] EQ number that the transaction tried to go into but
953 * was not enabled.
954 *
955 * 6 5 4 3 2 1 0
956 * 3210987654321098765432109876543210987654321098765432109876543210
957 * TTTTTTLLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBB xxxxxx
958 *
959 * SCS above, convert to HDR1 below
960 *
961 * 00TTTTTT00000000000000LLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBB
962 *
963 */
964
965#define FILL_PCIE_HDR_FIELDS_FROM_ERR_LOG(PIU_E_rpt, \
966 PIU_LEAF_BASE_ADDRx, REG1, REG2, ERR_LOG_REG) \
967 set ERR_LOG_REG, REG1 ;\
968 ldx [PIU_LEAF_BASE_ADDRx + REG1], REG2 ;\
969 /* move LRtB into right place */ ;\
970 srlx REG2, 16, REG1 ;\
971 sllx REG1, (63-41), REG1 ;\
972 srlx REG1, (63-41), REG1 ;\
973 /* move T into right place */ ;\
974 srlx REG2, 58, REG2 ;\
975 sllx REG2, 56, REG2 ;\
976 add REG2, REG1, REG1 ;\
977 stx REG1, [PIU_E_rpt + PCIERPT_HDR1]
978/*
979 * Bit 8
980 */
981#define LOG_IMU_EQ_NOT_EN_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, \
982 tmp1, tmp2) \
983 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
984 set (INTR | MSIQ | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT | \
985 H), tmp1 ;\
986 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
987 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
988 FILL_PCIE_HDR_FIELDS_FROM_ERR_LOG(PIU_rpt, PIU_LEAF_BASE_ADDR, \
989 tmp1, tmp2, \
990 PIU_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR);
991
992#define LOG_IMU_EQ_NOT_EN_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, \
993 tmp1, tmp2) \
994 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
995 set (INTR | MSIQ | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT | \
996 STOP), tmp1 ;\
997 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
998 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC]
999
1000#define LOG_IMU_EQ_OVER_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1001 tmp1, tmp2) \
1002 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1003 set (INTR | MSIQ | PHASE_UNKNOWN | OV | DIR_IRRELEVANT), \
1004 tmp1 ;\
1005 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1006 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC]
1007
1008
1009#define LOG_IMU_EQ_OVER_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1010 tmp1, tmp2) \
1011 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1012 set (INTR | MSIQ | PHASE_UNKNOWN | OV | DIR_IRRELEVANT | \
1013 STOP), tmp1 ;\
1014 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1015 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC]
1016
1017#define IMU_RDS_ERR_LOG_MSIINFO_SHIFT (58)
1018#define MSI64BITPATTERN (0x78) /* 1111000 64 bit msi */
1019#define MSI32BITPATTERN (0x2c) /* 1011000 32 bit msi */
1020
1021#define LOG_IMU_MSI_MES_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1022 tmp1, tmp2) \
1023 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1024 .pushlocals ;\
1025 set PCI_E_IMU_INT_STAT_ADDR, tmp2 ;\
1026 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1027 btst IMU_MSI_NOT_EN_P, tmp1 ;\
1028 bnz %xcc, 1f ;\
1029 btst IMU_COR_MES_NOT_EN_P, tmp1 ;\
1030 bnz %xcc, 2f ;\
1031 btst IMU_NONFATAL_MES_NOT_EN_P, tmp1 ;\
1032 bnz %xcc, 2f ;\
1033 btst IMU_FATAL_MES_NOT_EN_P, tmp1 ;\
1034 bnz %xcc, 2f ;\
1035 btst IMU_PMPME_MES_NOT_EN_P, tmp1 ;\
1036 bnz %xcc, 2f ;\
1037 btst IMU_PMEACK_MES_NOT_EN_P, tmp1 ;\
1038 bnz %xcc, 2f ;\
1039 btst IMU_MSI_PAR_ERR_P, tmp1 ;\
1040 bnz %xcc, 4f ;\
1041 btst IMU_MSI_MAL_ERR_P, tmp1 ;\
1042 bnz %xcc, 5f ;\
1043 clr tmp1 ;\
1044 ba,a 9f ;\
1045 .empty ;\
10461: ;\
1047 ldx [PIU_rpt + PCIERPT_IMU_RDS_ERR_LOG], tmp1 ;\
1048 srlx tmp1, IMU_RDS_ERR_LOG_MSIINFO_SHIFT, tmp1 ;\
1049 cmp tmp1, MSI64BITPATTERN /* is it 1111000 - 64 bit msi */;\
1050 bne,pn %xcc, 1f ;\
1051 nop ;\
1052 set (INTR | MSI64 | PHASE_UNKNOWN | ILL | H), tmp1 ;\
1053 ba 8f ;\
1054 sllx tmp1, ALIGN_TO_64, tmp1 ;\
10551: ;\
1056 set (INTR | MSI32 | PHASE_UNKNOWN | ILL | H), tmp1 ;\
1057 ba 8f ;\
1058 sllx tmp1, ALIGN_TO_64, tmp1 ;\
10592: ;\
1060 set (INTR | PCIEMSG | PHASE_UNKNOWN | ILL | INGRESS | H), \
1061 tmp1 ;\
1062 ba 8f ;\
1063 sllx tmp1, ALIGN_TO_64, tmp1 ;\
10644: ;\
1065 ldx [PIU_rpt + PCIERPT_IMU_RDS_ERR_LOG], tmp1 ;\
1066 srlx tmp1, IMU_RDS_ERR_LOG_MSIINFO_SHIFT, tmp1 ;\
1067 cmp tmp1, MSI64BITPATTERN /* is it 1111000 - 64 bit msi */;\
1068 bne,pn %xcc, 1f ;\
1069 nop ;\
1070 set (INTR | MSI64 | PDATA | INT | DIR_UNKNOWN | H), tmp1 ;\
1071 ba 8f ;\
1072 sllx tmp1, ALIGN_TO_64, tmp1 ;\
10731: ;\
1074 cmp tmp1, MSI32BITPATTERN /* is it 1011000 - 32 bit msi */;\
1075 set (INTR | MSI32 | PDATA | INT | DIR_UNKNOWN | H), tmp1 ;\
1076 bne,pn %xcc, 1f ;\
1077 nop ;\
1078 ba 8f ;\
1079 sllx tmp1, ALIGN_TO_64, tmp1 ;\
10801: ;\
1081 set (INTR | INT_OP_UNKNOWN | PDATA | INT | DIR_UNKNOWN | H),\
1082 tmp1 ;\
1083 ba 8f ;\
1084 sllx tmp1, ALIGN_TO_64, tmp1 ;\
10855: ;\
1086 ldx [PIU_rpt + PCIERPT_IMU_RDS_ERR_LOG], tmp1 ;\
1087 srlx tmp1, IMU_RDS_ERR_LOG_MSIINFO_SHIFT, tmp1 ;\
1088 cmp tmp1, MSI64BITPATTERN /* is it 1111000 - 64 bit msi */;\
1089 bne,pn %xcc, 2f ;\
1090 nop ;\
1091 set (INTR | MSI64 | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT | \
1092 H), tmp1 ;\
1093 ba 8f ;\
1094 sllx tmp1, ALIGN_TO_64, tmp1 ;\
10952: ;\
1096 cmp tmp1, MSI32BITPATTERN /* is it 1011000 - 32 bit msi */;\
1097 set (INTR | MSI32 | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT | \
1098 H), tmp1 ;\
1099 bne,pn %xcc, 2f ;\
1100 nop ;\
1101 ba 8f ;\
1102 sllx tmp1, ALIGN_TO_64, tmp1 ;\
11032: ;\
1104 set (INTR | INT_OP_UNKNOWN | PHASE_UNKNOWN | ILL | \
1105 DIR_IRRELEVANT | H), tmp1 ;\
1106 sllx tmp1, ALIGN_TO_64, tmp1 ;\
11078: ;\
1108 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1109 FILL_PCIE_HDR_FIELDS_FROM_ERR_LOG(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1110 tmp1, tmp2, \
1111 PIU_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR) ;\
11129: ;\
1113 .poplocals
1114
1115#define LOG_IMU_MSI_MES_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1116 tmp1, tmp2) \
1117 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1118 .pushlocals ;\
1119 set PCI_E_IMU_INT_STAT_ADDR, tmp2 ;\
1120 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1121 srlx tmp1, SECONDARY_TO_PRIMARY_SHIFT_SZ, tmp1 ;\
1122 btst IMU_MSI_NOT_EN_P, tmp1 ;\
1123 bnz %xcc, 1f ;\
1124 btst IMU_COR_MES_NOT_EN_P, tmp1 ;\
1125 bnz %xcc, 2f ;\
1126 btst IMU_NONFATAL_MES_NOT_EN_P, tmp1 ;\
1127 bnz %xcc, 2f ;\
1128 btst IMU_FATAL_MES_NOT_EN_P, tmp1 ;\
1129 bnz %xcc, 2f ;\
1130 btst IMU_PMPME_MES_NOT_EN_P, tmp1 ;\
1131 bnz %xcc, 2f ;\
1132 btst IMU_PMEACK_MES_NOT_EN_P, tmp1 ;\
1133 bnz %xcc, 2f ;\
1134 btst IMU_MSI_PAR_ERR_P, tmp1 ;\
1135 bnz %xcc, 4f ;\
1136 btst IMU_MSI_MAL_ERR_P, tmp1 ;\
1137 bnz %xcc, 5f ;\
1138 clr tmp1 ;\
1139 ba,a 9f ;\
1140 .empty ;\
11411: ;\
1142 set (INTR | MSI32 | PHASE_UNKNOWN | ILL | STOP), tmp1 ;\
1143 ba 8f ;\
1144 sllx tmp1, ALIGN_TO_64, tmp1 ;\
11452: ;\
1146 set (INTR | PCIEMSG | PHASE_UNKNOWN | ILL | INGRESS | STOP),\
1147 tmp1 ;\
1148 ba 8f ;\
1149 sllx tmp1, ALIGN_TO_64, tmp1 ;\
11504: ;\
1151 set (INTR | OP_UNKNOWN | PDATA | INT | DIR_UNKNOWN | STOP),\
1152 tmp1 ;\
1153 ba 8f ;\
1154 sllx tmp1, ALIGN_TO_64, tmp1 ;\
11555: ;\
1156 set (INTR | OP_UNKNOWN | PHASE_UNKNOWN | ILL | \
1157 DIR_IRRELEVANT | STOP), tmp1 ;\
1158 ba 8f ;\
1159 sllx tmp1, ALIGN_TO_64, tmp1 ;\
11608: ;\
1161 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
11629: ;\
1163 .poplocals
1164
1165/*
1166 * bit 17, PEU_ROF_P PCI | INGRESS | U | H | I
1167 * UE/CE Regs = Receiver Overflow, PCIe Status = IS
1168 * bit 20, PEU_UR_P PCI | INGRESS | U | H | I
1169 * UE/CE Regs = Unsupported Request, PCIe Status = IS
1170 */
1171#define LOG_PEU_UE_RECV_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1172 tmp1, tmp2) \
1173 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1174 set (PCI | INGRESS | U | H | I), tmp1 ;\
1175 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1176 add tmp1, IS, tmp1 ;\
1177 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1178 set PCI_E_PEU_UE_INT_STAT_ADDR, tmp1 ;\
1179 ldx [PIU_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1180 .pushlocals ;\
1181 set PEU_UR_P, tmp1 ;\
1182 btst tmp1, tmp2 ;\
1183 bnz %xcc, 1f ;\
1184 .empty ;\
1185 set PEU_UC_P, tmp1 ;\
1186 btst tmp1, tmp2 ;\
1187 bnz %xcc, 2f ;\
1188 .empty ;\
1189 set PEU_MFP_P, tmp1 ;\
1190 btst tmp1, tmp2 ;\
1191 bnz %xcc, 3f ;\
1192 .empty ;\
1193 set PEU_PP_P, tmp1 ;\
1194 btst tmp1, tmp2 ;\
1195 bnz %xcc, 4f ;\
1196 .empty ;\
1197 set PEU_ROF_P, tmp1 ;\
1198 btst tmp1, tmp2 ;\
1199 bnz %xcc, 5f ;\
1200 clr tmp2 ;\
1201 ba,a 9f ;\
1202 .empty ;\
12031: ;\
1204 set UNSUPPORTED_REQUEST, tmp1 ;\
1205 ba 8f ;\
1206 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12072: ;\
1208 set UNEXPECTED_COMPLETION, tmp1 ;\
1209 ba 8f ;\
1210 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12113: ;\
1212 set MALFORMED_TLP, tmp1 ;\
1213 ba 8f ;\
1214 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12154: ;\
1216 set DP, tmp1 ;\
1217 add tmp1, IS, tmp1 ;\
1218 /* rewrite the 4 bytes containing the PCIe err status */ ;\
1219 /* to include the Detected Parity bit */ ;\
1220 stuw tmp1, [PIU_rpt + (PCIERPT_SUN4V_DESC + 4)] ;\
1221 set POISONED_TLP, tmp1 ;\
1222 ba 8f ;\
1223 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12245: ;\
1225 set RECEIVER_OVERFLOW, tmp1 ;\
1226 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12278: ;\
1228 set PCI_E_PEU_RUE_HDR1_ADDR, tmp1 ;\
1229 ldx [PIU_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1230 stx tmp2, [PIU_rpt + PCIERPT_HDR1] ;\
1231 set PCI_E_PEU_RUE_HDR2_ADDR, tmp1 ;\
1232 ldx [PIU_LEAF_BASE_ADDR + tmp1], tmp2 ;\
12339: ;\
1234 .poplocals ;\
1235 stx tmp2, [PIU_rpt + PCIERPT_HDR2]
1236
1237
1238#define LOG_PEU_UE_RECV_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1239 tmp1, tmp2) \
1240 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1241 set (PCI | INGRESS | U), tmp1 ;\
1242 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1243 add tmp1, IS, tmp1 ;\
1244 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1245 set PCI_E_PEU_UE_INT_STAT_ADDR, tmp1 ;\
1246 ldx [PIU_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1247 .pushlocals ;\
1248 set PEU_UR_P, tmp1 ;\
1249 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1250 btst tmp1, tmp2 ;\
1251 bnz %xcc, 1f ;\
1252 .empty ;\
1253 set PEU_UC_P, tmp1 ;\
1254 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1255 btst tmp1, tmp2 ;\
1256 bnz %xcc, 2f ;\
1257 .empty ;\
1258 set PEU_MFP_P, tmp1 ;\
1259 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1260 btst tmp1, tmp2 ;\
1261 bnz %xcc, 3f ;\
1262 .empty ;\
1263 set PEU_PP_P, tmp1 ;\
1264 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1265 btst tmp1, tmp2 ;\
1266 bnz %xcc, 4f ;\
1267 set PEU_ROF_P, tmp1 ;\
1268 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1269 btst tmp1, tmp2 ;\
1270 bnz %xcc, 5f ;\
1271 clr tmp2 ;\
1272 ba,a 8f ;\
1273 .empty ;\
12741: ;\
1275 set (UNSUPPORTED_REQUEST | STOP), tmp1 ;\
1276 ba 8f ;\
1277 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12782: ;\
1279 set (UNEXPECTED_COMPLETION | STOP), tmp1 ;\
1280 ba 8f ;\
1281 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12823: ;\
1283 set (MALFORMED_TLP | STOP), tmp1 ;\
1284 ba 8f ;\
1285 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12864: ;\
1287 set (DP | STOP), tmp1 ;\
1288 add tmp1, IS, tmp1 ;\
1289 /* rewrite the 4 bytes containing the PCIe err status */ ;\
1290 /* to include the Detected Parity bit */ ;\
1291 stuw tmp1, [PIU_rpt + (PCIERPT_SUN4V_DESC + 4)] ;\
1292 set (POISONED_TLP | STOP), tmp1 ;\
1293 ba 8f ;\
1294 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12955: ;\
1296 set (RECEIVER_OVERFLOW | STOP), tmp1 ;\
1297 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
12988: ;\
1299 .poplocals
1300
1301#define LOG_PEU_CE_GROUP_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
1302 set PIU_PLC_TLU_CTB_TLR_CE_LOG, tmp2 ;\
1303 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1304 stx tmp1, [PIU_rpt + PCIERPT_PEU_CE_LOG_ENABLE] ;\
1305 set PIU_PLC_TLU_CTB_TLR_CE_INT_EN, tmp2 ;\
1306 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1307 stx tmp1, [PIU_rpt + PCIERPT_PEU_CE_INTERRUPT_ENABLE] ;\
1308 set PCI_E_PEU_CE_STAT_SET_ADDR, tmp2 ;\
1309 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1310 stx tmp1, [PIU_rpt + PCIERPT_PEU_CE_STATUS_SET]
1311
1312#define CLEAR_PEU_CE_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
1313 set PEU_CE_GROUP_P, tmp1 ;\
1314 set PCI_E_PEU_CE_STAT_CL_ADDR, tmp2 ;\
1315 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1316
1317#define CLEAR_PEU_CE_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
1318 set PEU_CE_GROUP_P, tmp1 ;\
1319 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1320 set PCI_E_PEU_CE_STAT_CL_ADDR, tmp2 ;\
1321 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1322
1323#define LOG_PEU_CE_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2)\
1324 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1325 .pushlocals ;\
1326 set PCI_E_PEU_CE_INT_STAT_ADDR, tmp2 ;\
1327 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1328 set PEU_CE_RTO_P, tmp1 ;\
1329 btst tmp1, tmp2 ;\
1330 bnz %xcc, 1f ;\
1331 .empty ;\
1332 set PEU_CE_RNR_P, tmp1 ;\
1333 btst tmp1, tmp2 ;\
1334 bnz %xcc, 2f ;\
1335 .empty ;\
1336 set PEU_CE_BDP_P, tmp1 ;\
1337 btst tmp1, tmp2 ;\
1338 bnz %xcc, 3f ;\
1339 btst PEU_CE_BTP_P, tmp2 ;\
1340 bnz %xcc, 4f ;\
1341 .empty ;\
1342 set (PCI | INGRESS | C), tmp1 ;\
1343 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1344 add tmp1, IS, tmp1 ;\
1345 set RECEIVER_ERROR, tmp2 ;\
1346 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1347 ba 8f ;\
1348 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
13491: ;\
1350 set (PCI | EGRESS | C), tmp1 ;\
1351 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1352 add tmp1, IS, tmp1 ;\
1353 set REPLAY_TIMER_TIMEOUT, tmp2 ;\
1354 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1355 ba 8f ;\
1356 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
13572: ;\
1358 set (PCI | EGRESS | C), tmp1 ;\
1359 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1360 add tmp1, IS, tmp1 ;\
1361 set REPLAY_NUM_ROLLOVER, tmp2 ;\
1362 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1363 ba 8f ;\
1364 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
13653: ;\
1366 set (PCI | INGRESS), tmp1 ;\
1367 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1368 add tmp1, IS, tmp1 ;\
1369 set BAD_DLLP, tmp2 ;\
1370 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1371 ba 8f ;\
1372 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
13734: ;\
1374 set (PCI | INGRESS), tmp1 ;\
1375 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1376 add tmp1, IS, tmp1 ;\
1377 set BAD_TLP, tmp2 ;\
1378 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1379 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
13808: ;\
1381 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1382 .poplocals
1383
1384
1385#define LOG_PEU_CE_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2)\
1386 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1387 .pushlocals ;\
1388 set PCI_E_PEU_CE_INT_STAT_ADDR, tmp2 ;\
1389 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1390 set PEU_CE_RTO_P, tmp1 ;\
1391 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1392 btst tmp1, tmp2 ;\
1393 bnz %xcc, 1f ;\
1394 .empty ;\
1395 set PEU_CE_RNR_P, tmp1 ;\
1396 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1397 btst tmp1, tmp2 ;\
1398 bnz %xcc, 2f ;\
1399 .empty ;\
1400 set PEU_CE_BDP_P, tmp1 ;\
1401 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1402 btst tmp1, tmp2 ;\
1403 bnz %xcc, 3f ;\
1404 set PEU_CE_BTP_P, tmp1 ;\
1405 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1406 btst tmp1, tmp2 ;\
1407 bnz %xcc, 4f ;\
1408 .empty ;\
1409 set (PCI | INGRESS | C | STOP), tmp1 ;\
1410 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1411 add tmp1, IS, tmp1 ;\
1412 set RECEIVER_ERROR, tmp2 ;\
1413 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1414 ba 8f ;\
1415 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
14161: ;\
1417 set (PCI | EGRESS | C | STOP), tmp1 ;\
1418 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1419 add tmp1, IS, tmp1 ;\
1420 set REPLAY_TIMER_TIMEOUT, tmp2 ;\
1421 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1422 ba 8f ;\
1423 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
14242: ;\
1425 set (PCI | EGRESS | C | STOP), tmp1 ;\
1426 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1427 add tmp1, IS, tmp1 ;\
1428 set REPLAY_NUM_ROLLOVER, tmp2 ;\
1429 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1430 ba 8f ;\
1431 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
14323: ;\
1433 set (PCI | INGRESS | STOP), tmp1 ;\
1434 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1435 add tmp1, IS, tmp1 ;\
1436 set BAD_DLLP, tmp2 ;\
1437 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1438 ba 8f ;\
1439 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
14404: ;\
1441 set (PCI | INGRESS | STOP), tmp1 ;\
1442 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1443 add tmp1, IS, tmp1 ;\
1444 set BAD_TLP, tmp2 ;\
1445 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1446 stx tmp2, [PIU_rpt + PCIERPT_WORD4] ;\
14478: ;\
1448 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1449 .poplocals
1450
1451#define LOG_PEU_OE_GROUP_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, tmp2) \
1452 set PCI_E_PEU_OTHER_LOG_ENB_ADDR, tmp2 ;\
1453 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1454 stx tmp1, [PIU_rpt + PCIERPT_PEU_OTHER_EVENT_LOG_ENABLE] ;\
1455 set PCI_E_PEU_OTHER_ERR_STAT_SET_ADDR, tmp2 ;\
1456 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1457 stx tmp1, [PIU_rpt + PCIERPT_PEU_OTHER_EVENT_STATUS_SET] ;\
1458 set PCI_E_PEU_OTHER_INT_ENB_ADDR, tmp2 ;\
1459 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1460 stx tmp1, [PIU_rpt + PCIERPT_PEU_OTHER_EVENT_INTR_ENABLE] ;\
1461
1462#define LOG_PEU_OE_INTR_STATUS_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1463 tmp2, MASK) \
1464 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1465 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1466 set MASK, tmp2 ;\
1467 and tmp1, tmp2, tmp1 ;\
1468 stx tmp1, [PIU_rpt + PCIERPT_PEU_OTHER_EVENT_INTR_STATUS] ;\
1469
1470#define LOG_PEU_OE_INTR_STATUS_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1471 tmp2, INTR_MASK) \
1472 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1473 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1474 set INTR_MASK, tmp2 ;\
1475 sllx tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp2 ;\
1476 and tmp1, tmp2, tmp1 ;\
1477 stx tmp1, [PIU_rpt + PCIERPT_PEU_OTHER_EVENT_INTR_STATUS] ;\
1478
1479#define LOG_PEU_OE_RECV_GROUP_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1480 tmp2) \
1481 set PCI_E_PEU_ROE_HDR1_ADDR, tmp2 ;\
1482 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1483 stx tmp1, [PIU_rpt + \
1484 PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG] ;\
1485 set PCI_E_PEU_ROE_HDR2_ADDR, tmp2 ;\
1486 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1487 stx tmp1, [PIU_rpt + \
1488 PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG]
1489
1490#define CLEAR_PEU_OE_RECV_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1491 tmp2) \
1492 set PEU_OE_RECEIVE_GROUP_P, tmp1 ;\
1493 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1494 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1495
1496#define CLEAR_PEU_OE_RECV_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1497 tmp2) \
1498 set PEU_OE_RECEIVE_GROUP_P, tmp1 ;\
1499 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1500 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1501 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1502
1503#define CLEAR_PEU_OE_DUP_LLI_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1504 tmp2) ;\
1505 set PEU_OE_DUP_LLI_P, tmp1 ;\
1506 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1507 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1508
1509#define CLEAR_PEU_OE_DUP_LLI_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1510 tmp2) ;\
1511 set PEU_OE_DUP_LLI_P, tmp1 ;\
1512 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1513 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1514 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1515
1516#define CLEAR_PEU_OE_NO_DUP_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1517 tmp2) \
1518 set PEU_OE_NO_DUP_GROUP_P, tmp1 ;\
1519 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1520 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1521
1522#define CLEAR_PEU_OE_NO_DUP_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1523 tmp2) \
1524 set PEU_OE_NO_DUP_GROUP_P, tmp1 ;\
1525 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1526 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1527 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1528
1529#define LOG_PEU_OE_TRANS_GROUP_REGS(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1530 tmp2) \
1531 set PCI_E_PEU_TOE_HDR1_ADDR, tmp2 ;\
1532 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1533 stx tmp1, [PIU_rpt + \
1534 PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG] ;\
1535 set PCI_E_PEU_TOE_HDR2_ADDR, tmp2 ;\
1536 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1537 stx tmp1, [PIU_rpt + \
1538 PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG]
1539
1540#define LOG_PEU_OE_RECV_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1541 tmp1, tmp2) \
1542 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1543 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1544 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1545 set PEU_O_MFC_P, tmp1 ;\
1546 btst tmp1, tmp2 ;\
1547 .pushlocals ;\
1548 bnz %xcc, 1f ;\
1549 clr tmp1 ;\
1550 ba 8f ;\
1551 nop ;\
15521: ;\
1553 set (PCI | INGRESS | U | H | I), tmp1 ;\
1554 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1555 add tmp1, IS, tmp1 ;\
1556 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1557 set MALFORMED_TLP, tmp1 ;\
1558 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
1559 set PCI_E_PEU_RUE_HDR1_ADDR, tmp1 ;\
1560 ldx [PIU_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1561 stx tmp2, [PIU_rpt + PCIERPT_HDR1] ;\
1562 set PCI_E_PEU_RUE_HDR2_ADDR, tmp1 ;\
1563 ldx [PIU_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1564 stx tmp2, [PIU_rpt + PCIERPT_HDR2] ;\
15658: ;\
1566 .poplocals ;\
1567 nop
1568
1569
1570#define LOG_PEU_OE_RECV_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1571 tmp1, tmp2) \
1572 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1573 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1574 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1575 set PEU_O_MFC_P, tmp1 ;\
1576 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1577 btst tmp1, tmp2 ;\
1578 .pushlocals ;\
1579 bnz %xcc, 1f ;\
1580 clr tmp1 ;\
1581 ba 8f ;\
1582 nop ;\
15831: ;\
1584 set (PCI | INGRESS | U | I | STOP), tmp1 ;\
1585 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1586 add tmp1, IS, tmp1 ;\
1587 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1588 set MALFORMED_TLP, tmp1 ;\
1589 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
15908: ;\
1591 .poplocals ;\
1592 nop
1593
1594#define LOG_PEU_OE_TRANS_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1595 tmp1, tmp2) \
1596 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1597 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1598 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1599 set PEU_O_WUC_P, tmp1 ;\
1600 btst tmp1, tmp2 ;\
1601 .pushlocals ;\
1602 bnz %xcc, 1f ;\
1603 set PEU_O_RUC_P, tmp1 ;\
1604 btst tmp1, tmp2 ;\
1605 bnz %xcc, 2f ;\
1606 clr tmp1 ;\
1607 ba 8f ;\
1608 nop ;\
16091: ;\
1610 set (PCI | WRITE | U), tmp1 ;\
1611 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1612 add tmp1, IS, tmp1 ;\
1613 add tmp1, ST, tmp1 ;\
1614 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1615 set COMPLETER_ABORT, tmp1 ;\
1616 ba 8f ;\
1617 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
16182: ;\
1619 set (PCI | READ | U), tmp1 ;\
1620 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1621 add tmp1, IS, tmp1 ;\
1622 add tmp1, ST, tmp1 ;\
1623 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1624 set COMPLETER_ABORT, tmp1 ;\
1625 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
16268: ;\
1627 .poplocals ;\
1628 nop
1629
1630#define LOG_PEU_OE_TRANS_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, \
1631 tmp1, tmp2) \
1632 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1633 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1634 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1635 set PEU_O_WUC_P, tmp1 ;\
1636 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1637 btst tmp1, tmp2 ;\
1638 .pushlocals ;\
1639 bnz %xcc, 1f ;\
1640 set PEU_O_RUC_P, tmp1 ;\
1641 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1642 btst tmp1, tmp2 ;\
1643 bnz %xcc, 2f ;\
1644 clr tmp1 ;\
1645 ba 8f ;\
1646 nop ;\
16471: ;\
1648 set (PCI | WRITE | U | STOP), tmp1 ;\
1649 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1650 add tmp1, IS, tmp1 ;\
1651 add tmp1, ST, tmp1 ;\
1652 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1653 set COMPLETER_ABORT, tmp1 ;\
1654 ba 8f ;\
1655 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
16562: ;\
1657 set (PCI | READ | U | STOP), tmp1 ;\
1658 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1659 add tmp1, IS, tmp1 ;\
1660 add tmp1, ST, tmp1 ;\
1661 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1662 set COMPLETER_ABORT, tmp1 ;\
1663 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
16648: ;\
1665 .poplocals ;\
1666 nop
1667
1668#define CLEAR_PEU_OE_TRANS_GROUP_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1669 tmp2) \
1670 set PEU_OE_TRANS_GROUP_P, tmp1 ;\
1671 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1672 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1673
1674
1675#define CLEAR_PEU_OE_TRANS_GROUP_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1676 tmp2) \
1677 set PEU_OE_TRANS_GROUP_P, tmp1 ;\
1678 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1679 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, tmp2 ;\
1680 stx tmp1, [PIU_LEAF_BASE_ADDR + tmp2]
1681
1682#define LOG_PEU_OE_NO_DUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1683 tmp2) \
1684 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1685 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1686 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1687 set PEU_O_IIP_P, tmp1 ;\
1688 btst tmp1, tmp2 ;\
1689 .pushlocals ;\
1690 bnz %xcc, 1f ;\
1691 btst tmp1, tmp2 ;\
1692 bnz %xcc, 1f ;\
1693 set PEU_O_EDP_P, tmp1 ;\
1694 btst tmp1, tmp2 ;\
1695 bnz %xcc, 2f ;\
1696 btst tmp1, tmp2 ;\
1697 bnz %xcc, 2f ;\
1698 set PEU_O_EHP_P, tmp1 ;\
1699 btst tmp1, tmp2 ;\
1700 bnz %xcc, 2f ;\
1701 btst tmp1, tmp2 ;\
1702 bnz %xcc, 2f ;\
1703 set PEU_O_LRS_P, tmp1 ;\
1704 btst tmp1, tmp2 ;\
1705 bnz %xcc, 3f ;\
1706 btst tmp1, tmp2 ;\
1707 bnz %xcc, 3f ;\
1708 set PEU_O_LDN_P, tmp1 ;\
1709 btst tmp1, tmp2 ;\
1710 bnz %xcc, 3f ;\
1711 btst tmp1, tmp2 ;\
1712 bnz %xcc, 3f ;\
1713 set PEU_O_LUP_P, tmp1 ;\
1714 btst tmp1, tmp2 ;\
1715 bnz %xcc, 3f ;\
1716 btst tmp1, tmp2 ;\
1717 bnz %xcc, 3f ;\
1718 clr tmp1 ;\
1719 ba 8f ;\
1720 nop ;\
17211: ;\
1722 set (PCI | INGRESS | U), tmp1 ;\
1723 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1724 add tmp1, IS, tmp1 ;\
1725 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1726 set DATA_LINK_ERROR, tmp1 ;\
1727 ba 8f ;\
1728 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
17292: ;\
1730 set (PCI | EGRESS | U), tmp1 ;\
1731 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1732 add tmp1, IS, tmp1 ;\
1733 add tmp1, ST, tmp1 ;\
1734 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1735 set DATA_LINK_ERROR, tmp1 ;\
1736 ba 8f ;\
1737 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
17383: ;\
1739 set (PCI | LINK | U), tmp1 ;\
1740 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1741 add tmp1, IS, tmp1 ;\
1742 add tmp1, ST, tmp1 ;\
1743 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1744 set DATA_LINK_ERROR, tmp1 ;\
1745 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
17468: ;\
1747 .poplocals ;\
1748 nop
1749
1750#define LOG_PEU_OE_NO_DUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1751 tmp2) \
1752 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1753 set PCI_E_PEU_OTHER_INT_STAT_ADDR, tmp2 ;\
1754 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp2 ;\
1755 set PEU_O_IIP_P, tmp1 ;\
1756 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1757 btst tmp1, tmp2 ;\
1758 .pushlocals ;\
1759 bnz %xcc, 1f ;\
1760 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1761 btst tmp1, tmp2 ;\
1762 bnz %xcc, 1f ;\
1763 set PEU_O_EDP_P, tmp1 ;\
1764 btst tmp1, tmp2 ;\
1765 bnz %xcc, 2f ;\
1766 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1767 btst tmp1, tmp2 ;\
1768 bnz %xcc, 2f ;\
1769 set PEU_O_EHP_P, tmp1 ;\
1770 btst tmp1, tmp2 ;\
1771 bnz %xcc, 2f ;\
1772 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1773 btst tmp1, tmp2 ;\
1774 bnz %xcc, 2f ;\
1775 set PEU_O_LRS_P, tmp1 ;\
1776 btst tmp1, tmp2 ;\
1777 bnz %xcc, 3f ;\
1778 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1779 btst tmp1, tmp2 ;\
1780 bnz %xcc, 3f ;\
1781 set PEU_O_LDN_P, tmp1 ;\
1782 btst tmp1, tmp2 ;\
1783 bnz %xcc, 3f ;\
1784 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1785 btst tmp1, tmp2 ;\
1786 bnz %xcc, 3f ;\
1787 set PEU_O_LUP_P, tmp1 ;\
1788 btst tmp1, tmp2 ;\
1789 bnz %xcc, 3f ;\
1790 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1791 btst tmp1, tmp2 ;\
1792 bnz %xcc, 3f ;\
1793 clr tmp1 ;\
1794 ba 8f ;\
1795 nop ;\
17961: ;\
1797 set (PCI | INGRESS | U | STOP), tmp1 ;\
1798 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1799 add tmp1, IS, tmp1 ;\
1800 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1801 set DATA_LINK_ERROR, tmp1 ;\
1802 ba 8f ;\
1803 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
18042: ;\
1805 set (PCI | EGRESS | U | STOP), tmp1 ;\
1806 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1807 add tmp1, IS, tmp1 ;\
1808 add tmp1, ST, tmp1 ;\
1809 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1810 set DATA_LINK_ERROR, tmp1 ;\
1811 ba 8f ;\
1812 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
18133: ;\
1814 set (PCI | LINK | U | STOP), tmp1 ;\
1815 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1816 add tmp1, IS, tmp1 ;\
1817 add tmp1, ST, tmp1 ;\
1818 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
1819 set DATA_LINK_ERROR, tmp1 ;\
1820 stx tmp1, [PIU_rpt + PCIERPT_WORD4] ;\
18218: ;\
1822 .poplocals ;\
1823 nop
1824
1825#define LOG_PCIERPT_CXPL_INTR_STATUS(PIU_rpt, PIU_LEAF_BASE_ADDR, LOGBIT,\
1826 scr1, scr2) \
1827 set LOGBIT, scr1 ;\
1828 stx scr1, [PIU_rpt + PCIERPT_PEU_CXPL_EVENT_ERROR_INT_STATUS];\
1829 set PCI_E_PEU_CXPL_INT_ENB_ADDR, scr2 ;\
1830 ldx [PIU_LEAF_BASE_ADDR + scr2], scr1 ;\
1831 stx scr1, [PIU_LEAF_BASE_ADDR + \
1832 PCIERPT_PEU_CXPL_EVENT_ERROR_INT_ENABLE];\
1833 set PCI_E_PEU_CXPL_LOG_ENB_ADDR, scr2 ;\
1834 ldx [PIU_LEAF_BASE_ADDR + scr2], scr1 ;\
1835 stx scr1, [PIU_LEAF_BASE_ADDR + \
1836 PCIERPT_PEU_CXPL_EVENT_ERROR_LOG_ENABLE];\
1837 set PCI_E_PEU_CXPL_STAT_SET_ADDR, scr2 ;\
1838 ldx [PIU_LEAF_BASE_ADDR + scr2], scr1 ;\
1839 stx scr1, [PIU_LEAF_BASE_ADDR + \
1840 PCIERPT_PEU_CXPL_EVENT_ERROR_STATUS_SET]
1841
1842
1843#define CLEAR_CXPL_INTR_STATUS(PIU_rpt, PIU_LEAF_BASE_ADDR, LOGBIT, \
1844 scr1, scr2) \
1845 set LOGBIT, scr2 ;\
1846 set PCI_E_PEU_CXPL_STAT_CL_ADDR, scr1 ;\
1847 stx scr2, [PIU_LEAF_BASE_ADDR + scr1]
1848
1849
1850/*
1851 * log MMU header and addr fields for the errors that need them
1852 */
1853#define MMU_FAULT_LOGGING_GROUP (MMU_TBW_DPE_P | MMU_TBW_ERR_P | \
1854 MMU_TBW_UDE_P | MMU_TBW_DME_P | \
1855 MMU_TTE_PRT_P | MMU_TTE_INV_P | \
1856 MMU_TRN_OOR_P | MMU_TRN_ERR_P | \
1857 MMU_BYP_OOR_P | MMU_BYP_ERR_P | \
1858 MMU_VA_OOR_P | MMU_VA_ADJ_UF_P | \
1859 MMU_IOTSBDESC_DPE_P | \
1860 MMU_IOTSBDESC_INV_P | \
1861 MMU_INV_PG_SZ_P | \
1862 MMU_SUN4V_KEY_ERR_P)
1863
1864#define LOG_MMU_FAULT_ADDR_AND_FAULT_STATUS(PIU_E_rpt, \
1865 PIU_LEAF_BASE_ADDRx, REG1, REG2) \
1866 set PCI_E_MMU_TRANS_FAULT_ADDR, REG1 ;\
1867 ldx [PIU_LEAF_BASE_ADDRx + REG1], REG2 ;\
1868 /* bits 63:2 hold the va, align value for ereport */ ;\
1869 srlx REG2, 2, REG2 ;\
1870 sllx REG2, 2, REG2 ;\
1871 stx REG2, [PIU_E_rpt + PCIERPT_WORD4] ;\
1872 sllx REG2, 32, REG2 ;\
1873 stx REG2, [PIU_E_rpt + PCIERPT_HDR2] ;\
1874 set PIU_DLC_MMU_CSR_A_FLTS_ADDR, REG1 ;\
1875 ldx [PIU_LEAF_BASE_ADDRx + REG1], REG2 ;\
1876 /* bits 22:16 hold tranaction type move to 62:56 */ ;\
1877 srlx REG2, 16, REG2 ;\
1878 sllx REG2, 56, REG2 ;\
1879 ldx [PIU_LEAF_BASE_ADDRx + REG1], REG1 ;\
1880 /* bits 15:0 hold BDF, move to 31:16, zero upper 32 bits */ ;\
1881 sllx REG1, (63 - 15), REG1 ;\
1882 srlx REG1, 32, REG1 ;\
1883 and REG1, REG2, REG2 ;\
1884 stx REG2, [PIU_E_rpt + PCIERPT_HDR1]
1885
1886#define LOG_MMU_ERR_GROUP_EPKT_P(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
1887 tmp2) \
1888 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
1889 set PCI_E_MMU_INT_STAT_ADDR, tmp2 ;\
1890 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1891 .pushlocals ;\
1892 btst MMU_BYP_ERR_P, tmp1 ;\
1893 bnz %xcc, 1f ;\
1894 btst MMU_BYP_OOR_P, tmp1 ;\
1895 bnz %xcc, 2f ;\
1896 set MMU_VA_OOR_P, tmp2 ;\
1897 btst tmp2, tmp1 ;\
1898 bnz %xcc, 3f ;\
1899 set MMU_VA_ADJ_UF_P, tmp2 ;\
1900 btst tmp2, tmp1 ;\
1901 bnz %xcc, 3f ;\
1902 btst MMU_TTE_INV_P, tmp1 ;\
1903 bnz %xcc, 4f ;\
1904 btst MMU_INV_PG_SZ_P, tmp1 ;\
1905 bnz %xcc, 4f ;\
1906 btst MMU_TTE_PRT_P, tmp1 ;\
1907 bnz %xcc, 5f ;\
1908 btst MMU_TTC_DPE_P, tmp1 ;\
1909 bnz %xcc, 6f ;\
1910 set MMU_IOTSBDESC_DPE_P, tmp2 ;\
1911 btst tmp2, tmp1 ;\
1912 bnz %xcc, 6f ;\
1913 btst MMU_TTC_CAE_P, tmp1 ;\
1914 bnz %xcc, 7f ;\
1915 nop ;\
1916 ba,a 8f ;\
1917 .empty ;\
19181: ;\
1919 set (MMU | BYPASS | PHASE_UNKNOWN | ILL | DIR_UNKNOWN | D | \
1920 H), tmp1 ;\
1921 ba 1f ;\
1922 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19232: ;\
1924 set (MMU | BYPASS | ADDR | ILL | RDRW | D | H), tmp1 ;\
1925 ba 1f ;\
1926 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19273: ;\
1928 set (MMU | TRANSLATION | ADDR | UNMAP | RDRW | D | H), tmp1 ;\
1929 ba 1f ;\
1930 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19314: ;\
1932 set (MMU | TRANSLATION | PDATA | INV | DIR_UNKNOWN | D | H),\
1933 tmp1 ;\
1934 ba 1f ;\
1935 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19365: ;\
1937 set (MMU | TRANSLATION | PDATA | PROT | WRITE | D | H), \
1938 tmp1 ;\
1939 ba 1f ;\
1940 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19416: ;\
1942 set (MMU | TRANSLATION | ADDR | PHASE_IRRELEVANT| \
1943 DIR_IRRELEVANT | D | H), tmp1 ;\
1944 ba 1f ;\
1945 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19467: ;\
1947 set (MMU | TRANSLATION | PDATA | COND_IRRELEVENT | \
1948 DIR_IRRELEVANT), tmp1 ;\
1949 ba 1f ;\
1950 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19518: ;\
1952 set MMU_TBW_DME_P, tmp2 ;\
1953 btst tmp2, tmp1 ;\
1954 bnz %xcc, 2f ;\
1955 set MMU_TBW_UDE_P, tmp2 ;\
1956 btst tmp2, tmp1 ;\
1957 bnz %xcc, 2f ;\
1958 set MMU_TBW_ERR_P, tmp2 ;\
1959 btst tmp2, tmp1 ;\
1960 bnz %xcc, 3f ;\
1961 set MMU_TBW_DPE_P, tmp2 ;\
1962 btst tmp2, tmp1 ;\
1963 bnz %xcc, 4f ;\
1964 btst MMU_TRN_ERR_P, tmp1 ;\
1965 bnz %xcc, 5f ;\
1966 btst MMU_TRN_OOR_P, tmp1 ;\
1967 bnz %xcc, 6f ;\
1968 set MMU_IOTSBDESC_INV_P, tmp2 ;\
1969 btst tmp2, tmp1 ;\
1970 bnz %xcc, 7f ;\
1971 set MMU_SUN4V_KEY_ERR_P, tmp2 ;\
1972 btst tmp2, tmp1 ;\
1973 bnz %xcc, 8f ;\
1974 clr tmp1 ;\
1975 ba,a 1f ;\
1976 nop ;\
19772: ;\
1978 set (MMU | TABLEWALK | PHASE_UNKNOWN | ILL | \
1979 DIR_IRRELEVANT | D | H), tmp1 ;\
1980 ba 1f ;\
1981 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19823: ;\
1983 set (MMU | TABLEWALK | PHASE_UNKNOWN | COND_UNKNOWN | \
1984 DIR_IRRELEVANT | D | H), tmp1 ;\
1985 ba 1f ;\
1986 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19874: ;\
1988 set (MMU | TABLEWALK | PDATA | INT | DIR_IRRELEVANT | D | H),\
1989 tmp1 ;\
1990 ba 1f ;\
1991 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19925: ;\
1993 set (MMU | TRANSLATION | PHASE_UNKNOWN | ILL | \
1994 DIR_IRRELEVANT | D | H), tmp1 ;\
1995 ba 1f ;\
1996 sllx tmp1, ALIGN_TO_64, tmp1 ;\
19976: ;\
1998 set (MMU | TRANSLATION | ADDR | ILL | RDRW | D | H), tmp1 ;\
1999 ba 1f ;\
2000 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20017: ;\
2002 set (MMU | TRANSLATION | PDATA | INV | RDRW | D | H), tmp1 ;\
2003 ba 1f ;\
2004 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20058: ;\
2006 set (MMU | TRANSLATION | ADDR | PROT | RDRW | D | H), tmp1 ;\
2007 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20081: ;\
2009 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
2010 set PCI_E_MMU_INT_STAT_ADDR, tmp2 ;\
2011 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
2012 set MMU_FAULT_LOGGING_GROUP, tmp2 ;\
2013 btst tmp2, tmp1 ;\
2014 bz %xcc, 1f ;\
2015 .empty ;\
2016 LOG_MMU_FAULT_ADDR_AND_FAULT_STATUS(PIU_rpt, PIU_LEAF_BASE_ADDR,\
2017 tmp1, tmp2); ;\
20181: ;\
2019 .poplocals
2020
2021#define LOG_MMU_ERR_GROUP_EPKT_S(PIU_rpt, PIU_LEAF_BASE_ADDR, tmp1, \
2022 tmp2) \
2023 EPKT_FILL_HEADER(PIU_rpt, tmp1); ;\
2024 set PCI_E_MMU_INT_STAT_ADDR, tmp2 ;\
2025 ldx [PIU_LEAF_BASE_ADDR + tmp2], tmp1 ;\
2026 srlx tmp1, SECONDARY_TO_PRIMARY_SHIFT_SZ, tmp1 ;\
2027 .pushlocals ;\
2028 btst MMU_BYP_ERR_P, tmp1 ;\
2029 bnz %xcc, 1f ;\
2030 btst MMU_BYP_OOR_P, tmp1 ;\
2031 bnz %xcc, 2f ;\
2032 set MMU_VA_OOR_P, tmp2 ;\
2033 btst tmp2, tmp1 ;\
2034 bnz %xcc, 3f ;\
2035 set MMU_VA_ADJ_UF_P, tmp2 ;\
2036 btst tmp2, tmp1 ;\
2037 bnz %xcc, 3f ;\
2038 btst MMU_TTE_INV_P, tmp1 ;\
2039 bnz %xcc, 4f ;\
2040 btst MMU_INV_PG_SZ_P, tmp1 ;\
2041 bnz %xcc, 4f ;\
2042 btst MMU_TTE_PRT_P, tmp1 ;\
2043 bnz %xcc, 5f ;\
2044 btst MMU_TTC_DPE_P, tmp1 ;\
2045 bnz %xcc, 6f ;\
2046 set MMU_IOTSBDESC_DPE_P, tmp2 ;\
2047 btst tmp2, tmp1 ;\
2048 bnz %xcc, 6f ;\
2049 btst MMU_TTC_CAE_P, tmp1 ;\
2050 bnz %xcc, 7f ;\
2051 nop ;\
2052 ba,a 8f ;\
2053 .empty ;\
20541: ;\
2055 set (MMU | BYPASS | PHASE_UNKNOWN | ILL | DIR_UNKNOWN | \
2056 STOP), tmp1 ;\
2057 ba 1f ;\
2058 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20592: ;\
2060 set (MMU | BYPASS | ADDR | ILL | RDRW | STOP), tmp1 ;\
2061 ba 1f ;\
2062 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20633: ;\
2064 set (MMU | TRANSLATION | ADDR | UNMAP | RDRW | STOP), tmp1 ;\
2065 ba 1f ;\
2066 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20674: ;\
2068 set (MMU | TRANSLATION | PDATA | INV | DIR_UNKNOWN | STOP), \
2069 tmp1 ;\
2070 ba 1f ;\
2071 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20725: ;\
2073 set (MMU | TRANSLATION | PDATA | PROT | WRITE | STOP), tmp1 ;\
2074 ba 1f ;\
2075 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20766: ;\
2077 set (MMU | TRANSLATION | ADDR | PHASE_IRRELEVANT| \
2078 DIR_IRRELEVANT | STOP), tmp1 ;\
2079 ba 1f ;\
2080 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20817: ;\
2082 set (MMU | TRANSLATION | PDATA | COND_IRRELEVENT | \
2083 DIR_IRRELEVANT | STOP), tmp1 ;\
2084 ba 1f ;\
2085 sllx tmp1, ALIGN_TO_64, tmp1 ;\
20868: ;\
2087 set MMU_TBW_DME_P, tmp2 ;\
2088 btst tmp2, tmp1 ;\
2089 bnz %xcc, 2f ;\
2090 set MMU_TBW_UDE_P, tmp2 ;\
2091 btst tmp2, tmp1 ;\
2092 bnz %xcc, 2f ;\
2093 set MMU_TBW_ERR_P, tmp2 ;\
2094 btst tmp2, tmp1 ;\
2095 bnz %xcc, 3f ;\
2096 set MMU_TBW_DPE_P, tmp2 ;\
2097 btst tmp2, tmp1 ;\
2098 bnz %xcc, 4f ;\
2099 btst MMU_TRN_ERR_P, tmp1 ;\
2100 bnz %xcc, 5f ;\
2101 btst MMU_TRN_OOR_P, tmp1 ;\
2102 bnz %xcc, 6f ;\
2103 set MMU_IOTSBDESC_INV_P, tmp2 ;\
2104 btst tmp2, tmp1 ;\
2105 bnz %xcc, 7f ;\
2106 set MMU_SUN4V_KEY_ERR_P, tmp2 ;\
2107 btst tmp2, tmp1 ;\
2108 bnz %xcc, 8f ;\
2109 clr tmp1 ;\
2110 ba,a 1f ;\
2111 .empty ;\
21122: ;\
2113 set (MMU | TABLEWALK | PHASE_UNKNOWN | ILL | \
2114 DIR_IRRELEVANT | STOP), tmp1 ;\
2115 ba 1f ;\
2116 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21173: ;\
2118 set (MMU | TABLEWALK | PHASE_UNKNOWN | COND_UNKNOWN | \
2119 DIR_IRRELEVANT | STOP), tmp1 ;\
2120 ba 1f ;\
2121 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21224: ;\
2123 set (MMU | TABLEWALK | PDATA | INT | DIR_IRRELEVANT | STOP),\
2124 tmp1 ;\
2125 ba 1f ;\
2126 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21275: ;\
2128 set (MMU | TRANSLATION | PHASE_UNKNOWN | ILL | \
2129 DIR_IRRELEVANT | STOP), tmp1 ;\
2130 ba 1f ;\
2131 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21326: ;\
2133 set (MMU | TRANSLATION | ADDR | ILL | RDRW | D | STOP), \
2134 tmp1 ;\
2135 ba 1f ;\
2136 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21377: ;\
2138 set (MMU | TRANSLATION | PDATA | INV | RDRW | STOP), tmp1 ;\
2139 ba 1f ;\
2140 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21418: ;\
2142 set (MMU | TRANSLATION | ADDR | PROT | RDRW | STOP), tmp1 ;\
2143 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21441: ;\
2145 stx tmp1, [PIU_rpt + PCIERPT_SUN4V_DESC] ;\
2146 .poplocals
2147
2148/* END CSTYLED */
2149
2150#ifdef __cplusplus
2151}
2152#endif
2153
2154#endif /* _NIAGARA_VPIU_ERRS_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.