[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / vpiu_errs_defs.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: vpiu_errs_defs.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _NIAGARA2_VPIU_ERRS_DEFS_H
#define	_NIAGARA2_VPIU_ERRS_DEFS_H

#pragma ident	"@(#)vpiu_errs_defs.h	1.1	07/05/03 SMI"

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASM
/*
 * Diagnostic error report structure.
 * Area containing both the sun4v error report and the diagnostic
 * error report.
 * Total size < 4096 (0x1000). So offsets into this struct can be used
 * as immediate values in assembler for reads and writes.
 * First 64 bytes is the sun4v error report sent to the affected guest.
 * The diagnostic error report starts at offset 0x40.
 */
struct epkt {
	/* sun4v guest error report starts at offset 0x0 */
	uint64_t	sysino;		/* I/O error interrupt number */
	uint64_t	sun4v_ehdl;	/* guest error handle */
	uint64_t	sun4v_stick;	/* %stick to guest */
	uint32_t	sun4v_desc;	/* error decriptor */
	uint32_t	sun4v_specfic;	/* error specific */
	uint64_t	word4;
	uint64_t	HDR1;		/* pci header 1 */
	uint64_t	HDR2;		/* pci header 2 */
	uint64_t	word7;		/* filler */
};

struct dmu_err {
	uint64_t	report_type;	/* cpu/io identifier */
	uint64_t	fpga_tod;	/* FPGA TOD */
	uint64_t	pciehdl; 	/* EHDL */
	uint64_t	pcistick; 	/* STICK */
	uint64_t	cpuver;		/* Proc version reg */
	uint32_t	agentid;
	uint32_t	mondo_num;
		/* mondo 62 regs */
	uint64_t	dmu_core_and_block_err_status;	/* 0x631808, dmu_cbes */
	uint64_t	imu_err_log_enable;		/* 0x631000, imu_ele */
	uint64_t	imu_interrupt_enable;		/* 0x631008, imu_ie */
	uint64_t	imu_enabled_err_status;		/* 0x631010, imu_is */
	uint64_t	imu_err_status_set;		/* 0x631020, imu_ess */
	uint64_t	imu_scs_err_log;
	uint64_t	imu_eqs_err_log;
	uint64_t	imu_rds_err_log;
	uint64_t	mmu_err_log_enable;		/* 0x641000, mmu_ele */
	uint64_t	mmu_intr_enable;		/* 0x641008, mmu_ie */
	uint64_t	mmu_intr_status;		/* 0x641010, mmu_is */
	uint64_t	mmu_err_status_set;		/* 0x641020, mmu_iss */
	uint64_t	mmu_translation_fault_address;	/* 0x641028, mmu_tfa */
	uint64_t	mmu_translation_fault_status;	/* 0x641030, mmu_tfs */
};

struct	peu_err {
	uint64_t	report_type;	/* cpu or io identifier */
	uint64_t	fpga_tod;	/* FPGA TOD */
	uint64_t	pciehdl; 	/* error handle */
	uint64_t	pcistick; 	/* value of %stick */
	uint64_t	cpuver;		/* Processor version reg */
	uint32_t	agentid;
	uint32_t	mondo_num;
	/* mondo 63 regs */
	uint64_t	peu_core_and_block_intr_enable;	/* 0x651800 peu_cbie */
	uint64_t	peu_core_and_block_intr_status;	/* 0x651808 peu_cbis */
	uint64_t	ilu_err_log_enable;		/* 0x651000 ilu_ele */
	uint64_t	ilu_intr_enable;		/* 0x651008 ilu_ie */
	uint64_t	ilu_intr_status;		/* 0x651010 ilu_is */
	uint64_t	ilu_err_status_set;		/* 0x651020 ilu_ess */
	uint64_t	peu_other_event_log_enable;	/* 0x681000 peu_oele */
	uint64_t	peu_other_event_intr_enable;	/* 0x681008 peu_oeie */
	uint64_t	peu_other_event_intr_status;	/* 0x681010 peu_oeis */
	uint64_t	peu_other_event_status_set;	/* 0x681020 peu_oess */
	uint64_t	peu_receive_other_event_header1_log;
							/* 0x681028 peu_roeh1 */
	uint64_t	peu_receive_other_event_header2_log;
							/* 0x681030 peu_roeh2 */
	uint64_t	peu_transmit_other_event_header1_log;
							/* 0x681038 peu_toeh1 */
	uint64_t	peu_transmit_other_event_header2_log;
							/* 0x681040 peu_toeh2 */
	uint64_t	peu_ue_log_enable;		/* 0x691000 peu_uele */
	uint64_t	peu_ue_interrupt_enable;	/* 0x691008 peu_ueie */
	uint64_t	peu_ue_status;			/* 0x691010 peu_ueis */
	uint64_t	peu_ue_status_set;		/* 0x691020 peu_uess */
	uint64_t	peu_receive_ue_header1_log;	/* 0x691028 peu_rueh1 */
	uint64_t	peu_receive_ue_header2_log;	/* 0x691030 peu_rueh2 */
	uint64_t	peu_transmit_ue_header1_log;	/* 0x691038 peu_tueh1 */
	uint64_t	peu_transmit_ue_header2_log;	/* 0x691040 peu_tueh2 */
	uint64_t	peu_ce_log_enable;		/* 0x6a1000 peu_cele */
	uint64_t	peu_ce_interrupt_enable;	/* 0x6a1008 peu_ceie */
	uint64_t	peu_ce_interrupt_status;	/* 0x6a1010 peu_ceis */
	uint64_t	peu_ce_status_set;		/* 0x6a1020 peu_cess */
	uint64_t	PEU_CXPL_event_error_log_enable; /* 0x6E2108 peu_eele */
	uint64_t	PEU_CXPL_event_error_int_enable; /* 0x6E2110 peu_eeie */
	uint64_t	PEU_CXPL_event_error_int_status; /* 0x6E2118 peu_eeis */
	uint64_t	PEU_CXPL_event_error_status_set; /* 0x6E2128 peu_eess */
};

struct pci_erpt {
	struct epkt	pciepkt;
	union {
		struct	dmu_err		dmu_err;
		struct	peu_err		peu_err;
	} _u;
	int		unsent_pkt;	/* mark pkt to be sent */
};

typedef struct epkt	sun4v_pcie_erpt_t;

#endif /* ASM */

#ifdef __cplusplus
}
#endif

#endif /* _NIAGARA2_VPIU_ERRS_DEFS_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: vpiu_errs_defs.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _NIAGARA2_VPIU_ERRS_DEFS_H
	50	#define _NIAGARA2_VPIU_ERRS_DEFS_H
	51
	52	#pragma ident "@(#)vpiu_errs_defs.h 1.1 07/05/03 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	#ifndef _ASM
	59	/*
	60	* Diagnostic error report structure.
	61	* Area containing both the sun4v error report and the diagnostic
	62	* error report.
	63	* Total size < 4096 (0x1000). So offsets into this struct can be used
	64	* as immediate values in assembler for reads and writes.
65	* First 64 bytes is the sun4v error report sent to the affected guest.
66	* The diagnostic error report starts at offset 0x40.
67	*/
68	struct epkt {
69	/* sun4v guest error report starts at offset 0x0 */
70	uint64_t sysino; /* I/O error interrupt number */
71	uint64_t sun4v_ehdl; /* guest error handle */
72	uint64_t sun4v_stick; /* %stick to guest */
73	uint32_t sun4v_desc; /* error decriptor */
74	uint32_t sun4v_specfic; /* error specific */
75	uint64_t word4;
76	uint64_t HDR1; /* pci header 1 */
77	uint64_t HDR2; /* pci header 2 */
78	uint64_t word7; /* filler */
79	};
80
81	struct dmu_err {
82	uint64_t report_type; /* cpu/io identifier */
83	uint64_t fpga_tod; /* FPGA TOD */
84	uint64_t pciehdl; /* EHDL */
85	uint64_t pcistick; /* STICK */
86	uint64_t cpuver; /* Proc version reg */
87	uint32_t agentid;
88	uint32_t mondo_num;
89	/* mondo 62 regs */
90	uint64_t dmu_core_and_block_err_status; /* 0x631808, dmu_cbes */
91	uint64_t imu_err_log_enable; /* 0x631000, imu_ele */
92	uint64_t imu_interrupt_enable; /* 0x631008, imu_ie */
93	uint64_t imu_enabled_err_status; /* 0x631010, imu_is */
94	uint64_t imu_err_status_set; /* 0x631020, imu_ess */
95	uint64_t imu_scs_err_log;
96	uint64_t imu_eqs_err_log;
97	uint64_t imu_rds_err_log;
98	uint64_t mmu_err_log_enable; /* 0x641000, mmu_ele */
99	uint64_t mmu_intr_enable; /* 0x641008, mmu_ie */
100	uint64_t mmu_intr_status; /* 0x641010, mmu_is */
101	uint64_t mmu_err_status_set; /* 0x641020, mmu_iss */
102	uint64_t mmu_translation_fault_address; /* 0x641028, mmu_tfa */
103	uint64_t mmu_translation_fault_status; /* 0x641030, mmu_tfs */
104	};
105
106	struct peu_err {
107	uint64_t report_type; /* cpu or io identifier */
108	uint64_t fpga_tod; /* FPGA TOD */
109	uint64_t pciehdl; /* error handle */
110	uint64_t pcistick; /* value of %stick */
111	uint64_t cpuver; /* Processor version reg */
112	uint32_t agentid;
113	uint32_t mondo_num;
114	/* mondo 63 regs */
115	uint64_t peu_core_and_block_intr_enable; /* 0x651800 peu_cbie */
116	uint64_t peu_core_and_block_intr_status; /* 0x651808 peu_cbis */
117	uint64_t ilu_err_log_enable; /* 0x651000 ilu_ele */
118	uint64_t ilu_intr_enable; /* 0x651008 ilu_ie */
119	uint64_t ilu_intr_status; /* 0x651010 ilu_is */
120	uint64_t ilu_err_status_set; /* 0x651020 ilu_ess */
121	uint64_t peu_other_event_log_enable; /* 0x681000 peu_oele */
122	uint64_t peu_other_event_intr_enable; /* 0x681008 peu_oeie */
123	uint64_t peu_other_event_intr_status; /* 0x681010 peu_oeis */
124	uint64_t peu_other_event_status_set; /* 0x681020 peu_oess */
125	uint64_t peu_receive_other_event_header1_log;
126	/* 0x681028 peu_roeh1 */
127	uint64_t peu_receive_other_event_header2_log;
128	/* 0x681030 peu_roeh2 */
129	uint64_t peu_transmit_other_event_header1_log;
130	/* 0x681038 peu_toeh1 */
131	uint64_t peu_transmit_other_event_header2_log;
132	/* 0x681040 peu_toeh2 */
133	uint64_t peu_ue_log_enable; /* 0x691000 peu_uele */
134	uint64_t peu_ue_interrupt_enable; /* 0x691008 peu_ueie */
135	uint64_t peu_ue_status; /* 0x691010 peu_ueis */
136	uint64_t peu_ue_status_set; /* 0x691020 peu_uess */
137	uint64_t peu_receive_ue_header1_log; /* 0x691028 peu_rueh1 */
138	uint64_t peu_receive_ue_header2_log; /* 0x691030 peu_rueh2 */
139	uint64_t peu_transmit_ue_header1_log; /* 0x691038 peu_tueh1 */
140	uint64_t peu_transmit_ue_header2_log; /* 0x691040 peu_tueh2 */
141	uint64_t peu_ce_log_enable; /* 0x6a1000 peu_cele */
142	uint64_t peu_ce_interrupt_enable; /* 0x6a1008 peu_ceie */
143	uint64_t peu_ce_interrupt_status; /* 0x6a1010 peu_ceis */
144	uint64_t peu_ce_status_set; /* 0x6a1020 peu_cess */
145	uint64_t PEU_CXPL_event_error_log_enable; /* 0x6E2108 peu_eele */
146	uint64_t PEU_CXPL_event_error_int_enable; /* 0x6E2110 peu_eeie */
147	uint64_t PEU_CXPL_event_error_int_status; /* 0x6E2118 peu_eeis */
148	uint64_t PEU_CXPL_event_error_status_set; /* 0x6E2128 peu_eess */
149	};
150
151	struct pci_erpt {
152	struct epkt pciepkt;
153	union {
154	struct dmu_err dmu_err;
155	struct peu_err peu_err;
156	} _u;
157	int unsent_pkt; /* mark pkt to be sent */
158	};
159
160	typedef struct epkt sun4v_pcie_erpt_t;
161
162	#endif /* ASM */
163
164	#ifdef __cplusplus
165	}
166	#endif
167
168	#endif /* _NIAGARA2_VPIU_ERRS_DEFS_H */