Commit | Line | Data |
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920dae64 AT |
1 | ! struct/union NAMETABLE_SIZE size 0x2e8 |
2 | u 0x0 0x8 HDNAME_ROOT | |
3 | u 0x8 0x8 HDNAME_FWD | |
4 | u 0x10 0x8 HDNAME_BACK | |
5 | u 0x18 0x8 HDNAME_ID | |
6 | u 0x20 0x8 HDNAME_CPUS | |
7 | u 0x28 0x8 HDNAME_CPU | |
8 | u 0x30 0x8 HDNAME_DEVICES | |
9 | u 0x38 0x8 HDNAME_DEVICE | |
10 | u 0x40 0x8 HDNAME_SERVICES | |
11 | u 0x48 0x8 HDNAME_SERVICE | |
12 | u 0x50 0x8 HDNAME_GUESTS | |
13 | u 0x58 0x8 HDNAME_GUEST | |
14 | u 0x60 0x8 HDNAME_MAU | |
15 | u 0x68 0x8 HDNAME_MAUS | |
16 | u 0x70 0x8 HDNAME_CWQ | |
17 | u 0x78 0x8 HDNAME_CWQS | |
18 | u 0x80 0x8 HDNAME_ROMSIZE | |
19 | u 0x88 0x8 HDNAME_ROMBASE | |
20 | u 0x90 0x8 HDNAME_MEMORY | |
21 | u 0x98 0x8 HDNAME_MBLOCK | |
22 | u 0xa0 0x8 HDNAME_UNBIND | |
23 | u 0xa8 0x8 HDNAME_MDPA | |
24 | u 0xb0 0x8 HDNAME_SIZE | |
25 | u 0xb8 0x8 HDNAME_UARTBASE | |
26 | u 0xc0 0x8 HDNAME_BASE | |
27 | u 0xc8 0x8 HDNAME_LINK | |
28 | u 0xd0 0x8 HDNAME_INOBITMAP | |
29 | u 0xd8 0x8 HDNAME_TOD | |
30 | u 0xe0 0x8 HDNAME_TODFREQUENCY | |
31 | u 0xe8 0x8 HDNAME_TODOFFSET | |
32 | u 0xf0 0x8 HDNAME_VID | |
33 | u 0xf8 0x8 HDNAME_XID | |
34 | u 0x100 0x8 HDNAME_PID | |
35 | u 0x108 0x8 HDNAME_SID | |
36 | u 0x110 0x8 HDNAME_GID | |
37 | u 0x118 0x8 HDNAME_STRANDID | |
38 | u 0x120 0x8 HDNAME_PARTTAG | |
39 | u 0x128 0x8 HDNAME_IGN | |
40 | u 0x130 0x8 HDNAME_INO | |
41 | u 0x138 0x8 HDNAME_MTU | |
42 | u 0x140 0x8 HDNAME_MEMOFFSET | |
43 | u 0x148 0x8 HDNAME_MEMSIZE | |
44 | u 0x150 0x8 HDNAME_MEMBASE | |
45 | u 0x158 0x8 HDNAME_REALBASE | |
46 | u 0x160 0x8 HDNAME_HYPERVISOR | |
47 | u 0x168 0x8 HDNAME_PERFCTRACCESS | |
48 | u 0x170 0x8 HDNAME_PERFCTRHTACCESS | |
49 | u 0x178 0x8 HDNAME_RNGCTLACCESSIBLE | |
50 | u 0x180 0x8 HDNAME_VPCIDEVICE | |
51 | u 0x188 0x8 HDNAME_PCIREGS | |
52 | u 0x190 0x8 HDNAME_CFGHANDLE | |
53 | u 0x198 0x8 HDNAME_CFGBASE | |
54 | u 0x1a0 0x8 HDNAME_DISKPA | |
55 | u 0x1a8 0x8 HDNAME_DIAGPRIV | |
56 | u 0x1b0 0x8 HDNAME_DEBUGPRINTFLAGS | |
57 | u 0x1b8 0x8 HDNAME_IOBASE | |
58 | u 0x1c0 0x8 HDNAME_HVUART | |
59 | u 0x1c8 0x8 HDNAME_FLAGS | |
60 | u 0x1d0 0x8 HDNAME_STICKFREQUENCY | |
61 | u 0x1d8 0x8 HDNAME_CEBLACKOUTSEC | |
62 | u 0x1e0 0x8 HDNAME_CEPOLLSEC | |
63 | u 0x1e8 0x8 HDNAME_MEMSCRUBMAX | |
64 | u 0x1f0 0x8 HDNAME_ERPT_PA | |
65 | u 0x1f8 0x8 HDNAME_ERPT_SIZE | |
66 | u 0x200 0x8 HDNAME_VDEVS | |
67 | u 0x208 0x8 HDNAME_RESET_REASON | |
68 | u 0x210 0x8 HDNAME_LDC_ENDPOINTS | |
69 | u 0x218 0x8 HDNAME_SP_LDC_ENDPOINTS | |
70 | u 0x220 0x8 HDNAME_LDC_ENDPOINT | |
71 | u 0x228 0x8 HDNAME_CHANNEL | |
72 | u 0x230 0x8 HDNAME_TARGET_TYPE | |
73 | u 0x238 0x8 HDNAME_TARGET_GUEST | |
74 | u 0x240 0x8 HDNAME_TARGET_CHANNEL | |
75 | u 0x248 0x8 HDNAME_TX_INO | |
76 | u 0x250 0x8 HDNAME_RX_INO | |
77 | u 0x258 0x8 HDNAME_SVC_ID | |
78 | u 0x260 0x8 HDNAME_SVC_ARG | |
79 | u 0x268 0x8 HDNAME_SVC_VINO | |
80 | u 0x270 0x8 HDNAME_PRIVATE_SVC | |
81 | u 0x278 0x8 HDNAME_LDC_MAPINRABASE | |
82 | u 0x280 0x8 HDNAME_LDC_MAPINSIZE | |
83 | u 0x288 0x8 HDNAME_IDX | |
84 | u 0x290 0x8 HDNAME_RESOURCE_ID | |
85 | u 0x298 0x8 HDNAME_CONSOLES | |
86 | u 0x2a0 0x8 HDNAME_CONSOLE | |
87 | u 0x2a8 0x8 HDNAME_VIRTUAL_DEVICES | |
88 | u 0x2b0 0x8 HDNAME_CHANNEL_DEVICES | |
89 | u 0x2b8 0x8 HDNAME_SYS_HWTW_MODE | |
90 | u 0x2c0 0x8 HDNAME_PCIE_BUS | |
91 | u 0x2c8 0x8 HDNAME_ALLOW_BYPASS | |
92 | u 0x2d0 0x8 HDNAME_L2SCRUB_INTERVAL | |
93 | u 0x2d8 0x8 HDNAME_L2SCRUB_ENTRIES | |
94 | u 0x2e0 0x8 HDNAME_CONTENT_VERSION | |
95 | ! struct/union CONFIG_SIZE size 0x570 | |
96 | u 0x0 0x8 CONFIG_MEMBASE | |
97 | u 0x8 0x8 CONFIG_MEMSIZE | |
98 | p 0x10 0x8 CONFIG_ACTIVE_HVMD | |
99 | p 0x18 0x8 CONFIG_PARSE_HVMD | |
100 | u 0x20 0x8 CONFIG_RELOC | |
101 | p 0x28 0x8 CONFIG_GUESTS | |
102 | p 0x30 0x8 CONFIG_MBLOCKS | |
103 | p 0x38 0x8 CONFIG_VCPUS | |
104 | p 0x40 0x8 CONFIG_STRANDS | |
105 | p 0x48 0x8 CONFIG_VSTATE | |
106 | p 0x50 0x8 CONFIG_PCIE_BUSSES | |
107 | p 0x58 0x8 CONFIG_HV_LDCS | |
108 | p 0x60 0x8 CONFIG_SP_LDCS | |
109 | u 0x68 0x8 CONFIG_SP_LDC_MAX_CID | |
110 | p 0x70 0x8 CONFIG_DUMMYTSB | |
111 | u 0x78 0x8 CONFIG_SINGLE_STRAND_LOCK | |
112 | u 0x80 0x8 CONFIG_STRAND_STARTSET | |
113 | u 0x88 0x8 CONFIG_STPRES | |
114 | u 0x90 0x8 CONFIG_STACTIVE | |
115 | u 0x98 0x8 CONFIG_STIDLE | |
116 | u 0xa0 0x8 CONFIG_STHALT | |
117 | u 0xa8 0x8 CONFIG_PRINT_SPINLOCK | |
118 | u 0xb0 0x8 CONFIG_HEARTBEAT_CPU | |
119 | u 0xb8 0x8 CONFIG_ERROR_SVCH | |
120 | p 0xc0 0x8 CONFIG_SVCS | |
121 | p 0xc8 0x8 CONFIG_VINTR | |
122 | u 0xd0 0x8 CONFIG_HVUART_ADDR | |
123 | u 0xd8 0x8 CONFIG_TOD | |
124 | u 0xe0 0x8 CONFIG_TODFREQUENCY | |
125 | u 0xe8 0x8 CONFIG_STICKFREQUENCY | |
126 | u 0xf0 0x8 CONFIG_SYS_HWTW_MODE | |
127 | u 0xf8 0x8 CONFIG_ERPT_PA | |
128 | u 0x100 0x8 CONFIG_ERPT_SIZE | |
129 | u 0x108 0x8 CONFIG_SRAM_ERPT_BUF_INUSE | |
130 | p 0x118 0x8 CONFIG_DEVS_DTNODE | |
131 | p 0x120 0x8 CONFIG_SVCS_DTNODE | |
132 | p 0x128 0x8 CONFIG_GUESTS_DTNODE | |
133 | p 0x130 0x8 CONFIG_CPUS_DTNODE | |
134 | p 0x138 0x8 CONFIG_HV_LDCS_DTNODE | |
135 | p 0x140 0x8 CONFIG_SP_LDCS_DTNODE | |
136 | u 0x148 0x8 CONFIG_ERRORLOCK | |
137 | ! struct CONFIG_HDNAMETABLE @ 0x150 has size 0x2e8 | |
138 | u 0x438 0x8 CONFIG_INTRTGT | |
139 | u 0x440 0x8 CONFIG_MEMSCRUB_MAX | |
140 | p 0x448 0x8 CONFIG_DEVINSTANCES | |
141 | u 0x450 0x8 CONFIG_CYCLIC_MAXD | |
142 | uc 0x458 0x1 CONFIG_HVCTL_STATE | |
143 | u 0x45a 0x2 CONFIG_HVCTL_HV_SEQ | |
144 | u 0x45c 0x2 CONFIG_HVCTL_ZEUS_SEQ | |
145 | u 0x468 0x8 CONFIG_HVCTL_RAND_NUM | |
146 | ! array CONFIG_HVCTL_IBUF @ 0x470 size 0x200 : element size 0x8 | |
147 | u 0x470 0x8 CONFIG_HVCTL_IBUF | |
148 | ! array CONFIG_HVCTL_OBUF @ 0x4b0 size 0x200 : element size 0x8 | |
149 | u 0x4b0 0x8 CONFIG_HVCTL_OBUF | |
150 | u 0x4f0 0x8 CONFIG_HVCTL_IP | |
151 | u 0x4f8 0x8 CONFIG_HVCTL_LDC | |
152 | u 0x500 0x8 CONFIG_HVCTL_LDC_LOCK | |
153 | u 0x508 0x8 CONFIG_CE_BLACKOUT | |
154 | u 0x510 0x8 CONFIG_CE_POLL_TIME | |
155 | u 0x518 0x8 CONFIG_ERRS_TO_SEND | |
156 | u 0x520 0x8 CONFIG_PHYSMEMSIZE | |
157 | u 0x528 0x8 CONFIG_DEL_RECONF_GID | |
158 | u 0x538 0x8 CONFIG_SCRUB_SYNC | |
159 | u 0x540 0x8 CONFIG_FPGA_STATUS_LOCK | |
160 | u 0x548 0x8 CONFIG_L2SCRUB_INTERVAL | |
161 | u 0x550 0x8 CONFIG_L2SCRUB_ENTRIES | |
162 | ! struct CONFIG_MCONFIG @ 0x558 has size 0x18 | |
163 | ! struct/union MAU_SIZE size 0xd0 | |
164 | u 0x0 0x8 MAU_PID | |
165 | u 0x8 0x8 MAU_STATE | |
166 | u 0x10 0x8 MAU_HANDLE | |
167 | u 0x18 0x8 MAU_INO | |
168 | u 0x20 0x8 MAU_STORE_IN_PROGR | |
169 | u 0x28 0x8 MAU_ENABLE_CWQ | |
170 | u 0x30 0x8 MAU_CPUSET | |
171 | ! array MAU_CPU_ACTIVE @ 0x38 size 0x40 : element size 0x1 | |
172 | uc 0x38 0x1 MAU_CPU_ACTIVE | |
173 | ! struct MAU_QUEUE @ 0x40 has size 0x50 | |
174 | ! struct MAU_IHDLR @ 0x90 has size 0x18 | |
175 | ! struct/union CWQ_SIZE size 0x1140 | |
176 | u 0x0 0x8 CWQ_PID | |
177 | u 0x8 0x8 CWQ_STATE | |
178 | u 0x10 0x8 CWQ_HANDLE | |
179 | u 0x18 0x8 CWQ_INO | |
180 | u 0x20 0x8 CWQ_CPUSET | |
181 | ! array CWQ_CPU_ACTIVE @ 0x28 size 0x40 : element size 0x1 | |
182 | uc 0x28 0x1 CWQ_CPU_ACTIVE | |
183 | ! struct CWQ_IHDLR @ 0x30 has size 0x18 | |
184 | ! struct CWQ_QUEUE @ 0x70 has size 0x10d0 | |
185 | ! struct/union RNG_SIZE size 0x40 | |
186 | u 0x0 0x4 RNG_LOCK | |
187 | ! struct RNG_CTL @ 0x8 has size 0x38 | |
188 | ! struct/union RWINDOW_SIZE size 0x80 | |
189 | ! array INS @ 0x0 size 0x200 : element size 0x8 | |
190 | u 0x0 0x8 INS | |
191 | ! array OUTS @ 0x40 size 0x200 : element size 0x8 | |
192 | u 0x40 0x8 OUTS | |
193 | ! struct/union VCPUTRAPSTATE_SIZE size 0x28 | |
194 | u 0x0 0x8 VCTS_TPC | |
195 | u 0x8 0x8 VCTS_TNPC | |
196 | u 0x10 0x8 VCTS_TSTATE | |
197 | u 0x18 0x8 VCTS_TT | |
198 | u 0x20 0x8 VCTS_HTSTATE | |
199 | ! struct/union VCPU_GLOBALS_SIZE size 0x38 | |
200 | ! array VCPU_GLOBALS_G @ 0x0 size 0x1c0 : element size 0x8 | |
201 | u 0x0 0x8 VCPU_GLOBALS_G | |
202 | ! struct/union VCPUSTATE_SIZE size 0x670 | |
203 | u 0x0 0x8 VS_TL | |
204 | ! array VS_TRAPSTACK @ 0x8 size 0x780 : element size 0x28 | |
205 | ! struct VS_TRAPSTACK @ 0x8 has size 0xf0 | |
206 | u 0xf8 0x8 VS_GL | |
207 | ! array VS_GLOBALS @ 0x100 size 0x540 : element size 0x38 | |
208 | ! struct VS_GLOBALS @ 0x100 has size 0xa8 | |
209 | u 0x1a8 0x8 VS_TBA | |
210 | u 0x1b0 0x8 VS_Y | |
211 | u 0x1b8 0x8 VS_ASI | |
212 | u 0x1c0 0x8 VS_SOFTINT | |
213 | u 0x1c8 0x8 VS_PIL | |
214 | u 0x1d0 0x8 VS_GSR | |
215 | u 0x1d8 0x8 VS_TICK | |
216 | u 0x1e0 0x8 VS_STICK | |
217 | u 0x1e8 0x8 VS_STICKCOMPARE | |
218 | ! array VS_SCRATCHPAD @ 0x1f0 size 0x200 : element size 0x8 | |
219 | u 0x1f0 0x8 VS_SCRATCHPAD | |
220 | u 0x230 0x8 VS_CWP | |
221 | u 0x238 0x8 VS_WSTATE | |
222 | u 0x240 0x8 VS_CANSAVE | |
223 | u 0x248 0x8 VS_CANRESTORE | |
224 | u 0x250 0x8 VS_OTHERWIN | |
225 | u 0x258 0x8 VS_CLEANWIN | |
226 | ! array VS_WINS @ 0x260 size 0x2000 : element size 0x80 | |
227 | ! struct VS_WINS @ 0x260 has size 0x400 | |
228 | u 0x660 0x2 VS_CPU_MONDO_HEAD | |
229 | u 0x662 0x2 VS_CPU_MONDO_TAIL | |
230 | u 0x664 0x2 VS_DEV_MONDO_HEAD | |
231 | u 0x666 0x2 VS_DEV_MONDO_TAIL | |
232 | u 0x668 0x2 VS_ERROR_RESUMABLE_HEAD | |
233 | u 0x66a 0x2 VS_ERROR_RESUMABLE_TAIL | |
234 | u 0x66c 0x2 VS_ERROR_NONRESUMABLE_HEAD | |
235 | u 0x66e 0x2 VS_ERROR_NONRESUMABLE_TAIL | |
236 | ! struct/union VCPU_SIZE size 0x9f8 | |
237 | p 0x0 0x8 CPU_GUEST | |
238 | p 0x8 0x8 CPU_ROOT | |
239 | p 0x10 0x8 CPU_STRAND | |
240 | u 0x18 0x4 CPU_RES_ID | |
241 | uc 0x1c 0x1 CPU_STRAND_SLOT | |
242 | uc 0x1d 0x1 CPU_VID | |
243 | uc 0x1e 0x1 CPU_PARTTAG | |
244 | ! array CPU_SCR @ 0x20 size 0x200 : element size 0x8 | |
245 | u 0x20 0x8 CPU_SCR | |
246 | u 0x60 0x8 CPU_STATUS | |
247 | u 0x80 0x8 CPU_CMD_LASTPOKE | |
248 | u 0x88 0x8 CPU_COMMAND | |
249 | u 0x90 0x8 CPU_CMD_ARG0 | |
250 | u 0x98 0x8 CPU_CMD_ARG1 | |
251 | u 0xa0 0x8 CPU_CMD_ARG2 | |
252 | u 0xa8 0x8 CPU_CMD_ARG3 | |
253 | u 0xb0 0x8 CPU_CMD_ARG4 | |
254 | u 0xb8 0x8 CPU_CMD_ARG5 | |
255 | u 0xc0 0x8 CPU_CMD_ARG6 | |
256 | u 0xc8 0x8 CPU_CMD_ARG7 | |
257 | u 0xd0 0x8 CPU_VINTR | |
258 | u 0xd8 0x8 CPU_START_PC | |
259 | u 0xe0 0x8 CPU_START_ARG | |
260 | u 0xe8 0x8 CPU_RTBA | |
261 | u 0xf0 0x8 CPU_MMU_AREA | |
262 | u 0xf8 0x8 CPU_MMU_AREA_RA | |
263 | u 0x100 0x8 CPU_CPUQ_BASE | |
264 | u 0x108 0x8 CPU_CPUQ_SIZE | |
265 | u 0x110 0x8 CPU_CPUQ_MASK | |
266 | u 0x118 0x8 CPU_CPUQ_BASE_RA | |
267 | u 0x120 0x8 CPU_DEVQ_BASE | |
268 | u 0x128 0x8 CPU_DEVQ_SIZE | |
269 | u 0x130 0x8 CPU_DEVQ_MASK | |
270 | u 0x138 0x8 CPU_DEVQ_BASE_RA | |
271 | u 0x140 0x8 CPU_DEVQ_LOCK | |
272 | u 0x148 0x8 CPU_DEVQ_SHDW_TAIL | |
273 | u 0x150 0x8 CPU_ERRQNR_BASE | |
274 | u 0x158 0x8 CPU_ERRQNR_SIZE | |
275 | u 0x160 0x8 CPU_ERRQNR_MASK | |
276 | u 0x168 0x8 CPU_ERRQNR_BASE_RA | |
277 | u 0x170 0x8 CPU_ERRQR_BASE | |
278 | u 0x178 0x8 CPU_ERRQR_SIZE | |
279 | u 0x180 0x8 CPU_ERRQR_MASK | |
280 | u 0x188 0x8 CPU_ERRQR_BASE_RA | |
281 | u 0x190 0x8 CPU_TTRACE_OFFSET | |
282 | u 0x198 0x8 CPU_TTRACEBUF_SIZE | |
283 | u 0x1a0 0x8 CPU_TTRACEBUF_RA | |
284 | u 0x1a8 0x8 CPU_TTRACEBUF_PA | |
285 | u 0x1b0 0x8 CPU_NTSBS_CTX0 | |
286 | u 0x1b8 0x8 CPU_NTSBS_CTXN | |
287 | ! array CPU_TSBDS_CTX0 @ 0x1c0 size 0x400 : element size 0x1 | |
288 | uc 0x1c0 0x1 CPU_TSBDS_CTX0 | |
289 | ! array CPU_TSBDS_CTXN @ 0x240 size 0x400 : element size 0x1 | |
290 | uc 0x240 0x1 CPU_TSBDS_CTXN | |
291 | u 0x2c0 0x8 CPU_MMUSTAT_AREA | |
292 | u 0x2c8 0x8 CPU_MMUSTAT_AREA_RA | |
293 | p 0x2d0 0x8 CPU_MAU | |
294 | p 0x2d8 0x8 CPU_CWQ | |
295 | p 0x2e0 0x8 CPU_RNG | |
296 | ! array CPU_SVCREGS @ 0x2e8 size 0x180 : element size 0x8 | |
297 | u 0x2e8 0x8 CPU_SVCREGS | |
298 | u 0x318 0x4 CPU_LDC_INTR_PEND | |
299 | u 0x320 0x8 CPU_LDC_ENDPOINT | |
300 | ! struct CPU_STATE_SAVE_AREA @ 0x350 has size 0x670 | |
301 | uc 0x9c0 0x1 CPU_LAUNCH_WITH_RETRY | |
302 | ! struct CPU_UTIL @ 0x9d0 has size 0x28 | |
303 | #define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR)) | |
304 | #define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR)) | |
305 | #define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR)) | |
306 | #define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR)) | |
307 | ! struct/union VCPU_UTIL_SIZE size 0x28 | |
308 | u 0x0 0x8 VCUTIL_STICK_LAST | |
309 | u 0x8 0x8 VCUTIL_YIELD_COUNT | |
310 | u 0x10 0x8 VCUTIL_YIELD_START | |
311 | #define CPU_UTIL_STICK_LAST (CPU_UTIL + VCUTIL_STICK_LAST) | |
312 | #define CPU_UTIL_YIELD_COUNT (CPU_UTIL + VCUTIL_YIELD_COUNT) | |
313 | #define CPU_UTIL_YIELD_START (CPU_UTIL + VCUTIL_YIELD_START) | |
314 | ! struct/union SCHED_SLOT_SIZE size 0x10 | |
315 | u 0x0 0x8 SCHED_SLOT_ACTION | |
316 | u 0x8 0x8 SCHED_SLOT_ARG | |
317 | ! struct/union HVCTL_HEADER_SIZE size 0x8 | |
318 | u 0x0 0x2 HVCTL_HEADER_OP | |
319 | ! struct/union HVCTL_MSG_SIZE size 0x40 | |
320 | ! struct HVCTL_MSG_HDR @ 0x0 has size 0x8 | |
321 | ! union HVCTL_MSG_MSG @ 0x8 has size 0x38 | |
322 | ! struct/union HVM_SCHED_SIZE size 0x8 | |
323 | u 0x0 0x8 HVM_SCHED_VCPUP | |
324 | ! struct/union HVM_SCRUB_SIZE size 0x10 | |
325 | u 0x0 0x8 HVM_SCRUB_START_PA | |
326 | u 0x8 0x8 HVM_SCRUB_START_LEN | |
327 | ! struct/union HVM_GUESTCMD_SIZE size 0x10 | |
328 | u 0x0 0x8 HVM_GUESTCMD_VCPUP | |
329 | u 0x8 0x8 HVM_GUESTCMD_ARG | |
330 | ! struct/union HVM_STOPGUEST_SIZE size 0x8 | |
331 | u 0x0 0x8 HVM_STOPGUEST_GUESTP | |
332 | ! struct/union HVM_SIZE size 0x40 | |
333 | u 0x0 0x8 HVM_CMD | |
334 | u 0x8 0x8 HVM_FROM_STRANDP | |
335 | ! union HVM_ARGS @ 0x10 has size 0x30 | |
336 | ! struct/union XCALL_MBOX_SIZE size 0x48 | |
337 | u 0x0 0x8 XCMB_COMMAND | |
338 | ! array XCMB_MONDOBUF @ 0x8 size 0x200 : element size 0x8 | |
339 | u 0x8 0x8 XCMB_MONDOBUF | |
340 | ! struct/union MINI_STACK_SIZE size 0x188 | |
341 | u 0x0 0x8 MINI_STACK_PTR | |
342 | ! array MINI_STACK_VAL @ 0x8 size 0xc00 : element size 0x8 | |
343 | u 0x8 0x8 MINI_STACK_VAL | |
344 | ! struct/union PCIE_DEVICE_SIZE size 0x20 | |
345 | p 0x8 0x8 PCIE_DEVICE_GUESTP | |
346 | ! struct/union STRAND_SIZE size 0x10ad0 | |
347 | uc 0x0 0x1 STRAND_ID | |
348 | p 0x8 0x8 STRAND_CONFIGP | |
349 | u 0x10 0x2 STRAND_CURRENT_SLOT | |
350 | ! array STRAND_SLOT @ 0x18 size 0x100 : element size 0x10 | |
351 | ! struct STRAND_SLOT @ 0x18 has size 0x20 | |
352 | ! struct STRAND_XCALL_MBOX @ 0x38 has size 0x48 | |
353 | ! array STRAND_HV_TXMONDO @ 0x80 size 0x200 : element size 0x8 | |
354 | u 0x80 0x8 STRAND_HV_TXMONDO | |
355 | ! array STRAND_HV_RXMONDO @ 0xc0 size 0x200 : element size 0x8 | |
356 | u 0xc0 0x8 STRAND_HV_RXMONDO | |
357 | u 0x100 0x8 STRAND_SCRUB_BASEPA | |
358 | u 0x108 0x8 STRAND_SCRUB_SIZE | |
359 | ! struct STRAND_MINI_STACK @ 0x110 has size 0x188 | |
360 | ! array STRAND_SCR @ 0x298 size 0x200 : element size 0x8 | |
361 | u 0x298 0x8 STRAND_SCR | |
362 | ! struct STRAND_CYCLIC @ 0x2d8 has size 0x248 | |
363 | u 0x520 0x8 STRAND_UE_TMP1 | |
364 | u 0x528 0x8 STRAND_UE_TMP2 | |
365 | u 0x530 0x8 STRAND_UE_TMP3 | |
366 | ! array STRAND_UE_GLOBALS @ 0x538 size 0xc00 : element size 0x40 | |
367 | ! struct STRAND_UE_GLOBALS @ 0x538 has size 0x180 | |
368 | u 0x6b8 0x8 STRAND_ERR_SEQ_NO | |
369 | u 0x6c0 0x4 STRAND_ERR_FLAG | |
370 | ! array STRAND_DIAG_BUF @ 0x6c8 size 0x180 : element size 0x8 | |
371 | p 0x6c8 0x30 STRAND_DIAG_BUF | |
372 | ! array STRAND_SUN4V_RPRT_BUF @ 0x6f8 size 0x180 : element size 0x8 | |
373 | p 0x6f8 0x30 STRAND_SUN4V_RPRT_BUF | |
374 | ! array STRAND_ERR_TABLE_ENTRY @ 0x728 size 0x180 : element size 0x8 | |
375 | p 0x728 0x30 STRAND_ERR_TABLE_ENTRY | |
376 | ! array STRAND_ERR_ISFSR @ 0x758 size 0x180 : element size 0x8 | |
377 | u 0x758 0x8 STRAND_ERR_ISFSR | |
378 | ! array STRAND_ERR_DSFSR @ 0x788 size 0x180 : element size 0x8 | |
379 | u 0x788 0x8 STRAND_ERR_DSFSR | |
380 | ! array STRAND_ERR_DSFAR @ 0x7b8 size 0x180 : element size 0x8 | |
381 | u 0x7b8 0x8 STRAND_ERR_DSFAR | |
382 | ! array STRAND_ERR_DESR @ 0x7e8 size 0x180 : element size 0x8 | |
383 | u 0x7e8 0x8 STRAND_ERR_DESR | |
384 | ! array STRAND_ERR_DFESR @ 0x818 size 0x180 : element size 0x8 | |
385 | u 0x818 0x8 STRAND_ERR_DFESR | |
386 | ! array STRAND_ERR_RETURN_ADDR @ 0x848 size 0x180 : element size 0x8 | |
387 | u 0x848 0x8 STRAND_ERR_RETURN_ADDR | |
388 | u 0x878 0x8 STRAND_IO_PROT | |
389 | u 0x880 0x8 STRAND_IO_ERROR | |
390 | u 0x888 0x8 STRAND_NRPENDING | |
391 | u 0x890 0x8 STRAND_REROUTED_CPU | |
392 | u 0x898 0x8 STRAND_REROUTED_EHDL | |
393 | u 0x8a0 0x8 STRAND_REROUTED_ADDR | |
394 | u 0x8a8 0x8 STRAND_REROUTED_STICK | |
395 | u 0x8b0 0x8 STRAND_REROUTED_ATTR | |
396 | u 0x8b8 0x8 STRAND_ABORT_PC | |
397 | u 0x8c0 0x8 STRAND_ERR_GLOBALS_SAVED | |
398 | u 0x8d0 0x8 STRAND_FAIL_TL | |
399 | u 0x8d8 0x8 STRAND_FAIL_GL | |
400 | ! array STRAND_FAIL_TRAPSTATE @ 0x8e0 size 0x780 : element size 0x28 | |
401 | ! struct STRAND_FAIL_TRAPSTATE @ 0x8e0 has size 0xf0 | |
402 | ! array STRAND_FAIL_TRAPGLOBALS @ 0x9d0 size 0x600 : element size 0x40 | |
403 | ! struct STRAND_FAIL_TRAPGLOBALS @ 0x9d0 has size 0xc0 | |
404 | ! array STRAND_MRA @ 0xa90 size 0x200 : element size 0x8 | |
405 | u 0xa90 0x8 STRAND_MRA | |
406 | ! array STRAND_STACK @ 0xad0 size 0x80000 : element size 0x8 | |
407 | u 0xad0 0x8 STRAND_STACK | |
408 | #define STRAND_SCR0 (STRAND_SCR + (0 * STRAND_SCR_INCR)) | |
409 | #define STRAND_SCR1 (STRAND_SCR + (1 * STRAND_SCR_INCR)) | |
410 | #define STRAND_SCR2 (STRAND_SCR + (2 * STRAND_SCR_INCR)) | |
411 | #define STRAND_SCR3 (STRAND_SCR + (3 * STRAND_SCR_INCR)) | |
412 | #define STRAND_FP_TMP1 STRAND_UE_TMP1 | |
413 | #define STRAND_FP_TMP2 STRAND_UE_TMP2 | |
414 | #define STRAND_FP_TMP3 STRAND_UE_TMP3 | |
415 | #define STRAND_ERR_ESR_INCR STRAND_ERR_ISFSR_INCR | |
416 | #define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR)) | |
417 | #define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR)) | |
418 | #define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR)) | |
419 | #define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR)) | |
420 | #define ENDOFSTACK (STACK_VAL_INCR * (STACKDEPTH + 1)) | |
421 | #define TOP (CPU_STACK + STACK_TOP) | |
422 | ! struct/union MAPPING_SIZE size 0x20 | |
423 | ! union MAPPING_ENTRY_ALIGNED @ 0x0 has size 0x10 | |
424 | ! array MAPPING_ICPUSET @ 0x10 size 0x40 : element size 0x8 | |
425 | u 0x10 0x8 MAPPING_ICPUSET | |
426 | ! array MAPPING_DCPUSET @ 0x18 size 0x40 : element size 0x8 | |
427 | u 0x18 0x8 MAPPING_DCPUSET | |
428 | ! struct MAP_ENTRY_ALIGNED_DATA @ 0x0 has size 0x10 | |
429 | u 0x0 0x8 MAP_DATA_VA | |
430 | u 0x8 0x8 MAP_DATA_TTE | |
431 | #define MAPPING_VA (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_VA) | |
432 | #define MAPPING_TTE (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_TTE) | |
433 | ! struct/union STACK_SIZE size 0x68 | |
434 | u 0x0 0x8 STACK_TOP | |
435 | ! array STACK_VAL @ 0x8 size 0x300 : element size 0x8 | |
436 | u 0x8 0x8 STACK_VAL | |
437 | #define BANK_SHIFT 6 | |
438 | #define CPU_EVBSC_L2_AFSR(n) CPU_VBSC_ERPT + EVBSC_L2_AFSR + (n * EVBSC_L2_AFSR_INCR) | |
439 | #define CPU_EVBSC_L2_AFAR(n) CPU_VBSC_ERPT + EVBSC_L2_AFAR + (n * EVBSC_L2_AFAR_INCR) | |
440 | #define CPU_EVBSC_DRAM_AFSR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFSR + (n * EVBSC_DRAM_AFSR_INCR) | |
441 | #define CPU_EVBSC_DRAM_AFAR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFAR + (n * EVBSC_DRAM_AFAR_INCR) | |
442 | #define CPU_EVBSC_DRAM_CNTR(n) CPU_VBSC_ERPT + EVBSC_DRAM_CNTR + (n * EVBSC_DRAM_CNTR_INCR) | |
443 | #define CPU_EVBSC_DRAM_LOC(n) CPU_VBSC_ERPT + EVBSC_DRAM_LOC + (n * EVBSC_DRAM_LOC_INCR) | |
444 | #define CPU_EVBSC_DCACHE_DATA(n) DCACHE_DATA + (n * DCACHE_DATA_INCR) | |
445 | #define CPU_EVBSC_ICACHE_DIAG_DATA(n) DIAG_BUF_ICACHE + ICACHE_DIAG_DATA + (n * ICACHE_DIAG_DATA_INCR) | |
446 | ! struct/union EPKTSIZE size 0x40 | |
447 | u 0x0 0x8 PCIERPT_SYSINO | |
448 | u 0x8 0x8 PCIERPT_SUN4V_EHDL | |
449 | u 0x10 0x8 PCIERPT_SUN4V_STICK | |
450 | u 0x18 0x4 PCIERPT_SUN4V_DESC | |
451 | u 0x1c 0x4 PCIERPT_SUN4V_SPECFIC | |
452 | u 0x20 0x8 PCIERPT_WORD4 | |
453 | u 0x28 0x8 PCIERPT_HDR1 | |
454 | u 0x30 0x8 PCIERPT_HDR2 | |
455 | ! struct/union DMU_ERR_SIZE size 0xa0 | |
456 | u 0x0 0x8 DMU_ERR_REPORT_TYPE_62 | |
457 | u 0x8 0x8 DMU_ERR_FPGA_TOD | |
458 | u 0x10 0x8 DMU_ERR_EHDL | |
459 | u 0x18 0x8 DMU_ERR_STICK | |
460 | u 0x20 0x8 DMU_ERR_CPUVER | |
461 | u 0x28 0x4 DMU_ERR_AGENTID | |
462 | u 0x2c 0x4 DMU_ERR_MONDO_NUM | |
463 | u 0x30 0x8 DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS | |
464 | u 0x38 0x8 DMU_ERR_IMU_ERR_LOG_ENABLE | |
465 | u 0x40 0x8 DMU_ERR_IMU_INTERRUPT_ENABLE | |
466 | u 0x48 0x8 DMU_ERR_IMU_ENABLED_ERR_STATUS | |
467 | u 0x50 0x8 DMU_ERR_IMU_ERR_STATUS_SET | |
468 | u 0x58 0x8 DMU_ERR_IMU_SCS_ERR_LOG | |
469 | u 0x60 0x8 DMU_ERR_IMU_EQS_ERR_LOG | |
470 | u 0x68 0x8 DMU_ERR_IMU_RDS_ERR_LOG | |
471 | u 0x70 0x8 DMU_ERR_MMU_ERR_LOG_ENABLE | |
472 | u 0x78 0x8 DMU_ERR_MMU_INTR_ENABLE | |
473 | u 0x80 0x8 DMU_ERR_MMU_INTR_STATUS | |
474 | u 0x88 0x8 DMU_ERR_MMU_ERR_STATUS_SET | |
475 | u 0x90 0x8 DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS | |
476 | u 0x98 0x8 DMU_ERR_MMU_TRANSLATION_FAULT_STATUS | |
477 | ! struct/union PEU_ERR_SIZE size 0x120 | |
478 | u 0x0 0x8 PCIE_ERR_REPORT_TYPE_63 | |
479 | u 0x30 0x8 PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE | |
480 | u 0x38 0x8 PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS | |
481 | u 0x40 0x8 PEU_ERR_ILU_ERR_LOG_ENABLE | |
482 | u 0x48 0x8 PEU_ERR_ILU_INTR_ENABLE | |
483 | u 0x50 0x8 PEU_ERR_ILU_INTR_STATUS | |
484 | u 0x58 0x8 PEU_ERR_ILU_ERR_STATUS_SET | |
485 | u 0x60 0x8 PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE | |
486 | u 0x68 0x8 PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE | |
487 | u 0x70 0x8 PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS | |
488 | u 0x78 0x8 PEU_ERR_PEU_OTHER_EVENT_STATUS_SET | |
489 | u 0x80 0x8 PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG | |
490 | u 0x88 0x8 PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG | |
491 | u 0x90 0x8 PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG | |
492 | u 0x98 0x8 PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG | |
493 | u 0xa0 0x8 PEU_ERR_PEU_UE_LOG_ENABLE | |
494 | u 0xa8 0x8 PEU_ERR_PEU_UE_INTERRUPT_ENABLE | |
495 | u 0xb0 0x8 PEU_ERR_PEU_UE_STATUS | |
496 | u 0xb8 0x8 PEU_ERR_PEU_UE_STATUS_SET | |
497 | u 0xc0 0x8 PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG | |
498 | u 0xc8 0x8 PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG | |
499 | u 0xd0 0x8 PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG | |
500 | u 0xd8 0x8 PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG | |
501 | u 0xe0 0x8 PEU_ERR_PEU_CE_LOG_ENABLE | |
502 | u 0xe8 0x8 PEU_ERR_PEU_CE_INTERRUPT_ENABLE | |
503 | u 0xf0 0x8 PEU_ERR_PEU_CE_INTERRUPT_STATUS | |
504 | u 0xf8 0x8 PEU_ERR_PEU_CE_STATUS_SET | |
505 | u 0x100 0x8 PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE | |
506 | u 0x108 0x8 PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE | |
507 | u 0x110 0x8 PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS | |
508 | u 0x118 0x8 PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET | |
509 | ! struct/union PCIERPT_SIZE size 0x168 | |
510 | ! struct PCI_ERPT_PCIEPKT @ 0x0 has size 0x40 | |
511 | ! union PCI_ERPT_U @ 0x40 has size 0x120 | |
512 | s 0x160 0x4 PCI_UNSENT_PKT | |
513 | #define PCIERPT_REPORT_TYPE_62 (PCI_ERPT_U + DMU_ERR_REPORT_TYPE_62) | |
514 | #define PCIERPT_FPGA_TOD (PCI_ERPT_U + DMU_ERR_FPGA_TOD) | |
515 | #define PCIERPT_EHDL (PCI_ERPT_U + DMU_ERR_EHDL) | |
516 | #define PCIERPT_STICK (PCI_ERPT_U + DMU_ERR_STICK) | |
517 | #define PCIERPT_CPUVER (PCI_ERPT_U + DMU_ERR_CPUVER ) | |
518 | #define PCIERPT_AGENTID (PCI_ERPT_U + DMU_ERR_AGENTID) | |
519 | #define PCIERPT_MONDO_NUM (PCI_ERPT_U + DMU_ERR_MONDO_NUM) | |
520 | #define PCIERPT_DMU_CORE_AND_BLOCK_ERR_STATUS (PCI_ERPT_U + DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS) | |
521 | #define PCIERPT_IMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_ERR_LOG_ENABLE) | |
522 | #define PCIERPT_IMU_INTERRUPT_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_INTERRUPT_ENABLE) | |
523 | #define PCIERPT_IMU_ENABLED_ERR_STATUS (PCI_ERPT_U + DMU_ERR_IMU_ENABLED_ERR_STATUS) | |
524 | #define PCIERPT_IMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_IMU_ERR_STATUS_SET) | |
525 | #define PCIERPT_IMU_SCS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_SCS_ERR_LOG) | |
526 | #define PCIERPT_IMU_EQS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_EQS_ERR_LOG) | |
527 | #define PCIERPT_IMU_RDS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_RDS_ERR_LOG) | |
528 | #define PCIERPT_MMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_ERR_LOG_ENABLE) | |
529 | #define PCIERPT_MMU_INTR_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_INTR_ENABLE) | |
530 | #define PCIERPT_MMU_INTR_STATUS (PCI_ERPT_U + DMU_ERR_MMU_INTR_STATUS) | |
531 | #define PCIERPT_MMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_MMU_ERR_STATUS_SET) | |
532 | #define PCIERPT_MMU_TRANSLATION_FAULT_ADDRESS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS) | |
533 | #define PCIERPT_MMU_TRANSLATION_FAULT_STATUS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_STATUS) | |
534 | #define PCIERPT_REPORT_TYPE_63 (PCI_ERPT_U + PCIE_ERR_REPORT_TYPE_63) | |
535 | #define PCIERPT_PEU_CORE_AND_BLOCK_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE) | |
536 | #define PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS) | |
537 | #define PCIERPT_ILU_ERR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_ERR_LOG_ENABLE) | |
538 | #define PCIERPT_ILU_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_INTR_ENABLE) | |
539 | #define PCIERPT_ILU_INTR_STATUS (PCI_ERPT_U + PEU_ERR_ILU_INTR_STATUS) | |
540 | #define PCIERPT_ILU_ERR_STATUS_SET (PCI_ERPT_U + PEU_ERR_ILU_ERR_STATUS_SET) | |
541 | #define PCIERPT_PEU_OTHER_EVENT_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE) | |
542 | #define PCIERPT_PEU_OTHER_EVENT_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE) | |
543 | #define PCIERPT_PEU_OTHER_EVENT_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS) | |
544 | #define PCIERPT_PEU_OTHER_EVENT_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_STATUS_SET) | |
545 | #define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG) | |
546 | #define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG) | |
547 | #define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG) | |
548 | #define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG) | |
549 | #define PCIERPT_PEU_UE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_LOG_ENABLE) | |
550 | #define PCIERPT_PEU_UE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_INTERRUPT_ENABLE) | |
551 | #define PCIERPT_PEU_UE_STATUS (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS) | |
552 | #define PCIERPT_PEU_UE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS_SET) | |
553 | #define PCIERPT_PEU_RECEIVE_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG) | |
554 | #define PCIERPT_PEU_RECEIVE_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG) | |
555 | #define PCIERPT_PEU_TRANSMIT_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG) | |
556 | #define PCIERPT_PEU_TRANSMIT_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG) | |
557 | #define PCIERPT_PEU_CE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_LOG_ENABLE) | |
558 | #define PCIERPT_PEU_CE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_ENABLE) | |
559 | #define PCIERPT_PEU_CE_INTERRUPT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_STATUS) | |
560 | #define PCIERPT_PEU_CE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CE_STATUS_SET) | |
561 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE) | |
562 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE) | |
563 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS) | |
564 | #define PCIERPT_PEU_CXPL_EVENT_ERROR_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET) | |
565 | ! struct/union LDC_CONSPKT_SIZE size 0x40 | |
566 | uc 0x0 0x1 LDC_CONS_TYPE | |
567 | uc 0x1 0x1 LDC_CONS_SIZE | |
568 | u 0x4 0x4 LDC_CONS_CTRL_MSG | |
569 | ! array LDC_CONS_PAYLOAD @ 0x8 size 0x1c0 : element size 0x1 | |
570 | uc 0x8 0x1 LDC_CONS_PAYLOAD | |
571 | ! struct/union CONSOLE_SIZE size 0x248 | |
572 | uc 0x0 0x1 CONS_TYPE | |
573 | u 0x18 0x8 CONS_UARTBASE | |
574 | uc 0x20 0x1 CONS_STATUS | |
575 | u 0x28 0x8 CONS_ENDPT | |
576 | u 0x30 0x8 CONS_INHEAD | |
577 | u 0x38 0x8 CONS_INTAIL | |
578 | p 0x40 0x8 CONS_VINTR_MAPREG | |
579 | ! array CONS_INBUF @ 0x48 size 0x1000 : element size 0x8 | |
580 | u 0x48 0x8 CONS_INBUF | |
581 | ! struct/union HVDISK_SIZE size 0x10 | |
582 | u 0x0 0x8 DISK_PA | |
583 | u 0x8 0x8 DISK_SIZE | |
584 | ! struct/union LDC_ENDPOINT_SIZE size 0x110 | |
585 | uc 0x1 0x1 LDC_IS_LIVE | |
586 | uc 0x2 0x1 LDC_IS_PRIVATE | |
587 | uc 0x3 0x1 LDC_IS_SVC_ID | |
588 | uc 0x4 0x1 LDC_RX_UPDATED | |
589 | uc 0x5 0x1 LDC_TXQ_FULL | |
590 | u 0x8 0x8 LDC_TX_QBASE_RA | |
591 | u 0x10 0x8 LDC_TX_QBASE_PA | |
592 | u 0x18 0x8 LDC_TX_QSIZE | |
593 | u 0x20 0x4 LDC_TX_QHEAD | |
594 | u 0x24 0x4 LDC_TX_QTAIL | |
595 | u 0x28 0x8 LDC_TX_CB | |
596 | u 0x30 0x8 LDC_TX_CBARG | |
597 | ! struct LDC_TX_MAPREG @ 0x38 has size 0x28 | |
598 | u 0x60 0x8 LDC_RX_QBASE_RA | |
599 | u 0x68 0x8 LDC_RX_QBASE_PA | |
600 | u 0x70 0x8 LDC_RX_QSIZE | |
601 | u 0x78 0x4 LDC_RX_QHEAD | |
602 | u 0x7c 0x4 LDC_RX_QTAIL | |
603 | u 0x80 0x8 LDC_RX_CB | |
604 | u 0x88 0x8 LDC_RX_CBARG | |
605 | ! struct LDC_RX_MAPREG @ 0x90 has size 0x28 | |
606 | p 0xb8 0x8 LDC_RX_VINTR_COOKIE | |
607 | uc 0xc0 0x1 LDC_TARGET_TYPE | |
608 | p 0xc8 0x8 LDC_TARGET_GUEST | |
609 | u 0xd0 0x8 LDC_TARGET_CHANNEL | |
610 | u 0xd8 0x8 LDC_MAP_TABLE_RA | |
611 | u 0xe0 0x8 LDC_MAP_TABLE_PA | |
612 | u 0xe8 0x8 LDC_MAP_TABLE_NENTRIES | |
613 | u 0xf0 0x8 LDC_MAP_TABLE_SZ | |
614 | ! struct/union VERSION_SIZE size 0x10 | |
615 | u 0x0 0x8 VERSION_NUM | |
616 | p 0x8 0x8 VERSION_PTR | |
617 | #define VERSION_MAJOR (VERSION_NUM+MAJOR_OFF) | |
618 | #define VERSION_MINOR (VERSION_NUM+MINOR_OFF) | |
619 | ! struct/union LDC_MAPREG_SIZE size 0x28 | |
620 | u 0x0 0x4 LDC_MAPREG_STATE | |
621 | uc 0x4 0x1 LDC_MAPREG_VALID | |
622 | u 0x8 0x8 LDC_MAPREG_INO | |
623 | u 0x10 0x8 LDC_MAPREG_CPUP | |
624 | u 0x18 0x8 LDC_MAPREG_COOKIE | |
625 | u 0x20 0x8 LDC_MAPREG_ENDPOINT | |
626 | u 0x0 0x8 WATCHDOG_TICKS | |
627 | ! struct/union LDC_I2E_SIZE size 0x10 | |
628 | p 0x0 0x8 LDC_I2E_ENDPOINT | |
629 | p 0x8 0x8 LDC_I2E_MAPREG | |
630 | ! struct/union SP_LDC_ENDPOINT_SIZE size 0xe8 | |
631 | uc 0x0 0x1 LDC_CHANNEL_IDX | |
632 | uc 0x1 0x1 SP_LDC_IS_LIVE | |
633 | uc 0x2 0x1 SP_LDC_TARGET_TYPE | |
634 | p 0x8 0x8 SP_LDC_TX_QD_PA | |
635 | p 0x10 0x8 SP_LDC_RX_QD_PA | |
636 | p 0x18 0x8 SP_LDC_TARGET_GUEST | |
637 | u 0x20 0x8 SP_LDC_TARGET_CHANNEL | |
638 | u 0x28 0x8 SP_LDC_TX_LOCK | |
639 | u 0x30 0x8 SP_LDC_RX_LOCK | |
640 | u 0x38 0x4 SP_LDC_TX_SCR_TXHEAD | |
641 | u 0x3c 0x4 SP_LDC_TX_SCR_TXTAIL | |
642 | u 0x40 0x8 SP_LDC_TX_SCR_TXSIZE | |
643 | u 0x48 0x8 SP_LDC_TX_SCR_TX_QPA | |
644 | u 0x50 0x4 SP_LDC_TX_SCR_RXHEAD | |
645 | u 0x54 0x4 SP_LDC_TX_SCR_RXTAIL | |
646 | u 0x58 0x8 SP_LDC_TX_SCR_RXSIZE | |
647 | u 0x60 0x8 SP_LDC_TX_SCR_RX_QPA | |
648 | u 0x68 0x8 SP_LDC_TX_SCR_TARGET | |
649 | u 0x70 0x4 SP_LDC_RX_SCR_TXHEAD | |
650 | u 0x74 0x4 SP_LDC_RX_SCR_TXTAIL | |
651 | u 0x78 0x8 SP_LDC_RX_SCR_TXSIZE | |
652 | u 0x80 0x8 SP_LDC_RX_SCR_TX_QPA | |
653 | u 0x88 0x4 SP_LDC_RX_SCR_RXHEAD | |
654 | u 0x8c 0x4 SP_LDC_RX_SCR_RXTAIL | |
655 | u 0x90 0x8 SP_LDC_RX_SCR_RXSIZE | |
656 | u 0x98 0x8 SP_LDC_RX_SCR_RX_QPA | |
657 | u 0xa0 0x8 SP_LDC_RX_SCR_TARGET | |
658 | ! struct SP_LDC_RX_SCR_PKT @ 0xa8 has size 0x40 | |
659 | ! struct/union SRAM_LDC_QENTRY_SIZE size 0x40 | |
660 | ! array SRAM_LDC_PKT_DATA @ 0x0 size 0x200 : element size 0x8 | |
661 | u 0x0 0x8 SRAM_LDC_PKT_DATA | |
662 | ! struct/union SRAM_LDC_QD_SIZE size 0x140 | |
663 | uc 0x100 0x1 SRAM_LDC_HEAD | |
664 | uc 0x101 0x1 SRAM_LDC_TAIL | |
665 | uc 0x102 0x1 SRAM_LDC_STATE | |
666 | uc 0x103 0x1 SRAM_LDC_STATE_UPDATED | |
667 | uc 0x104 0x1 SRAM_LDC_STATE_NOTIFY | |
668 | ! struct/union LDC_MAPIN_SIZE size 0x30 | |
669 | u 0x0 0x8 LDC_MI_PA | |
670 | u 0x8 0x8 LDC_MI_MMU_MAP | |
671 | u 0x10 0x8 LDC_MI_IO_VA | |
672 | u 0x18 0x8 LDC_MI_VA | |
673 | u 0x20 0x2 LDC_MI_VA_CTX | |
674 | u 0x22 0x2 LDC_MI_LOCAL_ENDPOINT | |
675 | uc 0x24 0x1 LDC_MI_PG_SIZE | |
676 | uc 0x25 0x1 LDC_MI_PERMS | |
677 | u 0x28 0x4 LDC_MI_MAP_TABLE_IDX | |
678 | #define LDC_MI_NEXT_IDX 0 /* clobber 1st word when free */ | |
679 | #define MIE_VA_MMU_SHIFT 0 | |
680 | #define MIE_RA_MMU_SHIFT 8 | |
681 | #define MIE_IO_MMU_SHIFT 16 | |
682 | #define LDC_MI_VA_MMU_MAP (LDC_MI_MMU_MAP + 7) | |
683 | #define LDC_MI_RA_MMU_MAP (LDC_MI_MMU_MAP + 6) | |
684 | #define LDC_MI_IO_MMU_MAP (LDC_MI_MMU_MAP + 5) | |
685 | ! struct/union GUEST_CONS_QUEUES_SIZE size 0x4000 | |
686 | ! array GUEST_CONS_RXQ @ 0x0 size 0x10000 : element size 0x1 | |
687 | uc 0x0 0x1 GUEST_CONS_RXQ | |
688 | ! array GUEST_CONS_TXQ @ 0x2000 size 0x10000 : element size 0x1 | |
689 | uc 0x2000 0x1 GUEST_CONS_TXQ | |
690 | ! struct/union RA2PA_SEGMENT_SIZE size 0x20 | |
691 | u 0x0 0x8 RA2PA_SEGMENT_BASE | |
692 | u 0x8 0x8 RA2PA_SEGMENT_LIMIT | |
693 | u 0x10 0x8 RA2PA_SEGMENT_OFFSET | |
694 | uc 0x18 0x1 RA2PA_SEGMENT_FLAGS | |
695 | ! struct/union GUEST_SIZE size 0x45910 | |
696 | u 0x0 0x8 GUEST_GID | |
697 | p 0x8 0x8 GUEST_CONFIGP | |
698 | u 0x10 0x4 GUEST_STATE | |
699 | u 0x18 0x8 GUEST_STATE_LOCK | |
700 | uc 0x20 0x1 GUEST_SOFT_STATE | |
701 | ! array GUEST_SOFT_STATE_STR @ 0x21 size 0x100 : element size 0x1 | |
702 | uc 0x21 0x1 GUEST_SOFT_STATE_STR | |
703 | u 0x48 0x8 GUEST_SOFT_STATE_LOCK | |
704 | u 0x50 0x8 GUEST_REAL_BASE | |
705 | u 0x58 0x8 GUEST_REAL_LIMIT | |
706 | u 0x60 0x8 GUEST_MEM_OFFSET | |
707 | ! array GUEST_RA2PA_SEGMENT @ 0x68 size 0x4000 : element size 0x20 | |
708 | ! struct GUEST_RA2PA_SEGMENT @ 0x68 has size 0x800 | |
709 | u 0x868 0x8 GUEST_LDC_MAPIN_BASERA | |
710 | u 0x870 0x8 GUEST_LDC_MAPIN_SIZE | |
711 | u 0x878 0x8 GUEST_PERM_MAPPINGS_LOCK | |
712 | ! array GUEST_PERM_MAPPINGS @ 0x880 size 0x800 : element size 0x20 | |
713 | ! struct GUEST_PERM_MAPPINGS @ 0x880 has size 0x100 | |
714 | ! struct GUEST_CONSOLE @ 0x980 has size 0x248 | |
715 | u 0xbc8 0x8 GUEST_TOD_OFFSET | |
716 | u 0xbd0 0x8 GUEST_TTRACE_FRZ | |
717 | ! array GUEST_VCPUS @ 0xbd8 size 0x1000 : element size 0x8 | |
718 | p 0xbd8 0x200 GUEST_VCPUS | |
719 | ! array GUEST_MAUS @ 0xdd8 size 0x200 : element size 0x8 | |
720 | p 0xdd8 0x40 GUEST_MAUS | |
721 | ! array GUEST_CWQS @ 0xe18 size 0x200 : element size 0x8 | |
722 | p 0xe18 0x40 GUEST_CWQS | |
723 | ! array GUEST_API_GROUPS @ 0xe58 size 0x680 : element size 0x10 | |
724 | ! struct GUEST_API_GROUPS @ 0xe58 has size 0xd0 | |
725 | u 0xf28 0x8 GUEST_HCALL_TABLE | |
726 | ! array GUEST_DEV2INST @ 0xf30 size 0x100 : element size 0x1 | |
727 | uc 0xf30 0x1 GUEST_DEV2INST | |
728 | ! struct GUEST_VINO2INST @ 0xf50 has size 0x800 | |
729 | ! struct GUEST_VDEV_STATE @ 0x1750 has size 0x1010 | |
730 | u 0x2760 0x8 GUEST_MD_PA | |
731 | u 0x2768 0x8 GUEST_MD_SIZE | |
732 | u 0x2770 0x8 GUEST_DUMPBUF_PA | |
733 | u 0x2778 0x8 GUEST_DUMPBUF_RA | |
734 | u 0x2780 0x8 GUEST_DUMPBUF_SIZE | |
735 | u 0x2788 0x8 GUEST_ENTRY | |
736 | u 0x2790 0x8 GUEST_ROM_BASE | |
737 | u 0x2798 0x8 GUEST_ROM_SIZE | |
738 | u 0x27a0 0x8 GUEST_PERFREG_ACCESSIBLE | |
739 | u 0x27a8 0x8 GUEST_DIAGPRIV | |
740 | u 0x27b0 0x8 GUEST_RESET_REASON | |
741 | u 0x27b8 0x8 GUEST_PERFREGHT_ACCESSIBLE | |
742 | u 0x27c0 0x8 GUEST_RNG_CTL_ACCESSIBLE | |
743 | ! struct GUEST_WATCHDOG @ 0x27c8 has size 0x8 | |
744 | ! struct GUEST_DISK @ 0x27d0 has size 0x10 | |
745 | u 0x27e0 0x8 GUEST_LDC_MAX_CHANNEL_IDX | |
746 | u 0x27e8 0x8 GUEST_LDC_MAPIN_FREE_IDX | |
747 | ! array GUEST_LDC_ENDPOINT @ 0x27f0 size 0x88000 : element size 0x110 | |
748 | ! struct GUEST_LDC_ENDPOINT @ 0x27f0 has size 0x11000 | |
749 | ! array GUEST_LDC_MAPIN @ 0x137f0 size 0x180000 : element size 0x30 | |
750 | ! struct GUEST_LDC_MAPIN @ 0x137f0 has size 0x30000 | |
751 | ! array GUEST_LDC_I2E @ 0x437f0 size 0x10000 : element size 0x10 | |
752 | ! struct GUEST_LDC_I2E @ 0x437f0 has size 0x2000 | |
753 | ! array GUEST_ASYNC_BUSY @ 0x45878 size 0x20 : element size 0x1 | |
754 | uc 0x45878 0x1 GUEST_ASYNC_BUSY | |
755 | ! array GUEST_ASYNC_LOCK @ 0x45880 size 0x100 : element size 0x8 | |
756 | u 0x45880 0x8 GUEST_ASYNC_LOCK | |
757 | ! array GUEST_ASYNC_BUF @ 0x458a0 size 0x200 : element size 0x8 | |
758 | u 0x458a0 0x8 GUEST_ASYNC_BUF | |
759 | u 0x458e0 0x8 GUEST_START_STICK | |
760 | ! struct GUEST_UTIL @ 0x458e8 has size 0x10 | |
761 | ! struct GUEST_MGUEST @ 0x45908 has size 0x8 | |
762 | ! struct/union GUEST_UTIL_SIZE size 0x10 | |
763 | u 0x0 0x8 GUTIL_STICK_LAST | |
764 | u 0x8 0x8 GUTIL_STOPPED_CYCLES | |
765 | ! struct/union HVCTL_RES_STATUS_SIZE size 0x38 | |
766 | u 0x0 0x4 HVCTL_RES_STATUS_RES | |
767 | u 0x4 0x4 HVCTL_RES_STATUS_RESID | |
768 | u 0x8 0x4 HVCTL_RES_STATUS_INFOID | |
769 | u 0xc 0x4 HVCTL_RES_STATUS_CODE | |
770 | ! array HVCTL_RES_STATUS_DATA @ 0x10 size 0x140 : element size 0x1 | |
771 | uc 0x10 0x1 HVCTL_RES_STATUS_DATA | |
772 | ! struct/union RS_GUEST_SOFT_STATE_SIZE size 0x21 | |
773 | uc 0x0 0x1 RS_GUEST_SOFT_STATE | |
774 | ! array RS_GUEST_SOFT_STATE_STR @ 0x1 size 0x100 : element size 0x1 | |
775 | sc 0x1 0x1 RS_GUEST_SOFT_STATE_STR | |
776 | ! struct/union DEVOPSVEC_SIZE size 0x180 | |
777 | p 0x0 0x8 DEVOPSVEC_DEVINO2VINO | |
778 | p 0x8 0x8 DEVOPSVEC_MONDO_RECEIVE | |
779 | p 0x10 0x8 DEVOPSVEC_GETVALID | |
780 | p 0x18 0x8 DEVOPSVEC_SETVALID | |
781 | p 0x20 0x8 DEVOPSVEC_GETSTATE | |
782 | p 0x28 0x8 DEVOPSVEC_SETSTATE | |
783 | p 0x30 0x8 DEVOPSVEC_GETTARGET | |
784 | p 0x38 0x8 DEVOPSVEC_SETTARGET | |
785 | p 0x40 0x8 DEVOPSVEC_MAP | |
786 | p 0x48 0x8 DEVOPSVEC_MAP_V2 | |
787 | p 0x50 0x8 DEVOPSVEC_GETMAP | |
788 | p 0x58 0x8 DEVOPSVEC_GETMAP_V2 | |
789 | p 0x60 0x8 DEVOPSVEC_UNMAP | |
790 | p 0x68 0x8 DEVOPSVEC_GETBYPASS | |
791 | p 0x70 0x8 DEVOPSVEC_CONFIGGET | |
792 | p 0x78 0x8 DEVOPSVEC_CONFIGPUT | |
793 | p 0x80 0x8 DEVOPSVEC_IOPEEK | |
794 | p 0x88 0x8 DEVOPSVEC_IOPOKE | |
795 | p 0x90 0x8 DEVOPSVEC_DMASYNC | |
796 | p 0x98 0x8 DEVOPSVEC_MSIQ_CONF | |
797 | p 0xa0 0x8 DEVOPSVEC_MSIQ_INFO | |
798 | p 0xa8 0x8 DEVOPSVEC_MSIQ_GETVALID | |
799 | p 0xb0 0x8 DEVOPSVEC_MSIQ_SETVALID | |
800 | p 0xb8 0x8 DEVOPSVEC_MSIQ_GETSTATE | |
801 | p 0xc0 0x8 DEVOPSVEC_MSIQ_SETSTATE | |
802 | p 0xc8 0x8 DEVOPSVEC_MSIQ_GETHEAD | |
803 | p 0xd0 0x8 DEVOPSVEC_MSIQ_SETHEAD | |
804 | p 0xd8 0x8 DEVOPSVEC_MSIQ_GETTAIL | |
805 | p 0xe0 0x8 DEVOPSVEC_MSI_GETVALID | |
806 | p 0xe8 0x8 DEVOPSVEC_MSI_SETVALID | |
807 | p 0xf0 0x8 DEVOPSVEC_MSI_GETSTATE | |
808 | p 0xf8 0x8 DEVOPSVEC_MSI_SETSTATE | |
809 | p 0x100 0x8 DEVOPSVEC_MSI_GETMSIQ | |
810 | p 0x108 0x8 DEVOPSVEC_MSI_SETMSIQ | |
811 | p 0x110 0x8 DEVOPSVEC_MSI_MSG_GETMSIQ | |
812 | p 0x118 0x8 DEVOPSVEC_MSI_MSG_SETMSIQ | |
813 | p 0x120 0x8 DEVOPSVEC_MSI_MSG_GETVALID | |
814 | p 0x128 0x8 DEVOPSVEC_MSI_MSG_SETVALID | |
815 | p 0x130 0x8 DEVOPSVEC_GETPERFREG | |
816 | p 0x138 0x8 DEVOPSVEC_SETPERFREG | |
817 | p 0x140 0x8 DEVOPSVEC_VGETCOOKIE | |
818 | p 0x148 0x8 DEVOPSVEC_VSETCOOKIE | |
819 | p 0x150 0x8 DEVOPSVEC_VGETVALID | |
820 | p 0x158 0x8 DEVOPSVEC_VSETVALID | |
821 | p 0x160 0x8 DEVOPSVEC_VGETTARGET | |
822 | p 0x168 0x8 DEVOPSVEC_VSETTARGET | |
823 | p 0x170 0x8 DEVOPSVEC_VGETSTATE | |
824 | p 0x178 0x8 DEVOPSVEC_VSETSTATE | |
825 | ! struct/union VINO2INST_SIZE size 0x800 | |
826 | ! array VINO2INST_VINO @ 0x0 size 0x4000 : element size 0x1 | |
827 | uc 0x0 0x1 VINO2INST_VINO | |
828 | ! struct/union PIU_COOKIE_SIZE size 0x3c0 | |
829 | u 0x0 0x8 PIU_COOKIE_HANDLE | |
830 | u 0x8 0x8 PIU_COOKIE_NCU | |
831 | u 0x10 0x8 PIU_COOKIE_PCIE | |
832 | u 0x18 0x8 PIU_COOKIE_CFG | |
833 | u 0x30 0x8 PIU_COOKIE_PERFREGS | |
834 | u 0x38 0x8 PIU_COOKIE_EQCTLSET | |
835 | u 0x40 0x8 PIU_COOKIE_EQCTLCLR | |
836 | u 0x48 0x8 PIU_COOKIE_EQSTATE | |
837 | u 0x50 0x8 PIU_COOKIE_EQTAIL | |
838 | u 0x58 0x8 PIU_COOKIE_EQHEAD | |
839 | u 0x60 0x8 PIU_COOKIE_MSIMAP | |
840 | u 0x68 0x8 PIU_COOKIE_MSICLR | |
841 | u 0x70 0x8 PIU_COOKIE_MSGMAP | |
842 | u 0x80 0x8 PIU_COOKIE_MMUFLUSH | |
843 | u 0x88 0x8 PIU_COOKIE_INTCLR | |
844 | u 0x90 0x8 PIU_COOKIE_INTMAP | |
845 | p 0x98 0x8 PIU_COOKIE_VIRTUAL_INTMAP | |
846 | u 0xa0 0x8 PIU_COOKIE_ERR_LOCK | |
847 | u 0xa8 0x8 PIU_COOKIE_ERR_LOCK_COUNTER | |
848 | u 0xb0 0x8 PIU_COOKIE_OE_STATUS | |
849 | u 0xb8 0x2 PIU_COOKIE_INOMAX | |
850 | u 0xba 0x2 PIU_COOKIE_VINO | |
851 | p 0xc0 0x8 PIU_COOKIE_IOTSB0 | |
852 | p 0xc8 0x8 PIU_COOKIE_IOTSB1 | |
853 | p 0xd0 0x8 PIU_COOKIE_MSIEQBASE | |
854 | p 0xd8 0x8 PIU_COOKIE_MSICOOKIE | |
855 | p 0xe0 0x8 PIU_COOKIE_ERRCOOKIE | |
856 | ! struct PIU_COOKIE_DMU_ERPT @ 0xe8 has size 0x168 | |
857 | ! struct PIU_COOKIE_PEU_ERPT @ 0x250 has size 0x168 | |
858 | #define PIU_COOKIE_BLACKLIST 0x3b8 | |
859 | ! struct/union PIU_MSIEQ_SIZE size 0x28 | |
860 | u 0x0 0x8 PIU_MSIEQ_EQMASK | |
861 | p 0x8 0x8 PIU_MSIEQ_BASE | |
862 | p 0x10 0x8 PIU_MSIEQ_GUEST | |
863 | u 0x18 0x8 PIU_MSIEQ_WORD0 | |
864 | u 0x20 0x8 PIU_MSIEQ_WORD1 | |
865 | ! struct/union PIU_MSI_COOKIE_SIZE size 0x5a8 | |
866 | p 0x0 0x8 PIU_MSI_COOKIE_PIU | |
867 | ! array PIU_MSI_COOKIE_EQ @ 0x8 size 0x2d00 : element size 0x28 | |
868 | ! struct PIU_MSI_COOKIE_EQ @ 0x8 has size 0x5a0 | |
869 | ! struct/union PIU_ERR_COOKIE_SIZE size 0x18 | |
870 | p 0x0 0x8 PIU_ERR_COOKIE_PIU | |
871 | ! array PIU_ERR_COOKIE_STATE @ 0x8 size 0x80 : element size 0x8 | |
872 | u 0x8 0x8 PIU_ERR_COOKIE_STATE | |
873 | ! struct/union VDEV_STATE_SIZE size 0x1010 | |
874 | u 0x0 0x8 VDEV_STATE_HANDLE | |
875 | ! array VDEV_STATE_MAPREG @ 0x8 size 0x8000 : element size 0x40 | |
876 | ! struct VDEV_STATE_MAPREG @ 0x8 has size 0x1000 | |
877 | u 0x1008 0x2 VDEV_STATE_INOMAX | |
878 | u 0x100a 0x2 VDEV_STATE_VINOBASE | |
879 | u 0x0 0x8 SVC_LINK_SIZE | |
880 | u 0x8 0x8 SVC_LINK_PA | |
881 | p 0x10 0x8 SVC_LINK_NEXT | |
882 | u 0x0 0x8 SVC_CALLBACK_RX | |
883 | u 0x8 0x8 SVC_CALLBACK_TX | |
884 | u 0x10 0x8 SVC_CALLBACK_COOKIE | |
885 | ! struct/union SVC_CTRL_SIZE size 0x80 | |
886 | u 0x0 0x4 SVC_CTRL_XID | |
887 | u 0x4 0x4 SVC_CTRL_SID | |
888 | u 0x8 0x4 SVC_CTRL_INO | |
889 | u 0xc 0x4 SVC_CTRL_MTU | |
890 | u 0x10 0x4 SVC_CTRL_CONFIG | |
891 | u 0x14 0x4 SVC_CTRL_STATE | |
892 | u 0x18 0x4 SVC_CTRL_COUNT | |
893 | u 0x1c 0x4 SVC_CTRL_DSTATE | |
894 | u 0x20 0x8 SVC_CTRL_LOCK | |
895 | u 0x28 0x8 SVC_CTRL_INTR_COOKIE | |
896 | ! struct SVC_CTRL_CALLBACK @ 0x30 has size 0x18 | |
897 | p 0x48 0x8 SVC_CTRL_LINK | |
898 | ! struct SVC_CTRL_RECV @ 0x50 has size 0x18 | |
899 | ! struct SVC_CTRL_SEND @ 0x68 has size 0x18 | |
900 | ! struct/union HV_SVC_DATA_SIZE size 0x4e0 | |
901 | u 0x0 0x8 HV_SVC_DATA_RXBASE | |
902 | u 0x8 0x8 HV_SVC_DATA_TXBASE | |
903 | u 0x10 0x8 HV_SVC_DATA_RXCHANNEL | |
904 | u 0x18 0x8 HV_SVC_DATA_TXCHANNEL | |
905 | ! array HV_SVC_DATA_SCR @ 0x20 size 0x80 : element size 0x8 | |
906 | u 0x20 0x8 HV_SVC_DATA_SCR | |
907 | u 0x30 0x4 HV_SVC_DATA_NUM_SVCS | |
908 | u 0x34 0x4 HV_SVC_DATA_SENDBUSY | |
909 | p 0x38 0x8 HV_SVC_DATA_SENDH | |
910 | p 0x40 0x8 HV_SVC_DATA_SENDT | |
911 | p 0x48 0x8 HV_SVC_DATA_SENDDH | |
912 | p 0x50 0x8 HV_SVC_DATA_SENDDT | |
913 | u 0x58 0x8 HV_SVC_DATA_LOCK | |
914 | ! array HV_SVC_DATA_SVC @ 0x60 size 0x2400 : element size 0x80 | |
915 | ! struct HV_SVC_DATA_SVC @ 0x60 has size 0x480 | |
916 | ! struct/union SVC_PKT_SIZE size 0x8 | |
917 | u 0x0 0x4 SVC_PKT_XID | |
918 | u 0x4 0x2 SVC_PKT_SUM | |
919 | u 0x6 0x2 SVC_PKT_SID | |
920 | ! struct/union MAPREG_SIZE size 0x40 | |
921 | uc 0x0 0x1 MAPREG_STATE | |
922 | uc 0x1 0x1 MAPREG_VALID | |
923 | u 0x2 0x2 MAPREG_PCPU | |
924 | u 0x4 0x2 MAPREG_VCPU | |
925 | uc 0x6 0x1 MAPREG_INO | |
926 | u 0x8 0x8 MAPREG_DATA0 | |
927 | u 0x10 0x8 MAPREG_DEVCOOKIE | |
928 | u 0x18 0x8 MAPREG_GETSTATE | |
929 | u 0x20 0x8 MAPREG_SETSTATE | |
930 | ! struct/union DTHDR_SIZE size 0x10 | |
931 | u 0x0 0x4 DTHDR_VER | |
932 | u 0x4 0x4 DTHDR_NODESZ | |
933 | u 0x8 0x4 DTHDR_NAMES | |
934 | u 0xc 0x4 DTHDR_DATA | |
935 | ! struct/union DTNODE_SIZE size 0x10 | |
936 | uc 0x0 0x1 DTNODE_TAG | |
937 | ! union DTNODE_DATA @ 0x8 has size 0x8 | |
938 | ! struct/union TRAPGLOBALS_SIZE size 0x40 | |
939 | ! array G @ 0x0 size 0x200 : element size 0x8 | |
940 | u 0x0 0x8 G | |
941 | ! struct/union TRAPSTATE_SIZE size 0x28 | |
942 | u 0x0 0x8 TRAPSTATE_HTSTATE | |
943 | u 0x8 0x8 TRAPSTATE_TSTATE | |
944 | u 0x10 0x8 TRAPSTATE_TT | |
945 | u 0x18 0x8 TRAPSTATE_TPC | |
946 | u 0x20 0x8 TRAPSTATE_TNPC | |
947 | ! struct/union DBGERROR_PAYLOAD_SIZE size 0x1f8 | |
948 | ! array DBGERROR_DATA @ 0x0 size 0xfc0 : element size 0x8 | |
949 | u 0x0 0x8 DBGERROR_DATA | |
950 | ! struct/union DBGERROR_SIZE size 0x200 | |
951 | u 0x0 0x8 DBGERROR_ERROR_SVCH | |
952 | ! struct DBGERROR_PAYLOAD @ 0x8 has size 0x1f8 | |
953 | ! struct/union DEVINST_SIZE size 0x10 | |
954 | p 0x0 0x8 DEVINST_COOKIE | |
955 | p 0x8 0x8 DEVINST_OPS | |
956 | ! struct/union ERPT_SVC_PKT_SIZE size 0x10 | |
957 | u 0x0 0x8 ERPT_PKT_ADDR | |
958 | u 0x8 0x8 ERPT_PKT_SIZE | |
959 | ! struct/union MAU_QUEUE_SIZE size 0x50 | |
960 | u 0x0 0x8 MQ_LOCK | |
961 | u 0x8 0x4 MQ_STATE | |
962 | u 0xc 0x4 MQ_BUSY | |
963 | u 0x10 0x8 MQ_BASE | |
964 | u 0x18 0x8 MQ_BASE_RA | |
965 | u 0x20 0x8 MQ_END | |
966 | u 0x28 0x8 MQ_HEAD | |
967 | u 0x30 0x8 MQ_HEAD_MARKER | |
968 | u 0x38 0x8 MQ_TAIL | |
969 | u 0x40 0x8 MQ_NENTRIES | |
970 | u 0x48 0x8 MQ_CPU_PID | |
971 | ! struct/union CWQ_QUEUE_SIZE size 0x10d0 | |
972 | u 0x0 0x8 CQ_LOCK | |
973 | u 0x8 0x4 CQ_STATE | |
974 | u 0xc 0x4 CQ_BUSY | |
975 | u 0x10 0x8 CQ_DR_BASE_RA | |
976 | u 0x18 0x8 CQ_DR_BASE | |
977 | u 0x20 0x8 CQ_DR_LAST | |
978 | u 0x28 0x8 CQ_DR_HEAD | |
979 | u 0x30 0x8 CQ_DR_TAIL | |
980 | u 0x38 0x8 CQ_BASE | |
981 | u 0x40 0x8 CQ_LAST | |
982 | u 0x48 0x8 CQ_HEAD | |
983 | u 0x50 0x8 CQ_HEAD_MARKER | |
984 | u 0x58 0x8 CQ_TAIL | |
985 | u 0x60 0x8 CQ_NENTRIES | |
986 | u 0x68 0x8 CQ_CPU_PID | |
987 | u 0x70 0x8 CQ_SCR1 | |
988 | u 0x78 0x8 CQ_SCR2 | |
989 | u 0x80 0x8 CQ_SCR3 | |
990 | u 0x88 0x8 CQ_DR_HV_OFFSET | |
991 | ! array CQ_HV_CWS @ 0x90 size 0x8200 : element size 0x40 | |
992 | ! struct CQ_HV_CWS @ 0x90 has size 0x1040 | |
993 | ! struct/union NCS_HVDESC_SIZE size 0x40 | |
994 | u 0x0 0x8 NHD_STATE | |
995 | u 0x8 0x8 NHD_TYPE | |
996 | ! struct NHD_REGS @ 0x10 has size 0x20 | |
997 | u 0x30 0x8 NHD_ERRSTATUS | |
998 | ! struct/union MA_REGS_SIZE size 0x20 | |
999 | ! union MR_CTL @ 0x0 has size 0x8 | |
1000 | ! union MR_MPA @ 0x8 has size 0x8 | |
1001 | ! union MR_MA @ 0x10 has size 0x8 | |
1002 | u 0x18 0x8 MR_NP | |
1003 | ! struct/union NCS_QCONF_ARG_SIZE size 0x20 | |
1004 | u 0x0 0x8 NQ_MID | |
1005 | u 0x8 0x8 NQ_BASE | |
1006 | u 0x10 0x8 NQ_END | |
1007 | u 0x18 0x8 NQ_NENTRIES | |
1008 | ! struct/union NCS_QTAIL_UPDATE_ARG_SIZE size 0x18 | |
1009 | u 0x0 0x8 NU_MID | |
1010 | u 0x8 0x8 NU_TAIL | |
1011 | u 0x10 0x8 NU_SYNCFLAG | |
1012 | ! struct/union CWQ_CW_RET_SIZE size 0x8 | |
1013 | u 0x0 0x8 CW_RET_DST_ADDR | |
1014 | u 0x0 0x8 CW_RET_CSR | |
1015 | ! struct/union CWQ_CW_SIZE size 0x40 | |
1016 | u 0x0 0x8 CW_CTLBITS | |
1017 | u 0x8 0x8 CW_SRC_ADDR | |
1018 | u 0x10 0x8 CW_AUTH_KEY_ADDR | |
1019 | u 0x18 0x8 CW_AUTH_IV_ADDR | |
1020 | u 0x20 0x8 CW_FINAL_AUTH_STATE_ADDR | |
1021 | u 0x28 0x8 CW_ENC_KEY_ADDR | |
1022 | u 0x30 0x8 CW_ENC_IV_ADDR | |
1023 | ! union CW_RET @ 0x38 has size 0x8 | |
1024 | #define CW_DST_ADDR (CW_RET + CW_RET_DST_ADDR) | |
1025 | #define CW_CSR (CW_RET + CW_RET_DST_ADDR) | |
1026 | ! struct/union CRYPTO_INTR_SIZE size 0x18 | |
1027 | u 0x0 0x8 CI_COOKIE | |
1028 | u 0x8 0x8 CI_ACTIVE | |
1029 | u 0x10 0x8 CI_DATA | |
1030 | ! struct/union RNG_CTLREGS_SIZE size 0x20 | |
1031 | u 0x0 0x8 RNG_CTLREGS_REG0 | |
1032 | u 0x8 0x8 RNG_CTLREGS_REG1 | |
1033 | u 0x10 0x8 RNG_CTLREGS_REG2 | |
1034 | u 0x18 0x8 RNG_CTLREGS_REG3 | |
1035 | ! struct/union RNG_CTLDATA_SIZE size 0x38 | |
1036 | ! struct RNG_CTLDATA_REGS @ 0x0 has size 0x20 | |
1037 | u 0x20 0x8 RNG_CTLDATA_STATE | |
1038 | u 0x28 0x8 RNG_CTLDATA_GUESTID | |
1039 | u 0x30 0x8 RNG_CTLDATA_READYTIME | |
1040 | ! struct/union SVCCN_PKT_SIZE size 0x3 | |
1041 | uc 0x0 0x1 SVCCN_PKT_TYPE | |
1042 | uc 0x1 0x1 SVCCN_PKT_LEN | |
1043 | ! array SVCCN_PKT_DATA @ 0x2 size 0x8 : element size 0x1 | |
1044 | uc 0x2 0x1 SVCCN_PKT_DATA | |
1045 | ! struct/union VBSC_CTRL_PKT_SIZE size 0x20 | |
1046 | u 0x0 0x8 VBSC_PKT_CMD | |
1047 | u 0x8 0x8 VBSC_PKT_ARG0 | |
1048 | u 0x10 0x8 VBSC_PKT_ARG1 | |
1049 | u 0x18 0x8 VBSC_PKT_ARG2 | |
1050 | ! struct/union CB_SIZE size 0x20 | |
1051 | u 0x0 0x8 CB_TICK | |
1052 | u 0x8 0x8 CB_HANDLER | |
1053 | u 0x10 0x8 CB_ARG0 | |
1054 | u 0x18 0x8 CB_ARG1 | |
1055 | ! struct/union CY_SIZE size 0x248 | |
1056 | u 0x0 0x8 CY_T0 | |
1057 | ! array CY_CB @ 0x8 size 0x1100 : element size 0x20 | |
1058 | ! struct CY_CB @ 0x8 has size 0x220 | |
1059 | u 0x228 0x8 CY_TICK | |
1060 | u 0x230 0x8 CY_HANDLER | |
1061 | u 0x238 0x8 CY_ARG0 | |
1062 | u 0x240 0x8 CY_ARG1 | |
1063 | #define STRAND_CY_T0 (STRAND_CYCLIC + CY_T0) | |
1064 | #define STRAND_CY_CB (STRAND_CYCLIC + CY_CB) | |
1065 | #define STRAND_CY_TICK (STRAND_CYCLIC + CY_TICK) | |
1066 | #define STRAND_CY_HANDLER (STRAND_CYCLIC + CY_HANDLER) | |
1067 | #define STRAND_CY_ARG0 (STRAND_CYCLIC + CY_ARG0) | |
1068 | #define STRAND_CY_ARG1 (STRAND_CYCLIC + CY_ARG1) | |
1069 | #define STRAND_CY_CB_TICK (STRAND_CYCLIC + CY_CB + CB_TICK) | |
1070 | #define STRAND_CY_CB_HANDLER (STRAND_CYCLIC + CY_CB + CB_HANDLER) | |
1071 | #define STRAND_CY_CB_ARG0 (STRAND_CYCLIC + CY_CB + CB_ARG0) | |
1072 | #define STRAND_CY_CB_ARG1 (STRAND_CYCLIC + CY_CB + CB_ARG1) | |
1073 | #define CB_LAST ((N_CB - 1) * CB_SIZE) | |
1074 | #define STRAND_CY_CB_LAST_TICK (STRAND_CY_CB_TICK + CB_LAST) | |
1075 | ! struct/union ERROR_TABLE_ENTRY_SIZE size 0x48 | |
1076 | ! array ERR_NAME @ 0x0 size 0x80 : element size 0x1 | |
1077 | sc 0x0 0x1 ERR_NAME | |
1078 | p 0x10 0x8 ERR_REPORT_FCN | |
1079 | p 0x18 0x8 ERR_GUEST_REPORT_FCN | |
1080 | p 0x20 0x8 ERR_CORRECT_FCN | |
1081 | p 0x28 0x8 ERR_STORM_FCN | |
1082 | p 0x30 0x8 ERR_PRINT_FCN | |
1083 | u 0x38 0x4 ERR_FLAGS | |
1084 | uc 0x3c 0x1 ERR_SUN4V_RPRT_TYPE | |
1085 | uc 0x3d 0x1 ERR_SUN4V_EDESC | |
1086 | u 0x40 0x4 ERR_REPORT_SIZE | |
1087 | ! struct/union ERR_WAY_SIZE size 0x88 | |
1088 | u 0x0 0x8 ERR_WAY_TAG_AND_ECC | |
1089 | ! array ERR_WAY_DATA_AND_ECC @ 0x8 size 0x400 : element size 0x8 | |
1090 | u 0x8 0x8 ERR_WAY_DATA_AND_ECC | |
1091 | ! struct/union ERR_L2_SIZE size 0x8d0 | |
1092 | u 0x0 0x8 ERR_L2_VDBITS | |
1093 | u 0x8 0x8 ERR_L2_UABITS | |
1094 | ! array ERR_L2_WAYS @ 0x10 size 0x4400 : element size 0x88 | |
1095 | ! struct ERR_L2_WAYS @ 0x10 has size 0x880 | |
1096 | ! array ERR_DRAM_CONTENTS @ 0x890 size 0x200 : element size 0x8 | |
1097 | u 0x890 0x8 ERR_DRAM_CONTENTS | |
1098 | ! struct/union ERR_TLB_SIZE size 0x10 | |
1099 | u 0x0 0x8 ERR_TLB_TAG | |
1100 | u 0x8 0x8 ERR_TLB_DATA | |
1101 | ! struct/union ERR_ICACHE_WAY_SIZE size 0x48 | |
1102 | ! array ERR_ICACHE_WAY_INSTR @ 0x0 size 0x200 : element size 0x8 | |
1103 | u 0x0 0x8 ERR_ICACHE_WAY_INSTR | |
1104 | u 0x40 0x8 ERR_ICACHE_WAY_TAG | |
1105 | ! struct/union ERR_ICACHE_SIZE size 0x240 | |
1106 | ! array ERR_ICACHE_WAY @ 0x0 size 0x1200 : element size 0x48 | |
1107 | ! struct ERR_ICACHE_WAY @ 0x0 has size 0x240 | |
1108 | ! struct/union ERR_DCACHE_WAY_SIZE size 0x18 | |
1109 | ! array ERR_DCACHE_WAY_DATA @ 0x0 size 0x80 : element size 0x8 | |
1110 | u 0x0 0x8 ERR_DCACHE_WAY_DATA | |
1111 | u 0x10 0x8 ERR_DCACHE_WAY_TAG | |
1112 | ! struct/union ERR_DCACHE_SIZE size 0x60 | |
1113 | ! array ERR_DCACHE_WAY @ 0x0 size 0x300 : element size 0x18 | |
1114 | ! struct ERR_DCACHE_WAY @ 0x0 has size 0x60 | |
1115 | ! struct/union ERR_SSI_SIZE size 0x10 | |
1116 | u 0x0 0x8 ERR_SSI_TIMEOUT | |
1117 | u 0x8 0x8 ERR_SSI_LOG | |
1118 | ! struct/union ERR_STB_SIZE size 0x28 | |
1119 | u 0x0 0x8 ERR_STB_DATA | |
1120 | u 0x8 0x8 ERR_STB_DATA_ECC | |
1121 | u 0x10 0x8 ERR_STB_PARITY | |
1122 | u 0x18 0x8 ERR_STB_MARKS | |
1123 | u 0x20 0x8 ERR_STB_CURR_PTR | |
1124 | ! struct/union ERR_SCRATCHPAD_SIZE size 0x10 | |
1125 | u 0x0 0x8 ERR_SCRATCHPAD_DATA | |
1126 | u 0x8 0x8 ERR_SCRATCHPAD_ECC | |
1127 | ! struct/union ERR_TCA_SIZE size 0x10 | |
1128 | u 0x0 0x8 ERR_TCA_DATA | |
1129 | u 0x8 0x8 ERR_TCA_ECC | |
1130 | ! struct/union ERR_REG_SIZE size 0x8 | |
1131 | u 0x0 0x8 ERR_REG_ECC | |
1132 | ! struct/union ERR_TSA_SIZE size 0x78 | |
1133 | u 0x0 0x8 ERR_TSA_ECC | |
1134 | u 0x8 0x8 ERR_TSA_TL | |
1135 | u 0x10 0x8 ERR_TSA_TT | |
1136 | u 0x18 0x8 ERR_TSA_TSTATE | |
1137 | u 0x20 0x8 ERR_TSA_HTSTATE | |
1138 | u 0x28 0x8 ERR_TSA_TPC | |
1139 | u 0x30 0x8 ERR_TSA_TNPC | |
1140 | u 0x38 0x8 ERR_TSA_CPU_MONDO_QHEAD | |
1141 | u 0x40 0x8 ERR_TSA_CPU_MONDO_QTAIL | |
1142 | u 0x48 0x8 ERR_TSA_DEV_MONDO_QHEAD | |
1143 | u 0x50 0x8 ERR_TSA_DEV_MONDO_QTAIL | |
1144 | u 0x58 0x8 ERR_TSA_ERR_RES_QHEAD | |
1145 | u 0x60 0x8 ERR_TSA_ERR_RES_QTAIL | |
1146 | u 0x68 0x8 ERR_TSA_ERR_NONRES_QHEAD | |
1147 | u 0x70 0x8 ERR_TSA_ERR_NONRES_QTAIL | |
1148 | ! struct/union ERR_MMU_ERR_REGS_SIZE size 0x88 | |
1149 | ! array ERR_MMU_PARITY @ 0x0 size 0x40 : element size 0x1 | |
1150 | uc 0x0 0x1 ERR_MMU_PARITY | |
1151 | ! array ERR_MMU_TSB_CFG_CTX0 @ 0x8 size 0x100 : element size 0x8 | |
1152 | u 0x8 0x8 ERR_MMU_TSB_CFG_CTX0 | |
1153 | ! array ERR_MMU_TSB_CFG_CTXNZ @ 0x28 size 0x100 : element size 0x8 | |
1154 | u 0x28 0x8 ERR_MMU_TSB_CFG_CTXNZ | |
1155 | ! array ERR_MMU_REAL_RANGE @ 0x48 size 0x100 : element size 0x8 | |
1156 | u 0x48 0x8 ERR_MMU_REAL_RANGE | |
1157 | ! array ERR_MMU_PHYS_OFFSET @ 0x68 size 0x100 : element size 0x8 | |
1158 | u 0x68 0x8 ERR_MMU_PHYS_OFFSET | |
1159 | ! struct/union ERR_MAMU_SIZE size 0x28 | |
1160 | u 0x0 0x8 ERR_MA_PA | |
1161 | u 0x8 0x8 ERR_MA_ADDR | |
1162 | u 0x10 0x8 ERR_MA_NP | |
1163 | u 0x18 0x8 ERR_MA_CTL | |
1164 | u 0x20 0x8 ERR_MA_SYNC | |
1165 | ! struct/union ERR_TRAP_REGS_SIZE size 0x28 | |
1166 | u 0x0 0x8 ERR_TT | |
1167 | u 0x8 0x8 ERR_TPC | |
1168 | u 0x10 0x8 ERR_TNPC | |
1169 | u 0x18 0x8 ERR_TSTATE | |
1170 | u 0x20 0x8 ERR_HTSTATE | |
1171 | ! struct/union ERR_SOC_SIZE size 0x48 | |
1172 | u 0x0 0x8 ERR_SOC_ESR | |
1173 | u 0x8 0x8 ERR_SOC_ELER | |
1174 | u 0x10 0x8 ERR_SOC_EIER | |
1175 | u 0x18 0x8 ERR_SOC_VCID | |
1176 | u 0x20 0x8 ERR_SOC_FEER | |
1177 | u 0x28 0x8 ERR_SOC_PESR | |
1178 | u 0x30 0x8 ERR_SOC_EIR | |
1179 | u 0x38 0x8 ERR_SOC_SII_SYND | |
1180 | u 0x40 0x8 ERR_SOC_NCU_SYND | |
1181 | ! struct/union ERR_DIAG_DATA_SIZE size 0x8d0 | |
1182 | ! array ERR_DIAG_DATA_DTLB @ 0x0 size 0x4000 : element size 0x10 | |
1183 | ! struct ERR_DIAG_DATA_DTLB @ 0x0 has size 0x800 | |
1184 | ! array ERR_DIAG_DATA_ITLB @ 0x0 size 0x2000 : element size 0x10 | |
1185 | ! struct ERR_DIAG_DATA_ITLB @ 0x0 has size 0x400 | |
1186 | ! struct ERR_DIAG_DATA_ICACHE @ 0x0 has size 0x240 | |
1187 | ! struct ERR_DIAG_DATA_DCACHE @ 0x0 has size 0x60 | |
1188 | ! struct ERR_DIAG_DATA_SSI_INFO @ 0x0 has size 0x10 | |
1189 | ! struct ERR_DIAG_DATA_STB @ 0x0 has size 0x28 | |
1190 | ! struct ERR_DIAG_DATA_SCRATCHPAD @ 0x0 has size 0x10 | |
1191 | ! struct ERR_DIAG_DATA_TSA @ 0x0 has size 0x78 | |
1192 | ! struct ERR_DIAG_DATA_MMU_REGS @ 0x0 has size 0x88 | |
1193 | ! struct ERR_DIAG_DATA_MAMU @ 0x0 has size 0x28 | |
1194 | ! struct ERR_DIAG_DATA_SOC @ 0x0 has size 0x48 | |
1195 | ! struct ERR_DIAG_DATA_TCA @ 0x0 has size 0x10 | |
1196 | ! struct ERR_DIAG_DATA_REG @ 0x0 has size 0x8 | |
1197 | ! struct ERR_DIAG_DATA_L2_CACHE @ 0x0 has size 0x8d0 | |
1198 | ! array ERR_DIAG_DATA_TRAP_REGS @ 0x0 size 0x780 : element size 0x28 | |
1199 | ! struct ERR_DIAG_DATA_TRAP_REGS @ 0x0 has size 0xf0 | |
1200 | uc 0x0 0x1 ERR_DIAG_DATA_REG_INFO | |
1201 | ! struct/union ERR_ABORT_DATA_SIZE size 0x800 | |
1202 | ! array ERR_ABORT_VERSION @ 0x0 size 0x200 : element size 0x1 | |
1203 | uc 0x0 0x1 ERR_ABORT_VERSION | |
1204 | u 0x40 0x8 ERR_ABORT_PC | |
1205 | u 0x48 0x8 ERR_ABORT_CWP | |
1206 | ! array ERR_ABORT_TRAP_REGS @ 0x50 size 0x780 : element size 0x28 | |
1207 | ! struct ERR_ABORT_TRAP_REGS @ 0x50 has size 0xf0 | |
1208 | ! array ERR_ABORT_GLOBAL_REGS @ 0x140 size 0x600 : element size 0x8 | |
1209 | u 0x140 0x8 ERR_ABORT_GLOBAL_REGS | |
1210 | ! array ERR_ABORT_REG_WINDOWS @ 0x200 size 0x3000 : element size 0x8 | |
1211 | u 0x200 0x8 ERR_ABORT_REG_WINDOWS | |
1212 | ! struct/union ERR_DIAG_BUF_SIZE size 0xa98 | |
1213 | u 0x0 0x8 ERR_DIAG_BUF_SPARC_ISFSR | |
1214 | u 0x8 0x8 ERR_DIAG_BUF_SPARC_DSFSR | |
1215 | u 0x10 0x8 ERR_DIAG_BUF_SPARC_DSFAR | |
1216 | u 0x18 0x8 ERR_DIAG_BUF_SPARC_DESR | |
1217 | u 0x20 0x8 ERR_DIAG_BUF_SPARC_DFESR | |
1218 | ! array ERR_DIAG_BUF_L2_CACHE_ESR @ 0x28 size 0x200 : element size 0x8 | |
1219 | u 0x28 0x8 ERR_DIAG_BUF_L2_CACHE_ESR | |
1220 | ! array ERR_DIAG_BUF_L2_CACHE_EAR @ 0x68 size 0x200 : element size 0x8 | |
1221 | u 0x68 0x8 ERR_DIAG_BUF_L2_CACHE_EAR | |
1222 | ! array ERR_DIAG_BUF_L2_CACHE_ND @ 0xa8 size 0x200 : element size 0x8 | |
1223 | u 0xa8 0x8 ERR_DIAG_BUF_L2_CACHE_ND | |
1224 | ! array ERR_DIAG_BUF_DRAM_ESR @ 0xe8 size 0x100 : element size 0x8 | |
1225 | u 0xe8 0x8 ERR_DIAG_BUF_DRAM_ESR | |
1226 | ! array ERR_DIAG_BUF_DRAM_EAR @ 0x108 size 0x100 : element size 0x8 | |
1227 | u 0x108 0x8 ERR_DIAG_BUF_DRAM_EAR | |
1228 | ! array ERR_DIAG_BUF_DRAM_CTR @ 0x128 size 0x100 : element size 0x8 | |
1229 | u 0x128 0x8 ERR_DIAG_BUF_DRAM_CTR | |
1230 | ! array ERR_DIAG_BUF_DRAM_LOC @ 0x148 size 0x100 : element size 0x8 | |
1231 | u 0x148 0x8 ERR_DIAG_BUF_DRAM_LOC | |
1232 | ! array ERR_DIAG_BUF_DRAM_FBD @ 0x168 size 0x100 : element size 0x8 | |
1233 | u 0x168 0x8 ERR_DIAG_BUF_DRAM_FBD | |
1234 | ! array ERR_DIAG_BUF_DRAM_RETRY @ 0x188 size 0x100 : element size 0x8 | |
1235 | u 0x188 0x8 ERR_DIAG_BUF_DRAM_RETRY | |
1236 | u 0x1a8 0x8 ERR_DIAG_L2_BANK | |
1237 | u 0x1b0 0x8 ERR_DIAG_L2_LINE_STATE | |
1238 | u 0x1b8 0x8 ERR_DIAG_L2_PA | |
1239 | ! union ERR_DIAG_BUF_DIAG_DATA @ 0x1c0 has size 0x8d0 | |
1240 | u 0xa90 0x4 ERR_DIAG_BUF_RPRT_IN_USE | |
1241 | u 0xa94 0x4 ERR_DIAG_BUF_RPRT_SIZE | |
1242 | ! struct/union CPU_SUN4V_RPRT_SIZE size 0x40 | |
1243 | u 0x0 0x8 CPU_SUN4V_RPRT_G_EHDL | |
1244 | u 0x8 0x8 CPU_SUN4V_RPRT_G_STICK | |
1245 | u 0x10 0x4 CPU_SUN4V_RPRT_EDESC | |
1246 | u 0x14 0x4 CPU_SUN4V_RPRT_ATTR | |
1247 | u 0x18 0x8 CPU_SUN4V_RPRT_ADDR | |
1248 | u 0x20 0x4 CPU_SUN4V_RPRT_SZ | |
1249 | u 0x24 0x2 CPU_SUN4V_RPRT_G_CPUID | |
1250 | u 0x26 0x2 CPU_SUN4V_RPRT_G_SECS | |
1251 | uc 0x28 0x1 CPU_SUN4V_RPRT_ASI | |
1252 | u 0x2a 0x2 CPU_SUN4V_RPRT_REG | |
1253 | u 0x2c 0x4 CPU_SUN4V_RPRT_WORD6 | |
1254 | u 0x30 0x8 CPU_SUN4V_RPRT_WORD7 | |
1255 | u 0x38 0x8 CPU_SUN4V_RPRT_WORD8 | |
1256 | #define ESUN4V_G_EHDL CPU_SUN4V_RPRT_G_EHDL | |
1257 | #define ESUN4V_G_STICK CPU_SUN4V_RPRT_G_STICK | |
1258 | #define ESUN4V_EDESC CPU_SUN4V_RPRT_EDESC | |
1259 | #define ESUN4V_ATTR CPU_SUN4V_RPRT_ATTR | |
1260 | #define ESUN4V_ADDR CPU_SUN4V_RPRT_ADDR | |
1261 | #define ESUN4V_SZ CPU_SUN4V_RPRT_SZ | |
1262 | #define ESUN4V_G_CPUID CPU_SUN4V_RPRT_G_CPUID | |
1263 | #define ESUN4V_G_SECS CPU_SUN4V_RPRT_G_SECS | |
1264 | ! struct/union ERR_SUN4V_RPRT_SIZE size 0x48 | |
1265 | ! union ERR_SUN4V_CPU_ERPT @ 0x0 has size 0x40 | |
1266 | u 0x40 0x8 ERR_SUN4V_RPRT_IN_USE | |
1267 | #define ERR_SUN4V_PCIE_ERPT ERR_SUN4V_CPU_ERPT | |
1268 | #define ERR_SUN4V_RPRT_G_EHDL (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_EHDL) | |
1269 | #define ERR_SUN4V_RPRT_G_STICK (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_STICK) | |
1270 | #define ERR_SUN4V_RPRT_EDESC (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_EDESC) | |
1271 | #define ERR_SUN4V_RPRT_ATTR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ATTR) | |
1272 | #define ERR_SUN4V_RPRT_ADDR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ADDR) | |
1273 | #define ERR_SUN4V_RPRT_SZ (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_SZ) | |
1274 | #define ERR_SUN4V_RPRT_G_CPUID (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_CPUID) | |
1275 | #define ERR_SUN4V_RPRT_G_SECS (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_SECS) | |
1276 | #define ERR_SUN4V_RPRT_ASI (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ASI) | |
1277 | #define ERR_SUN4V_RPRT_REG (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_REG) | |
1278 | #define ERR_SUN4V_PCIE_SYSINO (ERR_SUN4V_PCIE_ERPT + PCIERPT_SYSINO) | |
1279 | #define ERR_SUN4V_PCIE_EHDL (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_EHDL) | |
1280 | #define ERR_SUN4V_PCIE_STICK (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_STICK) | |
1281 | #define ERR_SUN4V_PCIE_DESC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_DESC) | |
1282 | #define ERR_SUN4V_PCIE_SPECIFIC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_SPECFIC) | |
1283 | #define ERR_SUN4V_PCIE_WORD4 (ERR_SUN4V_PCIE_ERPT + PCIERPT_WORD4) | |
1284 | #define ERR_SUN4V_PCIE_HDR1 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR1) | |
1285 | #define ERR_SUN4V_PCIE_HDR2 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR2) | |
1286 | ! struct/union ERR_DIAG_RPRT_SIZE size 0xaf0 | |
1287 | u 0x0 0x8 ERR_DIAG_RPRT_ERROR_TYPE | |
1288 | u 0x8 0x8 ERR_DIAG_RPRT_REPORT_TYPE | |
1289 | u 0x10 0x8 ERR_DIAG_RPRT_TOD | |
1290 | u 0x18 0x8 ERR_DIAG_RPRT_EHDL | |
1291 | u 0x20 0x8 ERR_DIAG_RPRT_ERR_STICK | |
1292 | u 0x28 0x8 ERR_DIAG_RPRT_CPUVER | |
1293 | u 0x30 0x8 ERR_DIAG_RPRT_SERIAL | |
1294 | u 0x38 0x8 ERR_DIAG_RPRT_TSTATE | |
1295 | u 0x40 0x8 ERR_DIAG_RPRT_HTSTATE | |
1296 | u 0x48 0x8 ERR_DIAG_RPRT_TPC | |
1297 | u 0x50 0x2 ERR_DIAG_RPRT_CPUID | |
1298 | u 0x52 0x2 ERR_DIAG_RPRT_TT | |
1299 | uc 0x54 0x1 ERR_DIAG_RPRT_TL | |
1300 | ! union ERR_DIAG_RPRT_ERR_DIAG @ 0x58 has size 0xa98 | |
1301 | #define ERR_DIAG_RPRT_IN_USE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_IN_USE) | |
1302 | #define ERR_DIAG_ABORT_DATA ERR_DIAG_RPRT_ERR_DIAG | |
1303 | #define ERR_DIAG_DATA_OFFSET (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_DIAG_DATA) | |
1304 | #define ERR_DIAG_RPRT_REPORT_SIZE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_SIZE) | |
1305 | ! struct/union NIU_COOKIE_SIZE size 0x10 | |
1306 | p 0x0 0x8 NIU_LDG2LDN_TABLE | |
1307 | p 0x8 0x8 NIU_VEC2LDG_TABLE | |
1308 | /* ECC_SYNDROME_TABLE_ENTRY_SIZE 0x1 */ | |
1309 | /* ECC_MASK_TABLE_ENTRY_SIZE 0x4 */ | |
1310 | ! struct/union FPGA_UART_COOKIE_SIZE size 0x20 | |
1311 | u 0x0 0x8 FPGA_UART_COOKIE_STATUS | |
1312 | u 0x8 0x8 FPGA_UART_COOKIE_ENABLE | |
1313 | u 0x10 0x8 FPGA_UART_COOKIE_DISABLE | |
1314 | uc 0x18 0x1 FPGA_UART_COOKIE_VALID | |
1315 | uc 0x19 0x1 FPGA_UART_COOKIE_STATE | |
1316 | uc 0x1a 0x1 FPGA_UART_COOKIE_TARGET | |
1317 | ||
1318 | #define ENUM_HVctl_res_guest 0x0 | |
1319 | #define ENUM_HVctl_res_vcpu 0x1 | |
1320 | #define ENUM_HVctl_res_memory 0x2 | |
1321 | #define ENUM_HVctl_res_mau 0x3 | |
1322 | #define ENUM_HVctl_res_cwq 0x4 | |
1323 | #define ENUM_HVctl_res_ldc 0x5 | |
1324 | #define ENUM_HVctl_res_console 0x6 | |
1325 | #define ENUM_HVctl_res_hv_ldc 0x7 | |
1326 | #define ENUM_HVctl_res_pcie_bus 0x8 | |
1327 | #define ENUM_HVctl_res_guestmd 0x9 | |
1328 | #define ENUM_HVctl_res_network_device 0xa | |
1329 | ||
1330 | #define ENUM_HVctl_info_guest_state 0x0 | |
1331 | #define ENUM_HVctl_info_guest_soft_state 0x1 | |
1332 | #define ENUM_HVctl_info_guest_tod 0x2 | |
1333 | #define ENUM_HVctl_info_guest_utilisation 0x3 | |
1334 | #define ENUM_HVctl_info_guest_max 0x4 | |
1335 | p 0x0 0x8 MCONFIG_MAUS | |
1336 | p 0x8 0x8 MCONFIG_CWQS | |
1337 | p 0x10 0x8 MCONFIG_RNG | |
1338 | #define CONFIG_MAUS (CONFIG_MCONFIG + MCONFIG_MAUS) | |
1339 | #define CONFIG_CWQS (CONFIG_MCONFIG + MCONFIG_CWQS) | |
1340 | #define CONFIG_RNG (CONFIG_MCONFIG + MCONFIG_RNG) | |
1341 | p 0x0 0x8 MGUEST_NIU_STATEP | |
1342 | #define GUEST_NIU_STATEP (GUEST_MGUEST + MGUEST_NIU_STATEP) | |
1343 | ! struct/union NIUMAPREG_SIZE size 0x40 | |
1344 | u 0x0 0x4 NIUMAPREG_STATE | |
1345 | u 0x4 0x4 NIUMAPREG_VALID | |
1346 | u 0x8 0x8 NIUMAPREG_VCPUP | |
1347 | ! struct/union NIUSTATE_SIZE size 0x1000 | |
1348 | ! array NIUSTATE_MAPREG @ 0x0 size 0x8000 : element size 0x40 | |
1349 | ! struct NIUSTATE_MAPREG @ 0x0 has size 0x1000 |