[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / src / errors_l1_cache.s

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: errors_l1_cache.s
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#pragma ident	"@(#)errors_l1_cache.s	1.2	07/07/17 SMI"

#include <sys/asm_linkage.h>
#include <hypervisor.h>
#include <asi.h>
#include <mmu.h>
#include <hprivregs.h>

#include <offsets.h>
#include <util.h>
#include <error_defs.h>
#include <error_regs.h>
#include <error_asm.h>

	/*
	 * Dump I-Cache diagnostic data
	 * %g7 return address
	 */
	ENTRY(dump_icache)

	GET_ERR_DIAG_DATA_BUF(%g1, %g2)

	/*
	 * load the DESR
	 */
	GET_ERR_DESR(%g4, %g3)

	/*
	 * Icache index from DESR[10:0]
	 */
	and	%g4, DESR_ADDRESS_MASK, %g4
	/*
	 * just want the I-Cache index [5:0]
	 */
	and	%g4, ASI_ICACHE_INDEX_MASK, %g4
	sllx	%g4, ASI_ICACHE_INSTR_INDEX_SHIFT, %g4

	/*
	 * get diag_buf->icache
	 */
	add	%g1, ERR_DIAG_BUF_DIAG_DATA, %g1
	add	%g1, ERR_DIAG_DATA_ICACHE, %g1

	/*
	 * Dump the icache tag and data information for all ways
	 * DESR[5:0] D-Cache Index
	 */
	mov	(MAX_ICACHE_WAYS - 1) * ERR_ICACHE_WAY_SIZE, %g2
1:
	/*
	 * offset into DIAG_BUF
	 */
	add	%g1, %g2, %g3

	/*
	 * Create ASI_ICACHE_INSTR VA
	 */
	mov	1, %g5
	sllx	%g5, %g2, %g5
	sllx	%g5, ASI_ICACHE_INSTR_WAY_SHIFT, %g5
	or	%g4, %g5, %g5

	/*
	 * read each word and store
	 * word 0
	 */
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3	! next icache_way word
	/*
	 * The I-Cache word to be read is identified by ASI_ICACHE_INSTR
	 * bits [5:3]. To build the address we just add ASI_REGISTER_INCR
	 * to get  the first word, then add ASI_REGISTER_INCR
	 *  to get the next 7 addresses
	 */
	add	%g5, 8, %g5	! ASI_ICACHE_INSTR word 1
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3	! next icache_way word
	add	%g5, ASI_REGISTER_INCR, %g5	! ASI_ICACHE_INSTR word 2
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3	! next icache_way word
	add	%g5, ASI_REGISTER_INCR, %g5	! ASI_ICACHE_INSTR word 3
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3	! next icache_way word
	add	%g5, ASI_REGISTER_INCR, %g5	! ASI_ICACHE_INSTR word 4
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3	! next icache_way word
	add	%g5, ASI_REGISTER_INCR, %g5	! ASI_ICACHE_INSTR word 5
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3	! next icache_way word
	add	%g5, ASI_REGISTER_INCR, %g5	! ASI_ICACHE_INSTR word 6
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3	! next icache_way word
	add	%g5, ASI_REGISTER_INCR, %g5	! ASI_ICACHE_INSTR word 7
	ldxa	[%g5]ASI_ICACHE_INSTR, %g6
	stx	%g6, [%g3]

	/*	
	 * now get the ASI_ICACHE_TAG data
	 */
	add	%g3, ERR_ICACHE_WAY_INSTR_INCR, %g3
	mov	1, %g5
	sllx	%g5, %g2, %g5
	sllx	%g5, ASI_ICACHE_TAG_WAY_SHIFT, %g5
	or	%g4, %g5, %g5
	ldxa	[%g5]ASI_ICACHE_TAG, %g6
	stx	%g6, [%g3]

	/*
	 * next way
	 */
	brgz,pt	%g2, 1b
	sub	%g2, ERR_ICACHE_WAY_SIZE, %g2

	HVRET

	SET_SIZE(dump_icache)

	/*
	 * Dump DCache diagnostic data
	 *
	 * %g7 return address
	 */

	ENTRY(dump_dcache)

	GET_ERR_DIAG_DATA_BUF(%g1, %g2)

	/*
	 * load the DESR
	 */
	GET_ERR_DESR(%g4, %g3)

	/*
	 * D-Cache index from DESR[10:0]
	 */
	and	%g4, DESR_ADDRESS_MASK, %g4
	/*
	 * just want the D-Cache index [6:0]
	 */
	and	%g4, ASI_DCACHE_INDEX_MASK, %g4
	sllx	%g4, ASI_DCACHE_DATA_INDEX_SHIFT, %g4

	/*
	 * get diag_buf->dcache
	 */
	add	%g1, ERR_DIAG_BUF_DIAG_DATA, %g1
	add	%g1, ERR_DIAG_DATA_DCACHE, %g1

	/*
	 * Dump the D-Cache tag and data information for all ways
	 */
	mov	(MAX_DCACHE_WAYS - 1) * ERR_DCACHE_WAY_SIZE, %g2
1:
	/*
	 * offset into DIAG_BUF
	 */
	add	%g1, %g2, %g3

	/*
	 * Create ASI_DCACHE_DATA VA
	 */
	mov	1, %g5
	sllx	%g5, %g2, %g5
	sllx	%g5, ASI_DCACHE_DATA_WAY_SHIFT, %g5
	or	%g4, %g5, %g5

	/*
	 * read each word and store
	 * word 0
	 */
	ldxa	[%g5]ASI_DCACHE_DATA, %g6
	stx	%g6, [%g3]

	add	%g3, 8, %g3	! next dcache_way word
	/*
	 * The D-Cache word to be read is identiied by ASI_DCACHE_DATA
	 * bit [3]. To build the address we just add 8 to get the
	 * first word.
	 */
	add	%g5, 8, %g5	! ASI_DCACHE_DATA word 1
	ldxa	[%g5]ASI_DCACHE_DATA, %g6
	stx	%g6, [%g3]

	/*	
	 * now get the ASI_DCACHE_TAG data
	 */
	add	%g3, 8, %g3
	mov	1, %g5
	sllx	%g5, %g2, %g5
	sllx	%g5, ASI_DCACHE_TAG_WAY_SHIFT, %g5
	or	%g4, %g5, %g5
	ldxa	[%g5]ASI_DCACHE_TAG, %g6
	stx	%g6, [%g3]

	/*
	 * next way
	 */
	brgz,a,pt	%g2, 1b
	sub	%g2, ERR_DCACHE_WAY_SIZE, %g2

	HVRET

	SET_SIZE(dump_dcache)

	ENTRY(icache_storm)

	! first verify that storm prevention is enabled
	CHECK_BLACKOUT_INTERVAL(%g4)

	/*
	 * save our return address
	 */
	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)

	/*
	 * Disable I-cache errors
	 */
	setx	CORE_ICACHE_ERRORS_ENABLE , %g4, %g1
	mov	CORE_ERR_REPORT_EN, %g4
	ldxa	[%g4]ASI_ERR_EN, %g6
	andn	%g6, %g1, %g6
	stxa	%g6, [%g4]ASI_ERR_EN

	/*
	 * Set up a cyclic on this strand to re-enable the CERER bits
	 * after an interval of (default) 6 seconds. Set a flag in the
	 * strand struct to indicate that the cyclic has been set
	 * for these errors.
	 */
	mov	STRAND_ERR_FLAG_ICACHE, %g4	! I-Cache flag
	STRAND_STRUCT(%g6)
	lduw	[%g6 + STRAND_ERR_FLAG], %g3	! installed flags
	btst	%g4, %g3			! handler installed?
	bnz,pn	%xcc, 9f			!   yes

	or	%g3, %g4, %g3			!   no: set it
	STRAND2CONFIG_STRUCT(%g6, %g4)
	ldx	[%g4 + CONFIG_CE_BLACKOUT], %g1
	brz,pn	%g1, 9f				! zero: blackout disabled
	nop
	SET_STRAND_ERR_FLAG(%g6, %g3, %g5)
	mov	STRAND_ERR_FLAG_ICACHE, %g4	! g4 = arg 1, flags to clear
	setx	CORE_ICACHE_ERRORS_ENABLE, %g5, %g3	! g3 = arg 0 : bit(s) to set
	setx	cerer_set_error_bits, %g5, %g2
	RELOC_OFFSET(%g5, %g6)
	sub	%g2, %g6, %g2			! g2 = handler address
				        	! g1 = delta tick
	VCPU_STRUCT(%g6)
						! g6 - CPU struct
	HVCALL(cyclic_add_rel)	/* ( del_tick, address, arg0, arg1 ) */
9:
	GET_ERR_RETURN_ADDR(%g7, %g2)
	HVRET
	SET_SIZE(icache_storm)

	ENTRY(dcache_storm)

	! first verify that storm prevention is enabled
	CHECK_BLACKOUT_INTERVAL(%g4)

	/*
	 * save our return address
	 */
	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)

	/*
	 * Disable D-Cache errors
	 */
	setx	CORE_DCACHE_ERRORS_ENABLE, %g4, %g1
	mov	CORE_ERR_REPORT_EN, %g4
	ldxa	[%g4]ASI_ERR_EN, %g6
	andn	%g6, %g1, %g6
	stxa	%g6, [%g4]ASI_ERR_EN

	/*
	 * Set up a cyclic on this strand to re-enable the CERER bits
	 * after an interval of (default) 6 seconds. Set a flag in the
	 * strand struct to indicate that the cyclic has been set
	 * for these errors.
	 */
	mov	STRAND_ERR_FLAG_DCACHE, %g4	! D-Cache flag
	STRAND_STRUCT(%g6)
	lduw	[%g6 + STRAND_ERR_FLAG], %g3	! installed flags
	btst	%g4, %g3			! handler installed?
	bnz,pn	%xcc, 9f			!   yes

	or	%g3, %g4, %g3			!   no: set it
	STRAND2CONFIG_STRUCT(%g6, %g4)
	ldx	[%g4 + CONFIG_CE_BLACKOUT], %g1
	brz,pn	%g1, 9f				! zero: blackout disabled
	nop
	SET_STRAND_ERR_FLAG(%g6, %g3, %g5)
	mov	STRAND_ERR_FLAG_DCACHE, %g4	! g4 = arg 1, flags to clear
	setx	CORE_DCACHE_ERRORS_ENABLE, %g5, %g3		! g3 = arg 0 : bit(s) to set
	setx	cerer_set_error_bits, %g5, %g2
	RELOC_OFFSET(%g5, %g6)
	sub	%g2, %g6, %g2			! g2 = handler address
				        	! g1 = delta tick
	VCPU_STRUCT(%g6)
						! g6 - CPU struct
	HVCALL(cyclic_add_rel)	/* ( del_tick, address, arg0, arg1 ) */
9:
	GET_ERR_RETURN_ADDR(%g7, %g2)
	HVRET
	SET_SIZE(dcache_storm)
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: errors_l1_cache.s
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#pragma ident "@(#)errors_l1_cache.s 1.2 07/07/17 SMI"
	50
	51	#include <sys/asm_linkage.h>
	52	#include <hypervisor.h>
	53	#include <asi.h>
	54	#include <mmu.h>
	55	#include <hprivregs.h>
	56
	57	#include <offsets.h>
	58	#include <util.h>
	59	#include <error_defs.h>
	60	#include <error_regs.h>
	61	#include <error_asm.h>
	62
	63	/*
	64	* Dump I-Cache diagnostic data
65	* %g7 return address
66	*/
67	ENTRY(dump_icache)
68
69	GET_ERR_DIAG_DATA_BUF(%g1, %g2)
70
71	/*
72	* load the DESR
73	*/
74	GET_ERR_DESR(%g4, %g3)
75
76	/*
77	* Icache index from DESR[10:0]
78	*/
79	and %g4, DESR_ADDRESS_MASK, %g4
80	/*
81	* just want the I-Cache index [5:0]
82	*/
83	and %g4, ASI_ICACHE_INDEX_MASK, %g4
84	sllx %g4, ASI_ICACHE_INSTR_INDEX_SHIFT, %g4
85
86	/*
87	* get diag_buf->icache
88	*/
89	add %g1, ERR_DIAG_BUF_DIAG_DATA, %g1
90	add %g1, ERR_DIAG_DATA_ICACHE, %g1
91
92	/*
93	* Dump the icache tag and data information for all ways
94	* DESR[5:0] D-Cache Index
95	*/
96	mov (MAX_ICACHE_WAYS - 1) * ERR_ICACHE_WAY_SIZE, %g2
97	1:
98	/*
99	* offset into DIAG_BUF
100	*/
101	add %g1, %g2, %g3
102
103	/*
104	* Create ASI_ICACHE_INSTR VA
105	*/
106	mov 1, %g5
107	sllx %g5, %g2, %g5
108	sllx %g5, ASI_ICACHE_INSTR_WAY_SHIFT, %g5
109	or %g4, %g5, %g5
110
111	/*
112	* read each word and store
113	* word 0
114	*/
115	ldxa [%g5]ASI_ICACHE_INSTR, %g6
116	stx %g6, [%g3]
117
118	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3 ! next icache_way word
119	/*
120	* The I-Cache word to be read is identified by ASI_ICACHE_INSTR
121	* bits [5:3]. To build the address we just add ASI_REGISTER_INCR
122	* to get the first word, then add ASI_REGISTER_INCR
123	* to get the next 7 addresses
124	*/
125	add %g5, 8, %g5 ! ASI_ICACHE_INSTR word 1
126	ldxa [%g5]ASI_ICACHE_INSTR, %g6
127	stx %g6, [%g3]
128
129	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3 ! next icache_way word
130	add %g5, ASI_REGISTER_INCR, %g5 ! ASI_ICACHE_INSTR word 2
131	ldxa [%g5]ASI_ICACHE_INSTR, %g6
132	stx %g6, [%g3]
133
134	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3 ! next icache_way word
135	add %g5, ASI_REGISTER_INCR, %g5 ! ASI_ICACHE_INSTR word 3
136	ldxa [%g5]ASI_ICACHE_INSTR, %g6
137	stx %g6, [%g3]
138
139	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3 ! next icache_way word
140	add %g5, ASI_REGISTER_INCR, %g5 ! ASI_ICACHE_INSTR word 4
141	ldxa [%g5]ASI_ICACHE_INSTR, %g6
142	stx %g6, [%g3]
143
144	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3 ! next icache_way word
145	add %g5, ASI_REGISTER_INCR, %g5 ! ASI_ICACHE_INSTR word 5
146	ldxa [%g5]ASI_ICACHE_INSTR, %g6
147	stx %g6, [%g3]
148
149	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3 ! next icache_way word
150	add %g5, ASI_REGISTER_INCR, %g5 ! ASI_ICACHE_INSTR word 6
151	ldxa [%g5]ASI_ICACHE_INSTR, %g6
152	stx %g6, [%g3]
153
154	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3 ! next icache_way word
155	add %g5, ASI_REGISTER_INCR, %g5 ! ASI_ICACHE_INSTR word 7
156	ldxa [%g5]ASI_ICACHE_INSTR, %g6
157	stx %g6, [%g3]
158
159	/*
160	* now get the ASI_ICACHE_TAG data
161	*/
162	add %g3, ERR_ICACHE_WAY_INSTR_INCR, %g3
163	mov 1, %g5
164	sllx %g5, %g2, %g5
165	sllx %g5, ASI_ICACHE_TAG_WAY_SHIFT, %g5
166	or %g4, %g5, %g5
167	ldxa [%g5]ASI_ICACHE_TAG, %g6
168	stx %g6, [%g3]
169
170	/*
171	* next way
172	*/
173	brgz,pt %g2, 1b
174	sub %g2, ERR_ICACHE_WAY_SIZE, %g2
175
176	HVRET
177
178	SET_SIZE(dump_icache)
179
180	/*
181	* Dump DCache diagnostic data
182	*
183	* %g7 return address
184	*/
185
186	ENTRY(dump_dcache)
187
188	GET_ERR_DIAG_DATA_BUF(%g1, %g2)
189
190	/*
191	* load the DESR
192	*/
193	GET_ERR_DESR(%g4, %g3)
194
195	/*
196	* D-Cache index from DESR[10:0]
197	*/
198	and %g4, DESR_ADDRESS_MASK, %g4
199	/*
200	* just want the D-Cache index [6:0]
201	*/
202	and %g4, ASI_DCACHE_INDEX_MASK, %g4
203	sllx %g4, ASI_DCACHE_DATA_INDEX_SHIFT, %g4
204
205	/*
206	* get diag_buf->dcache
207	*/
208	add %g1, ERR_DIAG_BUF_DIAG_DATA, %g1
209	add %g1, ERR_DIAG_DATA_DCACHE, %g1
210
211	/*
212	* Dump the D-Cache tag and data information for all ways
213	*/
214	mov (MAX_DCACHE_WAYS - 1) * ERR_DCACHE_WAY_SIZE, %g2
215	1:
216	/*
217	* offset into DIAG_BUF
218	*/
219	add %g1, %g2, %g3
220
221	/*
222	* Create ASI_DCACHE_DATA VA
223	*/
224	mov 1, %g5
225	sllx %g5, %g2, %g5
226	sllx %g5, ASI_DCACHE_DATA_WAY_SHIFT, %g5
227	or %g4, %g5, %g5
228
229	/*
230	* read each word and store
231	* word 0
232	*/
233	ldxa [%g5]ASI_DCACHE_DATA, %g6
234	stx %g6, [%g3]
235
236	add %g3, 8, %g3 ! next dcache_way word
237	/*
238	* The D-Cache word to be read is identiied by ASI_DCACHE_DATA
239	* bit [3]. To build the address we just add 8 to get the
240	* first word.
241	*/
242	add %g5, 8, %g5 ! ASI_DCACHE_DATA word 1
243	ldxa [%g5]ASI_DCACHE_DATA, %g6
244	stx %g6, [%g3]
245
246	/*
247	* now get the ASI_DCACHE_TAG data
248	*/
249	add %g3, 8, %g3
250	mov 1, %g5
251	sllx %g5, %g2, %g5
252	sllx %g5, ASI_DCACHE_TAG_WAY_SHIFT, %g5
253	or %g4, %g5, %g5
254	ldxa [%g5]ASI_DCACHE_TAG, %g6
255	stx %g6, [%g3]
256
257	/*
258	* next way
259	*/
260	brgz,a,pt %g2, 1b
261	sub %g2, ERR_DCACHE_WAY_SIZE, %g2
262
263	HVRET
264
265	SET_SIZE(dump_dcache)
266
267	ENTRY(icache_storm)
268
269	! first verify that storm prevention is enabled
270	CHECK_BLACKOUT_INTERVAL(%g4)
271
272	/*
273	* save our return address
274	*/
275	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)
276
277	/*
278	* Disable I-cache errors
279	*/
280	setx CORE_ICACHE_ERRORS_ENABLE , %g4, %g1
281	mov CORE_ERR_REPORT_EN, %g4
282	ldxa [%g4]ASI_ERR_EN, %g6
283	andn %g6, %g1, %g6
284	stxa %g6, [%g4]ASI_ERR_EN
285
286	/*
287	* Set up a cyclic on this strand to re-enable the CERER bits
288	* after an interval of (default) 6 seconds. Set a flag in the
289	* strand struct to indicate that the cyclic has been set
290	* for these errors.
291	*/
292	mov STRAND_ERR_FLAG_ICACHE, %g4 ! I-Cache flag
293	STRAND_STRUCT(%g6)
294	lduw [%g6 + STRAND_ERR_FLAG], %g3 ! installed flags
295	btst %g4, %g3 ! handler installed?
296	bnz,pn %xcc, 9f ! yes
297
298	or %g3, %g4, %g3 ! no: set it
299	STRAND2CONFIG_STRUCT(%g6, %g4)
300	ldx [%g4 + CONFIG_CE_BLACKOUT], %g1
301	brz,pn %g1, 9f ! zero: blackout disabled
302	nop
303	SET_STRAND_ERR_FLAG(%g6, %g3, %g5)
304	mov STRAND_ERR_FLAG_ICACHE, %g4 ! g4 = arg 1, flags to clear
305	setx CORE_ICACHE_ERRORS_ENABLE, %g5, %g3 ! g3 = arg 0 : bit(s) to set
306	setx cerer_set_error_bits, %g5, %g2
307	RELOC_OFFSET(%g5, %g6)
308	sub %g2, %g6, %g2 ! g2 = handler address
309	! g1 = delta tick
310	VCPU_STRUCT(%g6)
311	! g6 - CPU struct
312	HVCALL(cyclic_add_rel) /* ( del_tick, address, arg0, arg1 ) */
313	9:
314	GET_ERR_RETURN_ADDR(%g7, %g2)
315	HVRET
316	SET_SIZE(icache_storm)
317
318	ENTRY(dcache_storm)
319
320	! first verify that storm prevention is enabled
321	CHECK_BLACKOUT_INTERVAL(%g4)
322
323	/*
324	* save our return address
325	*/
326	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)
327
328	/*
329	* Disable D-Cache errors
330	*/
331	setx CORE_DCACHE_ERRORS_ENABLE, %g4, %g1
332	mov CORE_ERR_REPORT_EN, %g4
333	ldxa [%g4]ASI_ERR_EN, %g6
334	andn %g6, %g1, %g6
335	stxa %g6, [%g4]ASI_ERR_EN
336
337	/*
338	* Set up a cyclic on this strand to re-enable the CERER bits
339	* after an interval of (default) 6 seconds. Set a flag in the
340	* strand struct to indicate that the cyclic has been set
341	* for these errors.
342	*/
343	mov STRAND_ERR_FLAG_DCACHE, %g4 ! D-Cache flag
344	STRAND_STRUCT(%g6)
345	lduw [%g6 + STRAND_ERR_FLAG], %g3 ! installed flags
346	btst %g4, %g3 ! handler installed?
347	bnz,pn %xcc, 9f ! yes
348
349	or %g3, %g4, %g3 ! no: set it
350	STRAND2CONFIG_STRUCT(%g6, %g4)
351	ldx [%g4 + CONFIG_CE_BLACKOUT], %g1
352	brz,pn %g1, 9f ! zero: blackout disabled
353	nop
354	SET_STRAND_ERR_FLAG(%g6, %g3, %g5)
355	mov STRAND_ERR_FLAG_DCACHE, %g4 ! g4 = arg 1, flags to clear
356	setx CORE_DCACHE_ERRORS_ENABLE, %g5, %g3 ! g3 = arg 0 : bit(s) to set
357	setx cerer_set_error_bits, %g5, %g2
358	RELOC_OFFSET(%g5, %g6)
359	sub %g2, %g6, %g2 ! g2 = handler address
360	! g1 = delta tick
361	VCPU_STRUCT(%g6)
362	! g6 - CPU struct
363	HVCALL(cyclic_add_rel) /* ( del_tick, address, arg0, arg1 ) */
364	9:
365	GET_ERR_RETURN_ADDR(%g7, %g2)
366	HVRET
367	SET_SIZE(dcache_storm)