[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / src / errors_soc.s

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: errors_soc.s
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#pragma ident	"@(#)errors_soc.s	1.6	07/08/17 SMI"

#include <sys/asm_linkage.h>
#include <sun4v/asi.h>
#include <sun4v/queue.h>
#include <hypervisor.h>
#include <asi.h>
#include <mmu.h>
#include <hprivregs.h>
#include <intr.h>

#include <offsets.h>
#include <util.h>
#include <error_defs.h>
#include <error_regs.h>
#include <error_soc.h>
#include <error_asm.h>
#include <niu.h>
#include <piu.h>

	/*
	 * SOC FBR Correctable Errrors require the DRAM ESRs to be included
	 * in the SER.
	 */
	ENTRY(dump_soc_fbr)

	GET_ERR_DIAG_DATA_BUF(%g1, %g2)
	! DIAG_BUF in %g1

	/*
	 * Store L2 ESR for the bank in error into the DIAG_BUF
	 */
	set	(NO_L2_BANKS - 1), %g3
.dump_soc_l2_banks:
	! skip banks which are disabled.  causes hang.
	SKIP_DISABLED_L2_BANK(%g3, %g4, %g5, .dump_soc_no_l2_error)

	setx	L2_ERROR_STATUS_REG, %g4, %g5
	sllx	%g3, L2_BANK_SHIFT, %g2
	or	%g5, %g2, %g2
	ldx	[%g2], %g4

	brz,pt	%g4, .dump_soc_no_l2_error
	nop

	stx	%g3, [%g1 + ERR_DIAG_L2_BANK]

	add	%g1, ERR_DIAG_BUF_L2_CACHE_ESR, %g2
	mulx	%g3, ERR_DIAG_BUF_L2_CACHE_ESR_INCR, %g5
	add	%g2, %g5, %g2
	! %g2	diag_buf->l2_cache.esr
	stx	%g4, [%g2]
.dump_soc_no_l2_error:
	brgz,pt	%g3, .dump_soc_l2_banks
	dec	%g3

	/*
	 * Store DRAM ESR/EAR/ND for the bank in error into the DIAG_BUF
	 */
	set	(NO_DRAM_BANKS - 1), %g3
.dump_soc_dram_banks:
	! skip banks which are disabled.  causes hang.
	SKIP_DISABLED_DRAM_BANK(%g3, %g4, %g5, .dump_soc_no_dram_error)

	! DRAM Error Status register
	setx	DRAM_ESR_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g2
	or	%g5, %g2, %g2
	ldx	[%g2], %g4
	add	%g1, ERR_DIAG_BUF_DRAM_ESR, %g2
	mulx	%g3, ERR_DIAG_BUF_DRAM_ESR_INCR, %g5
	add	%g2, %g5, %g2
	stx	%g4, [%g2]	! store DRAM ESR

	! DRAM Error Address register
	add	%g1, ERR_DIAG_BUF_DRAM_EAR, %g2
	mulx	%g3, ERR_DIAG_BUF_DRAM_EAR_INCR, %g5
	add	%g2, %g5, %g2
	setx	DRAM_EAR_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g4
	or	%g5, %g4, %g4
	ldx	[%g4], %g5
	stx	%g5, [%g2]

	! DRAM Error Location register
	add	%g1, ERR_DIAG_BUF_DRAM_LOC, %g2
	mulx	%g3, ERR_DIAG_BUF_DRAM_LOC_INCR, %g5
	add	%g2, %g5, %g2
	setx	DRAM_ELR_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g4
	or	%g5, %g4, %g4
	ldx	[%g4], %g5
	stx	%g5, [%g2]

	! DRAM Error Counter register
	add	%g1, ERR_DIAG_BUF_DRAM_CTR, %g2
	mulx	%g3, ERR_DIAG_BUF_DRAM_CTR_INCR, %g5
	add	%g2, %g5, %g2
	setx	DRAM_ECR_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g4
	or	%g5, %g4, %g4
	ldx	[%g4], %g5
	stx	%g5, [%g2]

	! DRAM FBD Syndrome register
	add	%g1, ERR_DIAG_BUF_DRAM_FBD, %g2
	mulx	%g3, ERR_DIAG_BUF_DRAM_FBD_INCR, %g5
	add	%g2, %g5, %g2
	setx	DRAM_FBD_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g4
	or	%g5, %g4, %g4
	ldx	[%g4], %g5
	stx	%g5, [%g2]

	! DRAM Error Retry register
	add	%g1, ERR_DIAG_BUF_DRAM_RETRY, %g2
	mulx	%g3, ERR_DIAG_BUF_DRAM_RETRY_INCR, %g5
	add	%g2, %g5, %g2
	setx	DRAM_RETRY_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g4
	or	%g5, %g4, %g4
	ldx	[%g4], %g5
	stx	%g5, [%g2]

.dump_soc_no_dram_error:
	! next bank
	brgz,pt	%g3, .dump_soc_dram_banks
	dec	%g3

	ba	dump_soc	! tail call
	nop

	SET_SIZE(dump_soc_fbr)

	/*
	 * Dump SOC diagnostic data
	 * %g7 return address
	 */
	ENTRY(dump_soc)

	GET_ERR_DIAG_DATA_BUF(%g1, %g2)

	/*
	 * get diag_buf->err_soc
	 */
	add	%g1, ERR_DIAG_BUF_DIAG_DATA, %g1
	add	%g1, ERR_DIAG_DATA_SOC, %g1

	! SOC Error Status Register
	setx	SOC_ERROR_STATUS_REG, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_ESR]

	! SOC Pending Error Status Register
	setx	SOC_PENDING_ERROR_STATUS_REG, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_PESR]

	! SOC SII Syndrome Status Register
	setx	SOC_SII_ERROR_SYNDROME_REG, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_SII_SYND]

	! SOC NCU Syndrome Status Register
	setx	SOC_NCU_ERROR_SYNDROME_REG, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_NCU_SYND]

	! SOC Error Log Enable Register
	setx	SOC_ERROR_LOG_ENABLE, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_ELER]

	! SOC Error Interrupt Enable Register
	setx	SOC_ERROR_TRAP_ENABLE, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_EIER]

#ifndef DEBUG_LEGION
	! SOC Error Steering Register
	setx	SOC_ERRORSTEER_REG, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_VCID]
#else
	stx	%g0, [%g1 + ERR_SOC_VCID]
#endif

	! SOC Fatal Error Enable Register
	setx	SOC_FATAL_ERROR_ENABLE, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_FEER]

	! SOC Error Injection Register
	setx	SOC_ERROR_INJECTION_REG, %g5, %g6
	ldx	[%g6], %g6
	stx	%g6, [%g1 + ERR_SOC_EIR]

	HVRET

	SET_SIZE(dump_soc)

	/*
	 * Clear ESRs after SOC error
	 * args
	 * %g7	return address
	 */
	ENTRY(clear_soc)

	ALTENTRY(clear_soc_after_storm)

	! SOC Error Status Register
	setx	SOC_ERROR_STATUS_REG, %g5, %g6
	ldx	[%g6], %g4			! save for later
	stx	%g0, [%g6]

	! SOC Pending Error Status Register
	setx	SOC_PENDING_ERROR_STATUS_REG, %g5, %g6
	stx	%g0, [%g6]

	! SOC SII Syndrome Status Register
	setx	SOC_SII_ERROR_SYNDROME_REG, %g5, %g6
	stx	%g0, [%g6]

	! SOC NCU Syndrome Status Register
	setx	SOC_NCU_ERROR_SYNDROME_REG, %g5, %g6
	stx	%g0, [%g6]

	! if we got an MCU/FBD error, clear the MCU/FBD registers now

	setx	SOC_MCU0FBR|SOC_MCU0ECC, %g5, %g6
	btst	%g4, %g6
	bnz	1f
	mov	0, %g3
	setx	SOC_MCU1FBR|SOC_MCU1ECC, %g5, %g6
	btst	%g4, %g6
	bnz	1f
	mov	1, %g3
	setx	SOC_MCU2FBR|SOC_MCU2ECC, %g5, %g6
	btst	%g4, %g6
	bnz	1f
	mov	2, %g3
	setx	SOC_MCU3FBR|SOC_MCU3ECC, %g5, %g6
	btst	%g4, %g6
	bnz	1f
	mov	3, %g3
	ba	2f		! no MCU/FBD error
	nop
1:
	! %g3	which MCU

	! skip banks which are disabled.  causes hang.
	SKIP_DISABLED_DRAM_BANK(%g3, %g4, %g5, 2f)

	setx	DRAM_ESR_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g2
	or	%g5, %g2, %g2
	ldx	[%g2], %g4
	stx	%g4, [%g2]	! clear DRAM ESR 	RW1C
	stx	%g0, [%g2]	! clear DRAM ESR 	RW

	setx	DRAM_FBD_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g4
	or	%g5, %g4, %g4
	stx	%g0, [%g4]	! clear DRAM FBD SYND	RW
2:

	HVRET

	SET_SIZE(clear_soc)
	SET_SIZE(clear_soc_after_storm)

	ENTRY(soc_storm)

	! first verify that storm prevention is enabled
	CHECK_BLACKOUT_INTERVAL(%g4)

	/*
	 * save our return address
	 */
	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)

	setx	SOC_ERROR_TRAP_ENABLE, %g4, %g3
	ldx	[%g3], %g4
	setx	SOC_CORRECTABLE_ERRORS, %g5, %g6
	btst	%g6, %g4
	bz,pn	%xcc, 9f		! SOC CEs already disabled
	andn	%g4, %g6, %g4
	stx	%g4, [%g3]
	setx	SOC_ERROR_LOG_ENABLE, %g4, %g3
	ldx	[%g3], %g4
	andn	%g4, %g6, %g4
	stx	%g4, [%g3]

	/*
	 * Set up a cyclic on this strand to re-enable the SOC CE bits
	 * after an interval of 6 seconds. Set a flag in the
	 * strand struct to indicate that the cyclic has been set
	 * for this bank.
	 */
	mov	STRAND_ERR_FLAG_SOC, %g4
	STRAND_STRUCT(%g6)
	lduw	[%g6 + STRAND_ERR_FLAG], %g2	! installed flags
	btst	%g4, %g2			! handler installed?
	bnz,pn	%xcc, 9f			!   yes

	STRAND2CONFIG_STRUCT(%g6, %g4)
	ldx	[%g4 + CONFIG_CE_BLACKOUT], %g1
	brz,a,pn %g1, 9f			! zero: blackout disabled
	  nop
	SET_STRAND_ERR_FLAG(%g6, STRAND_ERR_FLAG_SOC, %g5)
	setx	soc_set_error_bits, %g5, %g2
	RELOC_OFFSET(%g4, %g5)
	sub	%g2, %g5, %g2			! g2 = handler address
	setx	SOC_CORRECTABLE_ERRORS, %g4, %g3	! g3 = arg 0 : bit(s) to set
	mov	STRAND_ERR_FLAG_SOC, %g4		! g4 = arg 1 : cpu flags to clear
				        	! g1 = delta tick
	VCPU_STRUCT(%g6)
						! g6 - CPU struct
	HVCALL(cyclic_add_rel)	/* ( del_tick, address, arg0, arg1 ) */
9:
	GET_ERR_RETURN_ADDR(%g7, %g2)
	HVRET
	SET_SIZE(soc_storm)

	/*
	 * cyclic function used to re-enable SOC_TRAP_ENABLE bits
	 *
	 * %g1		SOC_TRAP_ENABLE bits to set
	 * %g2		CPU->err_flags to clear
	 * %g7		return address
	 * %g5 - %g6	clobbered
	 */
	ENTRY(soc_set_error_bits)
	STRAND_STRUCT(%g6)
	CLEAR_STRAND_ERR_FLAG(%g6, %g2, %g5)

	setx	SOC_ERROR_TRAP_ENABLE, %g4, %g5
	ldx	[%g5], %g4
	or	%g4, %g1, %g4
	stx	%g4, [%g5]
	setx	SOC_ERROR_LOG_ENABLE, %g4, %g5
	ldx	[%g5], %g4
	or	%g4, %g1, %g4
	stx	%g4, [%g5]

	/*
	 * We need to clear the SOC ESRs in case they were
	 * set while the error traps were disabled
	 */
	ba,a	clear_soc_after_storm		! tail call
	! NOTREACHED
	SET_SIZE(soc_set_error_bits)

	ENTRY(soc_sun4v_report)
	GET_ERR_SUN4V_RPRT_BUF(%g2, %g3)
	brz,pn	%g2, soc_sun4v_report_exit
	.empty

	! workaround for SOC ESRs always reading as 0
	ba	1f
	nop

	setx	SOC_NCU_ERROR_SYNDROME_REG, %g3, %g4
	ldx	[%g4], %g4
	! has a valid syndrome been logged ?
	setx	SOC_NCU_ESR_V, %g3, %g5
	btst	%g5, %g4
	bz,pn	%xcc, soc_sun4v_report_exit
	.empty
	! has a valid strandid been logged ?
	setx	SOC_NCU_ESR_S, %g3, %g5
	btst	%g5, %g4
	bz,pn	%xcc, soc_sun4v_report_exit
	.empty
	! has a valid PA been logged ?
	setx	SOC_NCU_ESR_P, %g3, %g5
	btst	%g5, %g4
	bz,pn	%xcc, soc_sun4v_report_exit
	.empty

1:
	srlx	%g4, SOC_NCU_ESR_STRANDID_SHIFT, %g5
	and	%g5, SOC_NCU_ESR_STRANDID_MASK, %g5
	stuh	%g5, [%g2 + ERR_SUN4V_RPRT_G_CPUID]
	setx	SOC_NCU_ESR_PA_MASK, %g3, %g5
	and	%g4, %g5, %g5
	VCPU_STRUCT(%g6)
	CPU_ERR_IO_PA_TO_RA(%g6, %g5, %g5)
	GUEST_STRUCT(%g6)
	mov	1, %g3
	! %g6	guestp
	! %g5	raddr		(need PA -> RA)
	! %g3	size
	RANGE_CHECK_IO(%g6, %g5, %g3, soc_pa_good, soc_pa_bad, %g4, %g1)
soc_pa_bad:
	mov	CPU_ERR_INVALID_RA, %g5
soc_pa_good:
	stx	%g5, [%g2 + ERR_SUN4V_RPRT_ADDR]
	/*
	 * SZ is 8 bytes for a single ASI VA
	 */
	mov	8, %g5
	st	%g5, [%g2 + ERR_SUN4V_RPRT_SZ]

soc_sun4v_report_exit:
	HVRET
	SET_SIZE(soc_sun4v_report)


	ENTRY(print_soc)
#ifdef DEBUG_LEGION
	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)
	GET_ERR_DIAG_DATA_BUF(%g1, %g2)

	/*
	 * print the D-SFSR/D-SFAR
	 */
	mov	%g1, %g6
	PRINT_NOTRAP("SOCU error: D-SFSR : ");
	ldx	[%g6 + ERR_DIAG_BUF_SPARC_DSFSR], %g3
	PRINTX_NOTRAP(%g3)
	PRINT_NOTRAP("\r\nSOCU error: D-SFAR : ");
	ldx	[%g6 + ERR_DIAG_BUF_SPARC_DSFAR], %g3
	PRINTX_NOTRAP(%g3)
	PRINT_NOTRAP("\r\nSOCU error: DESR: ");
	GET_ERR_DESR(%g3, %g4)
	PRINTX_NOTRAP(%g3)

	/*
	 * get diag_buf->err_soc
	 */
	add	%g6, ERR_DIAG_BUF_DIAG_DATA, %g6
	add	%g6, ERR_DIAG_DATA_SOC, %g6
	! SOC Error Status Register
	PRINT_NOTRAP("\r\nSOCU error: SOC ESR: ");
	ldx	[%g6 + ERR_SOC_ESR], %g3
	PRINTX_NOTRAP(%g3)

	! SOC Pending Error Status Register
	PRINT_NOTRAP("\r\nSOCU error: SOC PENDING ESR: ");
	ldx	[%g6 + ERR_SOC_PESR], %g3
	PRINTX_NOTRAP(%g3)

	! SOC SII Syndrome Status Register
	PRINT_NOTRAP("\r\nSOCU error: SOC SII ESR: ");
	ldx	[%g6 + ERR_SOC_SII_SYND], %g3
	PRINTX_NOTRAP(%g3)

	! SOC NCU Syndrome Status Register
	PRINT_NOTRAP("\r\nSOCU error: SOC NCU SYND : ");
	ldx	[%g6 + ERR_SOC_NCU_SYND], %g3
	PRINTX_NOTRAP(%g3)
	PRINT_NOTRAP("\r\n");

	GET_ERR_RETURN_ADDR(%g7, %g2)
#endif
	HVRET
	SET_SIZE(print_soc)

	/*
	 * Set the DRAM FBR Error Count registers
	 */
	ENTRY(reset_fbr_counters)
	set	(NO_DRAM_BANKS - 1), %g3
1:
	! skip banks which are disabled.  causes hang.
	SKIP_DISABLED_DRAM_BANK(%g3, %g4, %g5, 2f)

	setx	DRAM_FBR_COUNT_BASE, %g4, %g5
	sllx	%g3, DRAM_BANK_SHIFT, %g4
	add	%g5, %g4, %g5
	ldx	[%g5], %g4
	brnz,pt	%g4, 2f
	mov	DRAM_ERROR_COUNTER_FBR_RATIO, %g4
	stx	%g4, [%g5]
2:
	! next bank
	brgz,pt	%g3, 1b
	dec	%g3

	HVRET
	SET_SIZE(reset_fbr_counters)

	/*
	 * Clean up after FBR errors
	 * DSU errata (N2 erratum 190) means we must check whether
	 * the FBR has caused a bogus DSU error to be logged.
	 */
	ENTRY(reset_soc_fbr)
	STRAND_PUSH(%g7, %g3, %g4)

	GET_ERR_TABLE_ENTRY(%g3, %g4)
	ld	[%g3 + ERR_FLAGS], %g4
	set	ERR_CLEAR_SOC, %g3
	btst	%g4, %g3
	bz,pn	%xcc, 1f
	nop

	HVCALL(clear_soc)
1:
	HVCALL(reset_fbr_counters)
	HVCALL(verify_dsu_error)
	HVCALL(clear_dram_l2c_esr_regs)
	STRAND_POP(%g7, %g3)
	HVRET
	SET_SIZE(reset_soc_fbr)
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: errors_soc.s
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#pragma ident "@(#)errors_soc.s 1.6 07/08/17 SMI"
	50
	51	#include <sys/asm_linkage.h>
	52	#include <sun4v/asi.h>
	53	#include <sun4v/queue.h>
	54	#include <hypervisor.h>
	55	#include <asi.h>
	56	#include <mmu.h>
	57	#include <hprivregs.h>
	58	#include <intr.h>
	59
	60	#include <offsets.h>
	61	#include <util.h>
	62	#include <error_defs.h>
	63	#include <error_regs.h>
	64	#include <error_soc.h>
65	#include <error_asm.h>
66	#include <niu.h>
67	#include <piu.h>
68
69	/*
70	* SOC FBR Correctable Errrors require the DRAM ESRs to be included
71	* in the SER.
72	*/
73	ENTRY(dump_soc_fbr)
74
75	GET_ERR_DIAG_DATA_BUF(%g1, %g2)
76	! DIAG_BUF in %g1
77
78	/*
79	* Store L2 ESR for the bank in error into the DIAG_BUF
80	*/
81	set (NO_L2_BANKS - 1), %g3
82	.dump_soc_l2_banks:
83	! skip banks which are disabled. causes hang.
84	SKIP_DISABLED_L2_BANK(%g3, %g4, %g5, .dump_soc_no_l2_error)
85
86	setx L2_ERROR_STATUS_REG, %g4, %g5
87	sllx %g3, L2_BANK_SHIFT, %g2
88	or %g5, %g2, %g2
89	ldx [%g2], %g4
90
91	brz,pt %g4, .dump_soc_no_l2_error
92	nop
93
94	stx %g3, [%g1 + ERR_DIAG_L2_BANK]
95
96	add %g1, ERR_DIAG_BUF_L2_CACHE_ESR, %g2
97	mulx %g3, ERR_DIAG_BUF_L2_CACHE_ESR_INCR, %g5
98	add %g2, %g5, %g2
99	! %g2 diag_buf->l2_cache.esr
100	stx %g4, [%g2]
101	.dump_soc_no_l2_error:
102	brgz,pt %g3, .dump_soc_l2_banks
103	dec %g3
104
105	/*
106	* Store DRAM ESR/EAR/ND for the bank in error into the DIAG_BUF
107	*/
108	set (NO_DRAM_BANKS - 1), %g3
109	.dump_soc_dram_banks:
110	! skip banks which are disabled. causes hang.
111	SKIP_DISABLED_DRAM_BANK(%g3, %g4, %g5, .dump_soc_no_dram_error)
112
113	! DRAM Error Status register
114	setx DRAM_ESR_BASE, %g4, %g5
115	sllx %g3, DRAM_BANK_SHIFT, %g2
116	or %g5, %g2, %g2
117	ldx [%g2], %g4
118	add %g1, ERR_DIAG_BUF_DRAM_ESR, %g2
119	mulx %g3, ERR_DIAG_BUF_DRAM_ESR_INCR, %g5
120	add %g2, %g5, %g2
121	stx %g4, [%g2] ! store DRAM ESR
122
123	! DRAM Error Address register
124	add %g1, ERR_DIAG_BUF_DRAM_EAR, %g2
125	mulx %g3, ERR_DIAG_BUF_DRAM_EAR_INCR, %g5
126	add %g2, %g5, %g2
127	setx DRAM_EAR_BASE, %g4, %g5
128	sllx %g3, DRAM_BANK_SHIFT, %g4
129	or %g5, %g4, %g4
130	ldx [%g4], %g5
131	stx %g5, [%g2]
132
133	! DRAM Error Location register
134	add %g1, ERR_DIAG_BUF_DRAM_LOC, %g2
135	mulx %g3, ERR_DIAG_BUF_DRAM_LOC_INCR, %g5
136	add %g2, %g5, %g2
137	setx DRAM_ELR_BASE, %g4, %g5
138	sllx %g3, DRAM_BANK_SHIFT, %g4
139	or %g5, %g4, %g4
140	ldx [%g4], %g5
141	stx %g5, [%g2]
142
143	! DRAM Error Counter register
144	add %g1, ERR_DIAG_BUF_DRAM_CTR, %g2
145	mulx %g3, ERR_DIAG_BUF_DRAM_CTR_INCR, %g5
146	add %g2, %g5, %g2
147	setx DRAM_ECR_BASE, %g4, %g5
148	sllx %g3, DRAM_BANK_SHIFT, %g4
149	or %g5, %g4, %g4
150	ldx [%g4], %g5
151	stx %g5, [%g2]
152
153	! DRAM FBD Syndrome register
154	add %g1, ERR_DIAG_BUF_DRAM_FBD, %g2
155	mulx %g3, ERR_DIAG_BUF_DRAM_FBD_INCR, %g5
156	add %g2, %g5, %g2
157	setx DRAM_FBD_BASE, %g4, %g5
158	sllx %g3, DRAM_BANK_SHIFT, %g4
159	or %g5, %g4, %g4
160	ldx [%g4], %g5
161	stx %g5, [%g2]
162
163	! DRAM Error Retry register
164	add %g1, ERR_DIAG_BUF_DRAM_RETRY, %g2
165	mulx %g3, ERR_DIAG_BUF_DRAM_RETRY_INCR, %g5
166	add %g2, %g5, %g2
167	setx DRAM_RETRY_BASE, %g4, %g5
168	sllx %g3, DRAM_BANK_SHIFT, %g4
169	or %g5, %g4, %g4
170	ldx [%g4], %g5
171	stx %g5, [%g2]
172
173	.dump_soc_no_dram_error:
174	! next bank
175	brgz,pt %g3, .dump_soc_dram_banks
176	dec %g3
177
178	ba dump_soc ! tail call
179	nop
180
181	SET_SIZE(dump_soc_fbr)
182
183	/*
184	* Dump SOC diagnostic data
185	* %g7 return address
186	*/
187	ENTRY(dump_soc)
188
189	GET_ERR_DIAG_DATA_BUF(%g1, %g2)
190
191	/*
192	* get diag_buf->err_soc
193	*/
194	add %g1, ERR_DIAG_BUF_DIAG_DATA, %g1
195	add %g1, ERR_DIAG_DATA_SOC, %g1
196
197	! SOC Error Status Register
198	setx SOC_ERROR_STATUS_REG, %g5, %g6
199	ldx [%g6], %g6
200	stx %g6, [%g1 + ERR_SOC_ESR]
201
202	! SOC Pending Error Status Register
203	setx SOC_PENDING_ERROR_STATUS_REG, %g5, %g6
204	ldx [%g6], %g6
205	stx %g6, [%g1 + ERR_SOC_PESR]
206
207	! SOC SII Syndrome Status Register
208	setx SOC_SII_ERROR_SYNDROME_REG, %g5, %g6
209	ldx [%g6], %g6
210	stx %g6, [%g1 + ERR_SOC_SII_SYND]
211
212	! SOC NCU Syndrome Status Register
213	setx SOC_NCU_ERROR_SYNDROME_REG, %g5, %g6
214	ldx [%g6], %g6
215	stx %g6, [%g1 + ERR_SOC_NCU_SYND]
216
217	! SOC Error Log Enable Register
218	setx SOC_ERROR_LOG_ENABLE, %g5, %g6
219	ldx [%g6], %g6
220	stx %g6, [%g1 + ERR_SOC_ELER]
221
222	! SOC Error Interrupt Enable Register
223	setx SOC_ERROR_TRAP_ENABLE, %g5, %g6
224	ldx [%g6], %g6
225	stx %g6, [%g1 + ERR_SOC_EIER]
226
227	#ifndef DEBUG_LEGION
228	! SOC Error Steering Register
229	setx SOC_ERRORSTEER_REG, %g5, %g6
230	ldx [%g6], %g6
231	stx %g6, [%g1 + ERR_SOC_VCID]
232	#else
233	stx %g0, [%g1 + ERR_SOC_VCID]
234	#endif
235
236	! SOC Fatal Error Enable Register
237	setx SOC_FATAL_ERROR_ENABLE, %g5, %g6
238	ldx [%g6], %g6
239	stx %g6, [%g1 + ERR_SOC_FEER]
240
241	! SOC Error Injection Register
242	setx SOC_ERROR_INJECTION_REG, %g5, %g6
243	ldx [%g6], %g6
244	stx %g6, [%g1 + ERR_SOC_EIR]
245
246	HVRET
247
248	SET_SIZE(dump_soc)
249
250	/*
251	* Clear ESRs after SOC error
252	* args
253	* %g7 return address
254	*/
255	ENTRY(clear_soc)
256
257	ALTENTRY(clear_soc_after_storm)
258
259	! SOC Error Status Register
260	setx SOC_ERROR_STATUS_REG, %g5, %g6
261	ldx [%g6], %g4 ! save for later
262	stx %g0, [%g6]
263
264	! SOC Pending Error Status Register
265	setx SOC_PENDING_ERROR_STATUS_REG, %g5, %g6
266	stx %g0, [%g6]
267
268	! SOC SII Syndrome Status Register
269	setx SOC_SII_ERROR_SYNDROME_REG, %g5, %g6
270	stx %g0, [%g6]
271
272	! SOC NCU Syndrome Status Register
273	setx SOC_NCU_ERROR_SYNDROME_REG, %g5, %g6
274	stx %g0, [%g6]
275
276	! if we got an MCU/FBD error, clear the MCU/FBD registers now
277
278	setx SOC_MCU0FBR\|SOC_MCU0ECC, %g5, %g6
279	btst %g4, %g6
280	bnz 1f
281	mov 0, %g3
282	setx SOC_MCU1FBR\|SOC_MCU1ECC, %g5, %g6
283	btst %g4, %g6
284	bnz 1f
285	mov 1, %g3
286	setx SOC_MCU2FBR\|SOC_MCU2ECC, %g5, %g6
287	btst %g4, %g6
288	bnz 1f
289	mov 2, %g3
290	setx SOC_MCU3FBR\|SOC_MCU3ECC, %g5, %g6
291	btst %g4, %g6
292	bnz 1f
293	mov 3, %g3
294	ba 2f ! no MCU/FBD error
295	nop
296	1:
297	! %g3 which MCU
298
299	! skip banks which are disabled. causes hang.
300	SKIP_DISABLED_DRAM_BANK(%g3, %g4, %g5, 2f)
301
302	setx DRAM_ESR_BASE, %g4, %g5
303	sllx %g3, DRAM_BANK_SHIFT, %g2
304	or %g5, %g2, %g2
305	ldx [%g2], %g4
306	stx %g4, [%g2] ! clear DRAM ESR RW1C
307	stx %g0, [%g2] ! clear DRAM ESR RW
308
309	setx DRAM_FBD_BASE, %g4, %g5
310	sllx %g3, DRAM_BANK_SHIFT, %g4
311	or %g5, %g4, %g4
312	stx %g0, [%g4] ! clear DRAM FBD SYND RW
313	2:
314
315	HVRET
316
317	SET_SIZE(clear_soc)
318	SET_SIZE(clear_soc_after_storm)
319
320	ENTRY(soc_storm)
321
322	! first verify that storm prevention is enabled
323	CHECK_BLACKOUT_INTERVAL(%g4)
324
325	/*
326	* save our return address
327	*/
328	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)
329
330	setx SOC_ERROR_TRAP_ENABLE, %g4, %g3
331	ldx [%g3], %g4
332	setx SOC_CORRECTABLE_ERRORS, %g5, %g6
333	btst %g6, %g4
334	bz,pn %xcc, 9f ! SOC CEs already disabled
335	andn %g4, %g6, %g4
336	stx %g4, [%g3]
337	setx SOC_ERROR_LOG_ENABLE, %g4, %g3
338	ldx [%g3], %g4
339	andn %g4, %g6, %g4
340	stx %g4, [%g3]
341
342	/*
343	* Set up a cyclic on this strand to re-enable the SOC CE bits
344	* after an interval of 6 seconds. Set a flag in the
345	* strand struct to indicate that the cyclic has been set
346	* for this bank.
347	*/
348	mov STRAND_ERR_FLAG_SOC, %g4
349	STRAND_STRUCT(%g6)
350	lduw [%g6 + STRAND_ERR_FLAG], %g2 ! installed flags
351	btst %g4, %g2 ! handler installed?
352	bnz,pn %xcc, 9f ! yes
353
354	STRAND2CONFIG_STRUCT(%g6, %g4)
355	ldx [%g4 + CONFIG_CE_BLACKOUT], %g1
356	brz,a,pn %g1, 9f ! zero: blackout disabled
357	nop
358	SET_STRAND_ERR_FLAG(%g6, STRAND_ERR_FLAG_SOC, %g5)
359	setx soc_set_error_bits, %g5, %g2
360	RELOC_OFFSET(%g4, %g5)
361	sub %g2, %g5, %g2 ! g2 = handler address
362	setx SOC_CORRECTABLE_ERRORS, %g4, %g3 ! g3 = arg 0 : bit(s) to set
363	mov STRAND_ERR_FLAG_SOC, %g4 ! g4 = arg 1 : cpu flags to clear
364	! g1 = delta tick
365	VCPU_STRUCT(%g6)
366	! g6 - CPU struct
367	HVCALL(cyclic_add_rel) /* ( del_tick, address, arg0, arg1 ) */
368	9:
369	GET_ERR_RETURN_ADDR(%g7, %g2)
370	HVRET
371	SET_SIZE(soc_storm)
372
373	/*
374	* cyclic function used to re-enable SOC_TRAP_ENABLE bits
375	*
376	* %g1 SOC_TRAP_ENABLE bits to set
377	* %g2 CPU->err_flags to clear
378	* %g7 return address
379	* %g5 - %g6 clobbered
380	*/
381	ENTRY(soc_set_error_bits)
382	STRAND_STRUCT(%g6)
383	CLEAR_STRAND_ERR_FLAG(%g6, %g2, %g5)
384
385	setx SOC_ERROR_TRAP_ENABLE, %g4, %g5
386	ldx [%g5], %g4
387	or %g4, %g1, %g4
388	stx %g4, [%g5]
389	setx SOC_ERROR_LOG_ENABLE, %g4, %g5
390	ldx [%g5], %g4
391	or %g4, %g1, %g4
392	stx %g4, [%g5]
393
394	/*
395	* We need to clear the SOC ESRs in case they were
396	* set while the error traps were disabled
397	*/
398	ba,a clear_soc_after_storm ! tail call
399	! NOTREACHED
400	SET_SIZE(soc_set_error_bits)
401
402	ENTRY(soc_sun4v_report)
403	GET_ERR_SUN4V_RPRT_BUF(%g2, %g3)
404	brz,pn %g2, soc_sun4v_report_exit
405	.empty
406
407	! workaround for SOC ESRs always reading as 0
408	ba 1f
409	nop
410
411	setx SOC_NCU_ERROR_SYNDROME_REG, %g3, %g4
412	ldx [%g4], %g4
413	! has a valid syndrome been logged ?
414	setx SOC_NCU_ESR_V, %g3, %g5
415	btst %g5, %g4
416	bz,pn %xcc, soc_sun4v_report_exit
417	.empty
418	! has a valid strandid been logged ?
419	setx SOC_NCU_ESR_S, %g3, %g5
420	btst %g5, %g4
421	bz,pn %xcc, soc_sun4v_report_exit
422	.empty
423	! has a valid PA been logged ?
424	setx SOC_NCU_ESR_P, %g3, %g5
425	btst %g5, %g4
426	bz,pn %xcc, soc_sun4v_report_exit
427	.empty
428
429	1:
430	srlx %g4, SOC_NCU_ESR_STRANDID_SHIFT, %g5
431	and %g5, SOC_NCU_ESR_STRANDID_MASK, %g5
432	stuh %g5, [%g2 + ERR_SUN4V_RPRT_G_CPUID]
433	setx SOC_NCU_ESR_PA_MASK, %g3, %g5
434	and %g4, %g5, %g5
435	VCPU_STRUCT(%g6)
436	CPU_ERR_IO_PA_TO_RA(%g6, %g5, %g5)
437	GUEST_STRUCT(%g6)
438	mov 1, %g3
439	! %g6 guestp
440	! %g5 raddr (need PA -> RA)
441	! %g3 size
442	RANGE_CHECK_IO(%g6, %g5, %g3, soc_pa_good, soc_pa_bad, %g4, %g1)
443	soc_pa_bad:
444	mov CPU_ERR_INVALID_RA, %g5
445	soc_pa_good:
446	stx %g5, [%g2 + ERR_SUN4V_RPRT_ADDR]
447	/*
448	* SZ is 8 bytes for a single ASI VA
449	*/
450	mov 8, %g5
451	st %g5, [%g2 + ERR_SUN4V_RPRT_SZ]
452
453	soc_sun4v_report_exit:
454	HVRET
455	SET_SIZE(soc_sun4v_report)
456
457
458	ENTRY(print_soc)
459	#ifdef DEBUG_LEGION
460	STORE_ERR_RETURN_ADDR(%g7, %g4, %g5)
461	GET_ERR_DIAG_DATA_BUF(%g1, %g2)
462
463	/*
464	* print the D-SFSR/D-SFAR
465	*/
466	mov %g1, %g6
467	PRINT_NOTRAP("SOCU error: D-SFSR : ");
468	ldx [%g6 + ERR_DIAG_BUF_SPARC_DSFSR], %g3
469	PRINTX_NOTRAP(%g3)
470	PRINT_NOTRAP("\r\nSOCU error: D-SFAR : ");
471	ldx [%g6 + ERR_DIAG_BUF_SPARC_DSFAR], %g3
472	PRINTX_NOTRAP(%g3)
473	PRINT_NOTRAP("\r\nSOCU error: DESR: ");
474	GET_ERR_DESR(%g3, %g4)
475	PRINTX_NOTRAP(%g3)
476
477	/*
478	* get diag_buf->err_soc
479	*/
480	add %g6, ERR_DIAG_BUF_DIAG_DATA, %g6
481	add %g6, ERR_DIAG_DATA_SOC, %g6
482	! SOC Error Status Register
483	PRINT_NOTRAP("\r\nSOCU error: SOC ESR: ");
484	ldx [%g6 + ERR_SOC_ESR], %g3
485	PRINTX_NOTRAP(%g3)
486
487	! SOC Pending Error Status Register
488	PRINT_NOTRAP("\r\nSOCU error: SOC PENDING ESR: ");
489	ldx [%g6 + ERR_SOC_PESR], %g3
490	PRINTX_NOTRAP(%g3)
491
492	! SOC SII Syndrome Status Register
493	PRINT_NOTRAP("\r\nSOCU error: SOC SII ESR: ");
494	ldx [%g6 + ERR_SOC_SII_SYND], %g3
495	PRINTX_NOTRAP(%g3)
496
497	! SOC NCU Syndrome Status Register
498	PRINT_NOTRAP("\r\nSOCU error: SOC NCU SYND : ");
499	ldx [%g6 + ERR_SOC_NCU_SYND], %g3
500	PRINTX_NOTRAP(%g3)
501	PRINT_NOTRAP("\r\n");
502
503	GET_ERR_RETURN_ADDR(%g7, %g2)
504	#endif
505	HVRET
506	SET_SIZE(print_soc)
507
508	/*
509	* Set the DRAM FBR Error Count registers
510	*/
511	ENTRY(reset_fbr_counters)
512	set (NO_DRAM_BANKS - 1), %g3
513	1:
514	! skip banks which are disabled. causes hang.
515	SKIP_DISABLED_DRAM_BANK(%g3, %g4, %g5, 2f)
516
517	setx DRAM_FBR_COUNT_BASE, %g4, %g5
518	sllx %g3, DRAM_BANK_SHIFT, %g4
519	add %g5, %g4, %g5
520	ldx [%g5], %g4
521	brnz,pt %g4, 2f
522	mov DRAM_ERROR_COUNTER_FBR_RATIO, %g4
523	stx %g4, [%g5]
524	2:
525	! next bank
526	brgz,pt %g3, 1b
527	dec %g3
528
529	HVRET
530	SET_SIZE(reset_fbr_counters)
531
532	/*
533	* Clean up after FBR errors
534	* DSU errata (N2 erratum 190) means we must check whether
535	* the FBR has caused a bogus DSU error to be logged.
536	*/
537	ENTRY(reset_soc_fbr)
538	STRAND_PUSH(%g7, %g3, %g4)
539
540	GET_ERR_TABLE_ENTRY(%g3, %g4)
541	ld [%g3 + ERR_FLAGS], %g4
542	set ERR_CLEAR_SOC, %g3
543	btst %g4, %g3
544	bz,pn %xcc, 1f
545	nop
546
547	HVCALL(clear_soc)
548	1:
549	HVCALL(reset_fbr_counters)
550	HVCALL(verify_dsu_error)
551	HVCALL(clear_dram_l2c_esr_regs)
552	STRAND_POP(%g7, %g3)
553	HVRET
554	SET_SIZE(reset_soc_fbr)