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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * Hypervisor Software File: hcall_cpu.s | |
5 | * | |
6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
7 | * | |
8 | * - Do no alter or remove copyright notices | |
9 | * | |
10 | * - Redistribution and use of this software in source and binary forms, with | |
11 | * or without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistribution of source code must retain the above copyright notice, | |
15 | * this list of conditions and the following disclaimer. | |
16 | * | |
17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
18 | * this list of conditions and the following disclaimer in the | |
19 | * documentation and/or other materials provided with the distribution. | |
20 | * | |
21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
22 | * may be used to endorse or promote products derived from this software | |
23 | * without specific prior written permission. | |
24 | * | |
25 | * This software is provided "AS IS," without a warranty of any kind. | |
26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
37 | * | |
38 | * You acknowledge that this software is not designed, licensed or | |
39 | * intended for use in the design, construction, operation or maintenance of | |
40 | * any nuclear facility. | |
41 | * | |
42 | * ========== Copyright Header End ============================================ | |
43 | */ | |
44 | /* | |
45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
46 | * Use is subject to license terms. | |
47 | */ | |
48 | ||
49 | .ident "@(#)hcall_cpu.s 1.2 07/07/03 SMI" | |
50 | ||
51 | .file "hcall_cpu.s" | |
52 | ||
53 | #include <sys/asm_linkage.h> | |
54 | #include <asi.h> | |
55 | #include <sun4v/asi.h> | |
56 | #include <sun4v/queue.h> | |
57 | #include <hprivregs.h> | |
58 | #include <hypervisor.h> | |
59 | #include <ncu.h> | |
60 | #include <offsets.h> | |
61 | #include <config.h> | |
62 | #include <util.h> | |
63 | #include <clock.h> | |
64 | #include <cmp.h> | |
65 | #include <debug.h> | |
66 | #ifdef SUPPORT_NIAGARA2_1x | |
67 | #include <cache.h> | |
68 | #include <dram.h> | |
69 | #endif | |
70 | ||
71 | /* | |
72 | * Halt the current strand | |
73 | * | |
74 | * %g1 - %g6 clobbered | |
75 | * %g7 return address | |
76 | */ | |
77 | ENTRY_NP(plat_halt_strand) | |
78 | ||
79 | /* | |
80 | * The set of conditions where the halt instruction will "fall | |
81 | * through" is described in the PRM. However, the set doesn't | |
82 | * include a pending cpu, device or error queue interrupt. To | |
83 | * avoid halting this strand with a pending interrupt, check for | |
84 | * those first. | |
85 | */ | |
86 | mov CPU_MONDO_QUEUE_HEAD, %g1 | |
87 | ldxa [%g1]ASI_QUEUE, %g1 | |
88 | mov CPU_MONDO_QUEUE_TAIL, %g2 | |
89 | ldxa [%g2]ASI_QUEUE, %g2 | |
90 | cmp %g1, %g2 | |
91 | bne,pn %xcc, plat_halt_strand_exit | |
92 | mov DEV_MONDO_QUEUE_HEAD, %g1 | |
93 | ldxa [%g1]ASI_QUEUE, %g1 | |
94 | mov DEV_MONDO_QUEUE_TAIL, %g2 | |
95 | ldxa [%g2]ASI_QUEUE, %g2 | |
96 | cmp %g1, %g2 | |
97 | bne,pn %xcc, plat_halt_strand_exit | |
98 | mov ERROR_RESUMABLE_QUEUE_HEAD, %g1 | |
99 | ldxa [%g1]ASI_QUEUE, %g1 | |
100 | mov ERROR_RESUMABLE_QUEUE_TAIL, %g2 | |
101 | ldxa [%g2]ASI_QUEUE, %g2 | |
102 | cmp %g1, %g2 | |
103 | bne,pn %xcc, plat_halt_strand_exit | |
104 | nop | |
105 | ||
106 | HALT_STRAND() | |
107 | ||
108 | plat_halt_strand_exit: | |
109 | ||
110 | HVRET | |
111 | ||
112 | SET_SIZE(plat_halt_strand) | |
113 | ||
114 | ||
115 | #ifdef SUPPORT_NIAGARA2_1x | |
116 | /* Serial Number Register */ | |
117 | #define SERIAL_NUMBER 0x8000001000 | |
118 | ||
119 | /* DRAM CAS Address Width Register (Count 4 Step 4096) */ | |
120 | #define DRAM_CAS_ADDR_WIDTH_REG0 0x8400000000 | |
121 | #define DRAM_CAS_ADDR_WIDTH_REG1 0x8400001000 | |
122 | #define DRAM_CAS_ADDR_WIDTH_REG2 0x8400002000 | |
123 | #define DRAM_CAS_ADDR_WIDTH_REG3 0x8400003000 | |
124 | ||
125 | /* PLL Control Register */ | |
126 | #define PLL_CONTROL_REG (CLK_BASE + PLL_CTL_REG) | |
127 | ||
128 | /* PLL Lock Time Register */ | |
129 | #define PLL_LOCK_TIME_REG 0x8900000870 | |
130 | ||
131 | /* PEU Control Register */ | |
132 | #define PEU_CTRL_REG 0x8800680000 | |
133 | ||
134 | /* Debug Port Configuration Register */ | |
135 | #define DEBUG_PORT_CFG_REG 0x8600000000 | |
136 | ||
137 | ||
138 | #define TABLE_TWEAK(table, reg, bank, scr1, scr2) \ | |
139 | .pushlocals ;\ | |
140 | /* skip banks which are disabled. causes hang. */ ;\ | |
141 | SKIP_DISABLED_DRAM_BANK(bank, scr1, scr2, 0f) ;\ | |
142 | setx reg, scr2, scr1 ;\ | |
143 | stx scr1, [table + (bank * 8)] ;\ | |
144 | 0: .poplocals | |
145 | ||
146 | ||
147 | ENTRY_NP(init_cpu_yield_table) | |
148 | mov %g7, %l7 /* save return address */ | |
149 | PRINT("HV:init_cpu_yield_table\r\n") | |
150 | ||
151 | LABEL_ADDRESS(niagara2_cpu_yield_paddr_table, %g1) | |
152 | ||
153 | TABLE_TWEAK(%g1, DRAM_CAS_ADDR_WIDTH_REG0, /* bank */ 0, %g2, %g3) | |
154 | TABLE_TWEAK(%g1, DRAM_CAS_ADDR_WIDTH_REG1, /* bank */ 1, %g2, %g3) | |
155 | TABLE_TWEAK(%g1, DRAM_CAS_ADDR_WIDTH_REG2, /* bank */ 2, %g2, %g3) | |
156 | TABLE_TWEAK(%g1, DRAM_CAS_ADDR_WIDTH_REG3, /* bank */ 3, %g2, %g3) | |
157 | ||
158 | jmp %l7 + 4 | |
159 | nop | |
160 | SET_SIZE(init_cpu_yield_table) | |
161 | ||
162 | ||
163 | .section ".text" | |
164 | .align 8 | |
165 | .global niagara2_cpu_yield_paddr_table | |
166 | niagara2_cpu_yield_paddr_table: | |
167 | .xword SERIAL_NUMBER | |
168 | .xword SERIAL_NUMBER | |
169 | .xword SERIAL_NUMBER | |
170 | .xword SERIAL_NUMBER | |
171 | .xword PLL_CONTROL_REG | |
172 | .xword PLL_LOCK_TIME_REG | |
173 | .xword PEU_CTRL_REG | |
174 | .xword DEBUG_PORT_CFG_REG | |
175 | #endif /* SUPPORT_NIAGARA2_1x */ |