[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / src / hcall_niagara2.s

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: hcall_niagara2.s
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

	.ident	"@(#)hcall_niagara2.s	1.1	07/05/03 SMI"

#include <sys/asm_linkage.h>
#include <sun4v/asi.h>
#include <asi.h>
#include <offsets.h>
#include <vcpu.h>
#include <guest.h>
#include <util.h>
#include <cache.h>
#include <dram.h>
#include <debug.h>


	.section ".text"
	.align	32

/*
 * niagara2_getperf
 *
 * arg0 SPARC/DRAM performance register ID (%o0):
 *
 *  %o0(RegId)		Description                RegAddr
 *  ------------------------------------------------------------
 *   0    SPARC Performance Control register    ASR 0x10
 *   1    DRAM Performance Control register 0   DRAM_PERF_CTL0
 *   2    DRAM Performance Counter register 0   DRAM_PERF_COUNT0
 *   3    DRAM Performance Control register 1   DRAM_PERF_CTL1
 *   4    DRAM Performance Counter register 1   DRAM_PERF_COUNT0
 *   5    DRAM Performance Control register 2   DRAM_PERF_CTL2
 *   6    DRAM Performance Counter register 2   DRAM_PERF_COUNT2
 *   7    DRAM Performance Control register 3   DRAM_PERF_CTL3
 *   8    DRAM Performance Counter register 3   DRAM_PERF_COUNT3
 *  ------------------------------------------------------------
 *
 * ret0 status (%o0)
 * ret1 Perf register value (%o1)
 */
	ENTRY_NP(hcall_niagara2_getperf)
	! check if SPARC/DRAM perf registers are accessible
	GUEST_STRUCT(%g1)
	set	GUEST_PERFREG_ACCESSIBLE, %g2
	ldx	[%g1 + %g2], %g2
	brz,pn	%g2, herr_noaccess
	.empty

	! check if perfreg within range
	cmp	%o0, NIAGARA2_PERFREG_MAX
	bgeu,pn %xcc, herr_inval
	nop

	! read asr reg directly (special case, regId = 0),
	! do the rest by looking up the perf_paddr table
	brnz,a	%o0, 1f
	sub	%o0, 1, %g4			! get table entry pointer

	rd      PERFCNTRCTRL, %o1		! read sparc perf reg
	ba,pt	%xcc, 2f
	nop

1:
	/*
	 * If the required bank is disabled, return 0
	 */
	srlx	%g4, 1, %g5			! bank = (regId-1)/2
	SKIP_DISABLED_DRAM_BANK(%g5, %g3, %g2, 3f)

	set	niagara2_perf_paddr_table - niagara2_getperf_1, %g2
niagara2_getperf_1:
	rd	%pc, %g3
	add	%g2, %g3, %g2
	sllx	%g4, 4, %g4			! table entry offset
	add	%g4, %g2, %g2
	ldx	[%g2], %g3			! get perf reg paddr
	ldx	[%g3], %o1			! read dram perf reg
2:
	HCALL_RET(EOK)
3:
	mov	%g0, %o1	
	HCALL_RET(EOK)
	SET_SIZE(hcall_niagara2_getperf)

/*
 * niagara2_setperf
 *
 * arg0 SPARC/DRAM performance register ID (%o0)
 * arg1 perf register value (%o1)
 * ---
 * ret0 status (%o0)
 */
	ENTRY_NP(hcall_niagara2_setperf)
	! check if SPARC/DRAM perf registers are accessible
	GUEST_STRUCT(%g1)
	set	GUEST_PERFREG_ACCESSIBLE, %g2
	ldx	[%g1 + %g2], %g2
	brz,pn	%g2, herr_noaccess
	.empty

	! check if perfreg within range
	cmp	%o0, NIAGARA2_PERFREG_MAX
	bgeu,pn	%xcc, herr_inval
	nop

	! write asr reg directly (special case, regId = 0),
	! do the rest by looking up the perf_paddr table
	brnz,a	%o0, 1f
	sub	%o0, 1, %g4			! get table entry pointer

	/*
	 * guest is allowed to count hpriv events only
	 * if the "perfctrhtaccess" property is set
	 */
	btst	NIAGARA2_PERFCNTRCTL_HT, %o1
	bz,pt	%xcc, 0f
	nop
	set	GUEST_PERFREGHT_ACCESSIBLE, %g2
	ldx	[%g1 + %g2], %g2
	brz,pn	%g2, herr_noaccess
	nop
		
0:	wr      %o1, 0, PERFCNTRCTRL		! write sparc perf reg
	ba,pt	%xcc, 2f
	nop

1:	
	/*
	 * If the required bank is disabled, do nothing
	 */
	srlx	%g4, 1, %g5			! bank = (regId-1)/2
	SKIP_DISABLED_DRAM_BANK(%g5, %g3, %g2, 2f)

	set	niagara2_perf_paddr_table - niagara2_setperf_1, %g2
niagara2_setperf_1:
	rd	%pc, %g3
	add	%g2, %g3, %g2
	sllx	%g4, 4, %g4			! perf table entry offset
	add	%g4, %g2, %g2
	ldx	[%g2], %g3			! get perf reg paddr
	ldx	[%g2+8], %g1			! get perf reg write mask
	and	%g1, %o1, %g1
	stx	%g1, [%g3]			! write perf reg
2:
	HCALL_RET(EOK)
	SET_SIZE(hcall_niagara2_setperf)

/*
 * Niagara2 DRAM performance register physical address/mask table
 * (order must match performance RegId assignment, starting with RegId=1)
 */
	.section ".text"
	.align	8
niagara2_perf_paddr_table:
	.xword	DRAM_PERF_CTL0, 0xff
	.xword	DRAM_PERF_COUNT0, 0xffffffffffffffff
	.xword	DRAM_PERF_CTL1, 0xff
	.xword	DRAM_PERF_COUNT1, 0xffffffffffffffff
	.xword	DRAM_PERF_CTL2, 0xff
	.xword	DRAM_PERF_COUNT2, 0xffffffffffffffff
	.xword	DRAM_PERF_CTL3, 0xff
	.xword	DRAM_PERF_COUNT3, 0xffffffffffffffff
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: hcall_niagara2.s
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	.ident "@(#)hcall_niagara2.s 1.1 07/05/03 SMI"
	50
	51	#include <sys/asm_linkage.h>
	52	#include <sun4v/asi.h>
	53	#include <asi.h>
	54	#include <offsets.h>
	55	#include <vcpu.h>
	56	#include <guest.h>
	57	#include <util.h>
	58	#include <cache.h>
	59	#include <dram.h>
	60	#include <debug.h>
	61
	62
	63	.section ".text"
	64	.align 32
65
66	/*
67	* niagara2_getperf
68	*
69	* arg0 SPARC/DRAM performance register ID (%o0):
70	*
71	* %o0(RegId) Description RegAddr
72	* ------------------------------------------------------------
73	* 0 SPARC Performance Control register ASR 0x10
74	* 1 DRAM Performance Control register 0 DRAM_PERF_CTL0
75	* 2 DRAM Performance Counter register 0 DRAM_PERF_COUNT0
76	* 3 DRAM Performance Control register 1 DRAM_PERF_CTL1
77	* 4 DRAM Performance Counter register 1 DRAM_PERF_COUNT0
78	* 5 DRAM Performance Control register 2 DRAM_PERF_CTL2
79	* 6 DRAM Performance Counter register 2 DRAM_PERF_COUNT2
80	* 7 DRAM Performance Control register 3 DRAM_PERF_CTL3
81	* 8 DRAM Performance Counter register 3 DRAM_PERF_COUNT3
82	* ------------------------------------------------------------
83	*
84	* ret0 status (%o0)
85	* ret1 Perf register value (%o1)
86	*/
87	ENTRY_NP(hcall_niagara2_getperf)
88	! check if SPARC/DRAM perf registers are accessible
89	GUEST_STRUCT(%g1)
90	set GUEST_PERFREG_ACCESSIBLE, %g2
91	ldx [%g1 + %g2], %g2
92	brz,pn %g2, herr_noaccess
93	.empty
94
95	! check if perfreg within range
96	cmp %o0, NIAGARA2_PERFREG_MAX
97	bgeu,pn %xcc, herr_inval
98	nop
99
100	! read asr reg directly (special case, regId = 0),
101	! do the rest by looking up the perf_paddr table
102	brnz,a %o0, 1f
103	sub %o0, 1, %g4 ! get table entry pointer
104
105	rd PERFCNTRCTRL, %o1 ! read sparc perf reg
106	ba,pt %xcc, 2f
107	nop
108
109	1:
110	/*
111	* If the required bank is disabled, return 0
112	*/
113	srlx %g4, 1, %g5 ! bank = (regId-1)/2
114	SKIP_DISABLED_DRAM_BANK(%g5, %g3, %g2, 3f)
115
116	set niagara2_perf_paddr_table - niagara2_getperf_1, %g2
117	niagara2_getperf_1:
118	rd %pc, %g3
119	add %g2, %g3, %g2
120	sllx %g4, 4, %g4 ! table entry offset
121	add %g4, %g2, %g2
122	ldx [%g2], %g3 ! get perf reg paddr
123	ldx [%g3], %o1 ! read dram perf reg
124	2:
125	HCALL_RET(EOK)
126	3:
127	mov %g0, %o1
128	HCALL_RET(EOK)
129	SET_SIZE(hcall_niagara2_getperf)
130
131	/*
132	* niagara2_setperf
133	*
134	* arg0 SPARC/DRAM performance register ID (%o0)
135	* arg1 perf register value (%o1)
136	* ---
137	* ret0 status (%o0)
138	*/
139	ENTRY_NP(hcall_niagara2_setperf)
140	! check if SPARC/DRAM perf registers are accessible
141	GUEST_STRUCT(%g1)
142	set GUEST_PERFREG_ACCESSIBLE, %g2
143	ldx [%g1 + %g2], %g2
144	brz,pn %g2, herr_noaccess
145	.empty
146
147	! check if perfreg within range
148	cmp %o0, NIAGARA2_PERFREG_MAX
149	bgeu,pn %xcc, herr_inval
150	nop
151
152	! write asr reg directly (special case, regId = 0),
153	! do the rest by looking up the perf_paddr table
154	brnz,a %o0, 1f
155	sub %o0, 1, %g4 ! get table entry pointer
156
157	/*
158	* guest is allowed to count hpriv events only
159	* if the "perfctrhtaccess" property is set
160	*/
161	btst NIAGARA2_PERFCNTRCTL_HT, %o1
162	bz,pt %xcc, 0f
163	nop
164	set GUEST_PERFREGHT_ACCESSIBLE, %g2
165	ldx [%g1 + %g2], %g2
166	brz,pn %g2, herr_noaccess
167	nop
168
169	0: wr %o1, 0, PERFCNTRCTRL ! write sparc perf reg
170	ba,pt %xcc, 2f
171	nop
172
173	1:
174	/*
175	* If the required bank is disabled, do nothing
176	*/
177	srlx %g4, 1, %g5 ! bank = (regId-1)/2
178	SKIP_DISABLED_DRAM_BANK(%g5, %g3, %g2, 2f)
179
180	set niagara2_perf_paddr_table - niagara2_setperf_1, %g2
181	niagara2_setperf_1:
182	rd %pc, %g3
183	add %g2, %g3, %g2
184	sllx %g4, 4, %g4 ! perf table entry offset
185	add %g4, %g2, %g2
186	ldx [%g2], %g3 ! get perf reg paddr
187	ldx [%g2+8], %g1 ! get perf reg write mask
188	and %g1, %o1, %g1
189	stx %g1, [%g3] ! write perf reg
190	2:
191	HCALL_RET(EOK)
192	SET_SIZE(hcall_niagara2_setperf)
193
194	/*
195	* Niagara2 DRAM performance register physical address/mask table
196	* (order must match performance RegId assignment, starting with RegId=1)
197	*/
198	.section ".text"
199	.align 8
200	niagara2_perf_paddr_table:
201	.xword DRAM_PERF_CTL0, 0xff
202	.xword DRAM_PERF_COUNT0, 0xffffffffffffffff
203	.xword DRAM_PERF_CTL1, 0xff
204	.xword DRAM_PERF_COUNT1, 0xffffffffffffffff
205	.xword DRAM_PERF_CTL2, 0xff
206	.xword DRAM_PERF_COUNT2, 0xffffffffffffffff
207	.xword DRAM_PERF_CTL3, 0xff
208	.xword DRAM_PERF_COUNT3, 0xffffffffffffffff