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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / src / offsets.in
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AT		 1\ ========== Copyright Header Begin ==========================================
2\
3\ Hypervisor Software File: offsets.in
4\
5\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6\
7\ - Do no alter or remove copyright notices
8\
9\ - Redistribution and use of this software in source and binary forms, with
10\ or without modification, are permitted provided that the following
11\ conditions are met:
12\
13\ - Redistribution of source code must retain the above copyright notice,
14\ this list of conditions and the following disclaimer.
15\
16\ - Redistribution in binary form must reproduce the above copyright notice,
17\ this list of conditions and the following disclaimer in the
18\ documentation and/or other materials provided with the distribution.
19\
20\ Neither the name of Sun Microsystems, Inc. or the names of contributors
21\ may be used to endorse or promote products derived from this software
22\ without specific prior written permission.
23\
24\ This software is provided "AS IS," without a warranty of any kind.
25\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
26\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
27\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
28\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
29\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
30\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
31\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
32\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
33\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
34\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
35\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
36\
37\ You acknowledge that this software is not designed, licensed or
38\ intended for use in the design, construction, operation or maintenance of
39\ any nuclear facility.
40\
41\ ========== Copyright Header End ============================================
42\
43\ Copyright 2007 by Sun Microsystems, Inc. All rights reserved.
44\ Use is subject to license terms.
45\
46\ offsets.in: input file to produce offsets.h using the stabs program
47\
48#pragma ident "@(#)offsets.in 1.12 07/08/01 SMI"
49
50#ifndef _OFFSETS_H
51#define _OFFSETS_H
52#endif
53
54#include <sys/htypes.h>
55#include <sun4v/mmu.h>
56#include <traps.h>
57#include <mmu.h>
58#include <cache.h>
59#include <error_defs.h>
60#include <vpiu_errs_defs.h>
61#include <hypervisor.h>
62#include <svc.h>
63#include <vdev_ops.h>
64#include <vdev_intr.h>
65#include <piu.h>
66#include <svc_vbsc.h>
67#include <ncs.h>
68#include <rng.h>
69#include <cyclic.h>
70#include <vcpu.h>
71#include <mau.h>
72#include <cwq.h>
73#include <strand.h>
74#include <guest.h>
75#include <ldc.h>
76#include <hvctl.h>
77#include <md.h>
78#include <pcie.h>
79#include <config.h>
80#include <fpga.h>
81#include <vdev_simdisk.h>
82
83#include <md/md_impl.h>
84
85nametable NAMETABLE_SIZE
86
87config CONFIG_SIZE
88 membase CONFIG_MEMBASE
89 memsize CONFIG_MEMSIZE
90 physmemsize CONFIG_PHYSMEMSIZE
91 reloc CONFIG_RELOC
92 parse_hvmd CONFIG_PARSE_HVMD
93 active_hvmd CONFIG_ACTIVE_HVMD
94 guests CONFIG_GUESTS
95 mblocks CONFIG_MBLOCKS
96 vcpus CONFIG_VCPUS
97 strands CONFIG_STRANDS
98 vstate CONFIG_VSTATE
99 ldcb_pa CONFIG_LDCB_PA
100 pcie_busses CONFIG_PCIE_BUSSES
101 strand_startset CONFIG_STRAND_STARTSET
102 hv_ldcs CONFIG_HV_LDCS
103 sp_ldcs CONFIG_SP_LDCS
104 sp_ldc_max_cid CONFIG_SP_LDC_MAX_CID
105 hvuart_addr CONFIG_HVUART_ADDR
106 tod CONFIG_TOD
107 todfrequency CONFIG_TODFREQUENCY
108 sys_hwtw_mode CONFIG_SYS_HWTW_MODE
109 stickfrequency CONFIG_STICKFREQUENCY
110 dummytsbp CONFIG_DUMMYTSB
111 guests_dtnode CONFIG_GUESTS_DTNODE
112 cpus_dtnode CONFIG_CPUS_DTNODE
113 hv_ldcs_dtnode CONFIG_HV_LDCS_DTNODE
114 sp_ldcs_dtnode CONFIG_SP_LDCS_DTNODE
115 ldcb_dtnode CONFIG_LDCB_DTNODE
116 svc CONFIG_SVCS
117 vintr CONFIG_VINTR
118 devs_dtnode CONFIG_DEVS_DTNODE
119 svcs_dtnode CONFIG_SVCS_DTNODE
120 error_svch CONFIG_ERROR_SVCH
121 vbsc_dbgerror CONFIG_VBSC_DBGERROR
122 vbsc_svch CONFIG_VBSC_SVCH
123 error_lock CONFIG_ERRORLOCK
124 hdnametable CONFIG_HDNAMETABLE
125 memscrub_max CONFIG_MEMSCRUB_MAX
126 intrtgt CONFIG_INTRTGT
127 devinstancesp CONFIG_DEVINSTANCES
128 erpt_pa CONFIG_ERPT_PA
129 erpt_size CONFIG_ERPT_SIZE
130 sram_erpt_buf_inuse CONFIG_SRAM_ERPT_BUF_INUSE
131 cyclic_maxd CONFIG_CYCLIC_MAXD
132 ce_blackout CONFIG_CE_BLACKOUT
133 ce_poll_time CONFIG_CE_POLL_TIME
134 single_strand_lock CONFIG_SINGLE_STRAND_LOCK
135 strand_present CONFIG_STPRES
136 strand_active CONFIG_STACTIVE
137 strand_idle CONFIG_STIDLE
138 strand_halt CONFIG_STHALT
139 print_spinlock CONFIG_PRINT_SPINLOCK
140 errs_to_send CONFIG_ERRS_TO_SEND
141 heartbeat_cpu CONFIG_HEARTBEAT_CPU
142 hvctl_hv_seq CONFIG_HVCTL_HV_SEQ
143 hvctl_zeus_seq CONFIG_HVCTL_ZEUS_SEQ
144 hvctl_major CONFIG_HVCTL_MAJOR
145 hvctl_minor CONFIG_HVCTL_MINOR
146 hvctl_state CONFIG_HVCTL_STATE
147 hvctl_rand_num CONFIG_HVCTL_RAND_NUM
148 hvctl_ibuf CONFIG_HVCTL_IBUF
149 hvctl_obuf CONFIG_HVCTL_OBUF
150 hvctl_ip CONFIG_HVCTL_IP
151 hvctl_ldc CONFIG_HVCTL_LDC
152 hvctl_ldc_lock CONFIG_HVCTL_LDC_LOCK
153 del_reconf_gid CONFIG_DEL_RECONF_GID
154 scrub_sync CONFIG_SCRUB_SYNC
155 fpga_status_lock CONFIG_FPGA_STATUS_LOCK
156 l2scrub_interval CONFIG_L2SCRUB_INTERVAL
157 l2scrub_entries CONFIG_L2SCRUB_ENTRIES
158 config_m CONFIG_MCONFIG
159
160mau MAU_SIZE
161 pid MAU_PID
162 state MAU_STATE
163 handle MAU_HANDLE
164 ino MAU_INO
165 cpuset MAU_CPUSET
166 store_in_progr MAU_STORE_IN_PROGR
167 enable_cwq MAU_ENABLE_CWQ
168 cpu_active MAU_CPU_ACTIVE
169 queue MAU_QUEUE
170 ihdlr MAU_IHDLR
171
172cwq CWQ_SIZE
173 pid CWQ_PID
174 state CWQ_STATE
175 handle CWQ_HANDLE
176 ino CWQ_INO
177 cpuset CWQ_CPUSET
178 cpu_active CWQ_CPU_ACTIVE
179 queue CWQ_QUEUE
180 ihdlr CWQ_IHDLR
181
182rng RNG_SIZE
183 lock RNG_LOCK
184 ctl RNG_CTL
185
186rwindow RWINDOW_SIZE
187
188vcpu_trapstate VCPUTRAPSTATE_SIZE
189 tpc VCTS_TPC
190 tnpc VCTS_TNPC
191 tstate VCTS_TSTATE
192 tt VCTS_TT
193 htstate VCTS_HTSTATE
194
195vcpu_globals VCPU_GLOBALS_SIZE
196 g VCPU_GLOBALS_G
197
198vcpustate VCPUSTATE_SIZE
199 tl VS_TL
200 trapstack VS_TRAPSTACK
201 gl VS_GL
202 globals VS_GLOBALS
203 tba VS_TBA
204 y VS_Y
205 asi VS_ASI
206 softint VS_SOFTINT
207 pil VS_PIL
208 gsr VS_GSR
209 tick VS_TICK
210 stick VS_STICK
211 stickcompare VS_STICKCOMPARE
212 scratchpad VS_SCRATCHPAD
213 cwp VS_CWP
214 wstate VS_WSTATE
215 cansave VS_CANSAVE
216 canrestore VS_CANRESTORE
217 otherwin VS_OTHERWIN
218 cleanwin VS_CLEANWIN
219 wins VS_WINS
220 globals VS_GLOBALS
221 cpu_mondo_head VS_CPU_MONDO_HEAD
222 cpu_mondo_tail VS_CPU_MONDO_TAIL
223 dev_mondo_head VS_DEV_MONDO_HEAD
224 dev_mondo_tail VS_DEV_MONDO_TAIL
225 error_resumable_head VS_ERROR_RESUMABLE_HEAD
226 error_resumable_tail VS_ERROR_RESUMABLE_TAIL
227 error_nonresumable_head VS_ERROR_NONRESUMABLE_HEAD
228 error_nonresumable_tail VS_ERROR_NONRESUMABLE_TAIL
229
230vcpu VCPU_SIZE
231 guest CPU_GUEST
232 root CPU_ROOT
233 strand CPU_STRAND
234 res_id CPU_RES_ID
235 strand_slot CPU_STRAND_SLOT
236 vid CPU_VID
237 parttag CPU_PARTTAG
238 maup CPU_MAU
239 cwqp CPU_CWQ
240 start_pc CPU_START_PC
241 start_arg CPU_START_ARG
242 rtba CPU_RTBA
243 mmu_area CPU_MMU_AREA
244 mmu_area_ra CPU_MMU_AREA_RA
245 pending_senders CPU_PENDING_SENDERS
246 cpuq_base CPU_CPUQ_BASE
247 cpuq_size CPU_CPUQ_SIZE
248 cpuq_mask CPU_CPUQ_MASK
249 cpuq_base_ra CPU_CPUQ_BASE_RA
250 devq_lock CPU_DEVQ_LOCK
251 devq_base CPU_DEVQ_BASE
252 devq_size CPU_DEVQ_SIZE
253 devq_mask CPU_DEVQ_MASK
254 devq_base_ra CPU_DEVQ_BASE_RA
255 devq_shdw_tail CPU_DEVQ_SHDW_TAIL
256 errqnr_base CPU_ERRQNR_BASE
257 errqnr_size CPU_ERRQNR_SIZE
258 errqnr_mask CPU_ERRQNR_MASK
259 errqnr_base_ra CPU_ERRQNR_BASE_RA
260 errqr_base CPU_ERRQR_BASE
261 errqr_size CPU_ERRQR_SIZE
262 errqr_mask CPU_ERRQR_MASK
263 errqr_base_ra CPU_ERRQR_BASE_RA
264 status CPU_STATUS
265 command CPU_COMMAND
266 lastpoke CPU_CMD_LASTPOKE
267 arg0 CPU_CMD_ARG0
268 arg1 CPU_CMD_ARG1
269 arg2 CPU_CMD_ARG2
270 arg3 CPU_CMD_ARG3
271 arg4 CPU_CMD_ARG4
272 arg5 CPU_CMD_ARG5
273 arg6 CPU_CMD_ARG6
274 arg7 CPU_CMD_ARG7
275 vintr CPU_VINTR
276 ntsbs_ctx0 CPU_NTSBS_CTX0
277 ntsbs_ctxn CPU_NTSBS_CTXn
278 tsbds_ctx0 CPU_TSBDS_CTX0
279 tsbds_ctxn CPU_TSBDS_CTXn
280 mmustat_area CPU_MMUSTAT_AREA
281 mmustat_area_ra CPU_MMUSTAT_AREA_RA
282 rng CPU_RNG
283 svcregs CPU_SVCREGS
284 scr CPU_SCR
285 ttrace_buf_size CPU_TTRACEBUF_SIZE
286 ttrace_buf_ra CPU_TTRACEBUF_RA
287 ttrace_buf_pa CPU_TTRACEBUF_PA
288 ttrace_offset CPU_TTRACE_OFFSET
289 ldc_intr_pend CPU_LDC_INTR_PEND
290 ldc_endpoint CPU_LDC_ENDPOINT
291 state_save_area CPU_STATE_SAVE_AREA
292 launch_with_retry CPU_LAUNCH_WITH_RETRY
293 util CPU_UTIL
294
295\#define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR))
296\#define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR))
297\#define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR))
298\#define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR))
299
300vcpu_util VCPU_UTIL_SIZE
301 stick_last VCUTIL_STICK_LAST
302 yield_count VCUTIL_YIELD_COUNT
303 yield_start VCUTIL_YIELD_START
304
305\#define CPU_UTIL_STICK_LAST (CPU_UTIL + VCUTIL_STICK_LAST)
306\#define CPU_UTIL_YIELD_COUNT (CPU_UTIL + VCUTIL_YIELD_COUNT)
307\#define CPU_UTIL_YIELD_START (CPU_UTIL + VCUTIL_YIELD_START)
308
309sched_slot SCHED_SLOT_SIZE
310 action SCHED_SLOT_ACTION
311 arg SCHED_SLOT_ARG
312
313hvctl_header HVCTL_HEADER_SIZE
314 op HVCTL_HEADER_OP
315
316hvctl_msg HVCTL_MSG_SIZE
317 hdr HVCTL_MSG_HDR
318 msg HVCTL_MSG_MSG
319
320hvm_sched HVM_SCHED_SIZE
321 vcpup HVM_SCHED_VCPUP
322
323hvm_scrub HVM_SCRUB_SIZE
324 start_pa HVM_SCRUB_START_PA
325 len HVM_SCRUB_START_LEN
326
327hvm_guestcmd HVM_GUESTCMD_SIZE
328 vcpup HVM_GUESTCMD_VCPUP
329 arg HVM_GUESTCMD_ARG
330
331hvm_stopguest HVM_STOPGUEST_SIZE
332 guestp HVM_STOPGUEST_GUESTP
333
334hvm HVM_SIZE
335 cmd HVM_CMD
336 from_strandp HVM_FROM_STRANDP
337 args HVM_ARGS
338
339xcall_mbox XCALL_MBOX_SIZE
340 command XCMB_COMMAND
341 mondobuf XCMB_MONDOBUF
342
343mini_stack MINI_STACK_SIZE
344 ptr MINI_STACK_PTR
345 val MINI_STACK_VAL
346
347pcie_device PCIE_DEVICE_SIZE
348 res PCIE_DEVICE_RES
349 guestp PCIE_DEVICE_GUESTP
350
351strand STRAND_SIZE
352 configp STRAND_CONFIGP
353 id STRAND_ID
354 current_slot STRAND_CURRENT_SLOT
355 slot STRAND_SLOT
356 xc_mb STRAND_XCALL_MBOX
357 hv_txmondo STRAND_HV_TXMONDO
358 hv_rxmondo STRAND_HV_RXMONDO
359 scrub_basepa STRAND_SCRUB_BASEPA
360 scrub_size STRAND_SCRUB_SIZE
361 mini_stack STRAND_MINI_STACK
362 scr STRAND_SCR
363 ue_tmp1 STRAND_UE_TMP1
364 ue_tmp2 STRAND_UE_TMP2
365 ue_tmp3 STRAND_UE_TMP3
366 ue_globals STRAND_UE_GLOBALS
367 err_seq_no STRAND_ERR_SEQ_NO
368 err_flag STRAND_ERR_FLAG
369 strand_diag_buf STRAND_DIAG_BUF
370 strand_sun4v_rprt_buf STRAND_SUN4V_RPRT_BUF
371 strand_err_table_entry STRAND_ERR_TABLE_ENTRY
372 strand_err_isfsr STRAND_ERR_ISFSR
373 strand_err_dsfsr STRAND_ERR_DSFSR
374 strand_err_dsfar STRAND_ERR_DSFAR
375 strand_err_desr STRAND_ERR_DESR
376 strand_err_dfesr STRAND_ERR_DFESR
377 strand_err_return_addr STRAND_ERR_RETURN_ADDR
378 io_prot STRAND_IO_PROT
379 io_error STRAND_IO_ERROR
380 nrpending STRAND_NRPENDING
381 rerouted_cpu STRAND_REROUTED_CPU
382 rerouted_ehdl STRAND_REROUTED_EHDL
383 rerouted_addr STRAND_REROUTED_ADDR
384 rerouted_stick STRAND_REROUTED_STICK
385 rerouted_attr STRAND_REROUTED_ATTR
386 abort_pc STRAND_ABORT_PC
387 err_globals_saved STRAND_ERR_GLOBALS_SAVED
388 trapstate STRAND_FAIL_TRAPSTATE
389 trapglobals STRAND_FAIL_TRAPGLOBALS
390 fail_gl STRAND_FAIL_GL
391 fail_tl STRAND_FAIL_TL
392 mra STRAND_MRA
393 strand_stack STRAND_STACK
394 cyclic STRAND_CYCLIC
395
396\#define STRAND_SCR0 (STRAND_SCR + (0 * STRAND_SCR_INCR))
397\#define STRAND_SCR1 (STRAND_SCR + (1 * STRAND_SCR_INCR))
398\#define STRAND_SCR2 (STRAND_SCR + (2 * STRAND_SCR_INCR))
399\#define STRAND_SCR3 (STRAND_SCR + (3 * STRAND_SCR_INCR))
400
401\#define STRAND_FP_TMP1 STRAND_UE_TMP1
402\#define STRAND_FP_TMP2 STRAND_UE_TMP2
403\#define STRAND_FP_TMP3 STRAND_UE_TMP3
404\#define STRAND_ERR_ESR_INCR STRAND_ERR_ISFSR_INCR
405
406\#define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR))
407\#define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR))
408\#define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR))
409\#define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR))
410\#define ENDOFSTACK (STACK_VAL_INCR * (STACKDEPTH + 1))
411\#define TOP (CPU_STACK + STACK_TOP)
412
413mapping MAPPING_SIZE
414 _map_entry_aligned MAPPING_ENTRY_ALIGNED
415 icpuset MAPPING_ICPUSET
416 dcpuset MAPPING_DCPUSET
417
418map_entry_aligned
419 _map_data MAP_ENTRY_ALIGNED_DATA
420
421map_data
422 va MAP_DATA_VA
423 tte MAP_DATA_TTE
424
425\#define MAPPING_VA (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_VA)
426\#define MAPPING_TTE (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_TTE)
427
428stack STACK_SIZE
429 top STACK_TOP
430 val STACK_VAL
431
432\#define BANK_SHIFT 6
433
434\#define CPU_EVBSC_L2_AFSR(n) CPU_VBSC_ERPT + EVBSC_L2_AFSR + (n * EVBSC_L2_AFSR_INCR)
435
436\#define CPU_EVBSC_L2_AFAR(n) CPU_VBSC_ERPT + EVBSC_L2_AFAR + (n * EVBSC_L2_AFAR_INCR)
437
438\#define CPU_EVBSC_DRAM_AFSR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFSR + (n * EVBSC_DRAM_AFSR_INCR)
439
440\#define CPU_EVBSC_DRAM_AFAR(n) CPU_VBSC_ERPT + EVBSC_DRAM_AFAR + (n * EVBSC_DRAM_AFAR_INCR)
441
442\#define CPU_EVBSC_DRAM_CNTR(n) CPU_VBSC_ERPT + EVBSC_DRAM_CNTR + (n * EVBSC_DRAM_CNTR_INCR)
443
444\#define CPU_EVBSC_DRAM_LOC(n) CPU_VBSC_ERPT + EVBSC_DRAM_LOC + (n * EVBSC_DRAM_LOC_INCR)
445
446\#define CPU_EVBSC_DCACHE_DATA(n) DCACHE_DATA + (n * DCACHE_DATA_INCR)
447
448\#define CPU_EVBSC_ICACHE_DIAG_DATA(n) DIAG_BUF_ICACHE + ICACHE_DIAG_DATA + (n * ICACHE_DIAG_DATA_INCR)
449
450epkt EPKTSIZE
451 sysino PCIERPT_SYSINO
452 sun4v_ehdl PCIERPT_SUN4V_EHDL
453 sun4v_stick PCIERPT_SUN4V_STICK
454 sun4v_desc PCIERPT_SUN4V_DESC
455 sun4v_specfic PCIERPT_SUN4V_SPECFIC
456 word4 PCIERPT_WORD4
457 HDR1 PCIERPT_HDR1
458 HDR2 PCIERPT_HDR2
459
460
461
462dmu_err DMU_ERR_SIZE
463 report_type DMU_ERR_REPORT_TYPE_62
464 fpga_tod DMU_ERR_FPGA_TOD
465 pciehdl DMU_ERR_EHDL
466 pcistick DMU_ERR_STICK
467 cpuver DMU_ERR_CPUVER
468 agentid DMU_ERR_AGENTID
469 mondo_num DMU_ERR_MONDO_NUM
470 dmu_core_and_block_err_status DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS
471 imu_err_log_enable DMU_ERR_IMU_ERR_LOG_ENABLE
472 imu_interrupt_enable DMU_ERR_IMU_INTERRUPT_ENABLE
473 imu_enabled_err_status DMU_ERR_IMU_ENABLED_ERR_STATUS
474 imu_err_status_set DMU_ERR_IMU_ERR_STATUS_SET
475 imu_scs_err_log DMU_ERR_IMU_SCS_ERR_LOG
476 imu_eqs_err_log DMU_ERR_IMU_EQS_ERR_LOG
477 imu_rds_err_log DMU_ERR_IMU_RDS_ERR_LOG
478 mmu_err_log_enable DMU_ERR_MMU_ERR_LOG_ENABLE
479 mmu_intr_enable DMU_ERR_MMU_INTR_ENABLE
480 mmu_intr_status DMU_ERR_MMU_INTR_STATUS
481 mmu_err_status_set DMU_ERR_MMU_ERR_STATUS_SET
482 mmu_translation_fault_address DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS
483 mmu_translation_fault_status DMU_ERR_MMU_TRANSLATION_FAULT_STATUS
484
485
486peu_err PEU_ERR_SIZE
487 report_type PCIE_ERR_REPORT_TYPE_63
488 peu_core_and_block_intr_enable PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE
489 peu_core_and_block_intr_status PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS
490 ilu_err_log_enable PEU_ERR_ILU_ERR_LOG_ENABLE
491 ilu_intr_enable PEU_ERR_ILU_INTR_ENABLE
492 ilu_intr_status PEU_ERR_ILU_INTR_STATUS
493 ilu_err_status_set PEU_ERR_ILU_ERR_STATUS_SET
494 peu_other_event_log_enable PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE
495 peu_other_event_intr_enable PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE
496 peu_other_event_intr_status PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS
497 peu_other_event_status_set PEU_ERR_PEU_OTHER_EVENT_STATUS_SET
498 peu_receive_other_event_header1_log PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG
499 peu_receive_other_event_header2_log PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG
500 peu_transmit_other_event_header1_log PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG
501 peu_transmit_other_event_header2_log PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG
502 peu_ue_log_enable PEU_ERR_PEU_UE_LOG_ENABLE
503 peu_ue_interrupt_enable PEU_ERR_PEU_UE_INTERRUPT_ENABLE
504 peu_ue_status PEU_ERR_PEU_UE_STATUS
505 peu_ue_status_set PEU_ERR_PEU_UE_STATUS_SET
506 peu_receive_ue_header1_log PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG
507 peu_receive_ue_header2_log PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG
508 peu_transmit_ue_header1_log PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG
509 peu_transmit_ue_header2_log PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG
510 peu_ce_log_enable PEU_ERR_PEU_CE_LOG_ENABLE
511 peu_ce_interrupt_enable PEU_ERR_PEU_CE_INTERRUPT_ENABLE
512 peu_ce_interrupt_status PEU_ERR_PEU_CE_INTERRUPT_STATUS
513 peu_ce_status_set PEU_ERR_PEU_CE_STATUS_SET
514 PEU_CXPL_event_error_log_enable PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE
515 PEU_CXPL_event_error_int_enable PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE
516 PEU_CXPL_event_error_int_status PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS
517 PEU_CXPL_event_error_status_set PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET
518
519pci_erpt PCIERPT_SIZE
520 pciepkt PCI_ERPT_PCIEPKT
521 _u PCI_ERPT_U
522 unsent_pkt PCI_UNSENT_PKT
523
524\#define PCIERPT_REPORT_TYPE_62 (PCI_ERPT_U + DMU_ERR_REPORT_TYPE_62)
525\#define PCIERPT_FPGA_TOD (PCI_ERPT_U + DMU_ERR_FPGA_TOD)
526\#define PCIERPT_EHDL (PCI_ERPT_U + DMU_ERR_EHDL)
527\#define PCIERPT_STICK (PCI_ERPT_U + DMU_ERR_STICK)
528\#define PCIERPT_CPUVER (PCI_ERPT_U + DMU_ERR_CPUVER )
529\#define PCIERPT_AGENTID (PCI_ERPT_U + DMU_ERR_AGENTID)
530\#define PCIERPT_MONDO_NUM (PCI_ERPT_U + DMU_ERR_MONDO_NUM)
531\#define PCIERPT_DMU_CORE_AND_BLOCK_ERR_STATUS (PCI_ERPT_U + DMU_ERR_DMU_CORE_AND_BLOCK_ERR_STATUS)
532\#define PCIERPT_IMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_ERR_LOG_ENABLE)
533\#define PCIERPT_IMU_INTERRUPT_ENABLE (PCI_ERPT_U + DMU_ERR_IMU_INTERRUPT_ENABLE)
534\#define PCIERPT_IMU_ENABLED_ERR_STATUS (PCI_ERPT_U + DMU_ERR_IMU_ENABLED_ERR_STATUS)
535\#define PCIERPT_IMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_IMU_ERR_STATUS_SET)
536\#define PCIERPT_IMU_SCS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_SCS_ERR_LOG)
537\#define PCIERPT_IMU_EQS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_EQS_ERR_LOG)
538\#define PCIERPT_IMU_RDS_ERR_LOG (PCI_ERPT_U + DMU_ERR_IMU_RDS_ERR_LOG)
539\#define PCIERPT_MMU_ERR_LOG_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_ERR_LOG_ENABLE)
540\#define PCIERPT_MMU_INTR_ENABLE (PCI_ERPT_U + DMU_ERR_MMU_INTR_ENABLE)
541\#define PCIERPT_MMU_INTR_STATUS (PCI_ERPT_U + DMU_ERR_MMU_INTR_STATUS)
542\#define PCIERPT_MMU_ERR_STATUS_SET (PCI_ERPT_U + DMU_ERR_MMU_ERR_STATUS_SET)
543\#define PCIERPT_MMU_TRANSLATION_FAULT_ADDRESS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_ADDRESS)
544\#define PCIERPT_MMU_TRANSLATION_FAULT_STATUS (PCI_ERPT_U + DMU_ERR_MMU_TRANSLATION_FAULT_STATUS)
545\#define PCIERPT_REPORT_TYPE_63 (PCI_ERPT_U + PCIE_ERR_REPORT_TYPE_63)
546\#define PCIERPT_PEU_CORE_AND_BLOCK_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_ENABLE)
547\#define PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CORE_AND_BLOCK_INTR_STATUS)
548\#define PCIERPT_ILU_ERR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_ERR_LOG_ENABLE)
549\#define PCIERPT_ILU_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_ILU_INTR_ENABLE)
550\#define PCIERPT_ILU_INTR_STATUS (PCI_ERPT_U + PEU_ERR_ILU_INTR_STATUS)
551\#define PCIERPT_ILU_ERR_STATUS_SET (PCI_ERPT_U + PEU_ERR_ILU_ERR_STATUS_SET)
552\#define PCIERPT_PEU_OTHER_EVENT_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_LOG_ENABLE)
553\#define PCIERPT_PEU_OTHER_EVENT_INTR_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_ENABLE)
554\#define PCIERPT_PEU_OTHER_EVENT_INTR_STATUS (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_INTR_STATUS)
555\#define PCIERPT_PEU_OTHER_EVENT_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_OTHER_EVENT_STATUS_SET)
556\#define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER1_LOG)
557\#define PCIERPT_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_OTHER_EVENT_HEADER2_LOG)
558\#define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER1_LOG)
559\#define PCIERPT_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_OTHER_EVENT_HEADER2_LOG)
560\#define PCIERPT_PEU_UE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_LOG_ENABLE)
561\#define PCIERPT_PEU_UE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_UE_INTERRUPT_ENABLE)
562\#define PCIERPT_PEU_UE_STATUS (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS)
563\#define PCIERPT_PEU_UE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_UE_STATUS_SET)
564\#define PCIERPT_PEU_RECEIVE_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER1_LOG)
565\#define PCIERPT_PEU_RECEIVE_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_RECEIVE_UE_HEADER2_LOG)
566\#define PCIERPT_PEU_TRANSMIT_UE_HEADER1_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER1_LOG)
567\#define PCIERPT_PEU_TRANSMIT_UE_HEADER2_LOG (PCI_ERPT_U + PEU_ERR_PEU_TRANSMIT_UE_HEADER2_LOG)
568\#define PCIERPT_PEU_CE_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_LOG_ENABLE)
569\#define PCIERPT_PEU_CE_INTERRUPT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_ENABLE)
570\#define PCIERPT_PEU_CE_INTERRUPT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CE_INTERRUPT_STATUS)
571\#define PCIERPT_PEU_CE_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CE_STATUS_SET)
572\#define PCIERPT_PEU_CXPL_EVENT_ERROR_LOG_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_LOG_ENABLE)
573\#define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_ENABLE (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_ENABLE)
574\#define PCIERPT_PEU_CXPL_EVENT_ERROR_INT_STATUS (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_INT_STATUS)
575\#define PCIERPT_PEU_CXPL_EVENT_ERROR_STATUS_SET (PCI_ERPT_U + PEU_ERR_PEU_CXPL_EVENT_ERROR_STATUS_SET)
576
577ldc_conspkt LDC_CONSPKT_SIZE
578 type LDC_CONS_TYPE
579 size LDC_CONS_SIZE
580 ctrl_msg LDC_CONS_CTRL_MSG
581 payload LDC_CONS_PAYLOAD
582
583console CONSOLE_SIZE
584 type CONS_TYPE
585 vintr_arg CONS_VINTR_ARG
586 svcp CONS_SVCP
587 pending CONS_PENDING
588 uartbase CONS_UARTBASE
589 chars_avail CONS_CHARS_AVAIL
590 tbsy CONS_TBSY
591 status CONS_STATUS
592 endpt CONS_ENDPT
593 in_head CONS_INHEAD
594 in_tail CONS_INTAIL
595 vintr_mapreg CONS_VINTR_MAPREG
596 scr_orig_head CONS_SCR_ORIG_HEAD
597 scr_orig_tail CONS_SCR_ORIG_TAIL
598 in_buf CONS_INBUF
599
600hvdisk HVDISK_SIZE
601 pa DISK_PA
602 size DISK_SIZE
603
604ldc_endpoint LDC_ENDPOINT_SIZE
605 is_live LDC_IS_LIVE
606 is_private LDC_IS_PRIVATE
607 svc_id LDC_IS_SVC_ID
608 rx_updated LDC_RX_UPDATED
609 txq_full LDC_TXQ_FULL
610 tx_block_flag LDC_TX_BLOCK_FLAG
611 tx_qbase_ra LDC_TX_QBASE_RA
612 tx_qbase_pa LDC_TX_QBASE_PA
613 tx_qsize LDC_TX_QSIZE
614 tx_qhead LDC_TX_QHEAD
615 tx_qtail LDC_TX_QTAIL
616 tx_mapreg LDC_TX_MAPREG
617 tx_cb LDC_TX_CB
618 tx_cbarg LDC_TX_CBARG
619 rx_qbase_ra LDC_RX_QBASE_RA
620 rx_qbase_pa LDC_RX_QBASE_PA
621 rx_qsize LDC_RX_QSIZE
622 rx_qhead LDC_RX_QHEAD
623 rx_qtail LDC_RX_QTAIL
624 rx_mapreg LDC_RX_MAPREG
625 rx_vintr_cookie LDC_RX_VINTR_COOKIE
626 rx_cb LDC_RX_CB
627 rx_cbarg LDC_RX_CBARG
628 target_type LDC_TARGET_TYPE
629 target_guest LDC_TARGET_GUEST
630 target_channel LDC_TARGET_CHANNEL
631 map_table_ra LDC_MAP_TABLE_RA
632 map_table_pa LDC_MAP_TABLE_PA
633 map_table_nentries LDC_MAP_TABLE_NENTRIES
634 map_table_sz LDC_MAP_TABLE_SZ
635
636
637version VERSION_SIZE
638 version_num VERSION_NUM
639 verptr VERSION_PTR
640
641\#define VERSION_MAJOR (VERSION_NUM+MAJOR_OFF)
642\#define VERSION_MINOR (VERSION_NUM+MINOR_OFF)
643
644ldc_mapreg LDC_MAPREG_SIZE
645 state LDC_MAPREG_STATE
646 valid LDC_MAPREG_VALID
647 ino LDC_MAPREG_INO
648 pcpup LDC_MAPREG_CPUP
649 cookie LDC_MAPREG_COOKIE
650 endpoint LDC_MAPREG_ENDPOINT
651
652guest_watchdog
653 ticks WATCHDOG_TICKS
654
655ldc_ino2endpoint LDC_I2E_SIZE
656 endpointp LDC_I2E_ENDPOINT
657 mapregp LDC_I2E_MAPREG
658
659sp_ldc_endpoint SP_LDC_ENDPOINT_SIZE
660 channel_idx LDC_CHANNEL_IDX
661 is_live SP_LDC_IS_LIVE
662 target_type SP_LDC_TARGET_TYPE
663 tx_qd_pa SP_LDC_TX_QD_PA
664 rx_qd_pa SP_LDC_RX_QD_PA
665 tx_q_data_pa SP_LDC_TX_Q_DATA_PA
666 rx_q_data_pa SP_LDC_RX_Q_DATA_PA
667 target_guest SP_LDC_TARGET_GUEST
668 target_channel SP_LDC_TARGET_CHANNEL
669 tx_lock SP_LDC_TX_LOCK
670 rx_lock SP_LDC_RX_LOCK
671 tx_scr_txhead SP_LDC_TX_SCR_TXHEAD
672 tx_scr_txtail SP_LDC_TX_SCR_TXTAIL
673 tx_scr_txsize SP_LDC_TX_SCR_TXSIZE
674 tx_scr_tx_qpa SP_LDC_TX_SCR_TX_QPA
675 tx_scr_rxhead SP_LDC_TX_SCR_RXHEAD
676 tx_scr_rxtail SP_LDC_TX_SCR_RXTAIL
677 tx_scr_rxsize SP_LDC_TX_SCR_RXSIZE
678 tx_scr_rx_qpa SP_LDC_TX_SCR_RX_QPA
679 tx_scr_rx_qdpa SP_LDC_TX_SCR_RX_QDPA
680 tx_scr_target SP_LDC_TX_SCR_TARGET
681 rx_scr_txhead SP_LDC_RX_SCR_TXHEAD
682 rx_scr_txtail SP_LDC_RX_SCR_TXTAIL
683 rx_scr_txsize SP_LDC_RX_SCR_TXSIZE
684 rx_scr_tx_qpa SP_LDC_RX_SCR_TX_QPA
685 rx_scr_tx_qdpa SP_LDC_RX_SCR_TX_QDPA
686 rx_scr_rxhead SP_LDC_RX_SCR_RXHEAD
687 rx_scr_rxtail SP_LDC_RX_SCR_RXTAIL
688 rx_scr_rxsize SP_LDC_RX_SCR_RXSIZE
689 rx_scr_rx_qpa SP_LDC_RX_SCR_RX_QPA
690 rx_scr_target SP_LDC_RX_SCR_TARGET
691 rx_scr_pkt SP_LDC_RX_SCR_PKT
692
693
694sram_ldc_qentry SRAM_LDC_QENTRY_SIZE
695 pkt_data SRAM_LDC_PKT_DATA
696
697sram_ldc_qd SRAM_LDC_QD_SIZE
698 head SRAM_LDC_HEAD
699 tail SRAM_LDC_TAIL
700 state SRAM_LDC_STATE
701 state_updated SRAM_LDC_STATE_UPDATED
702 state_notify SRAM_LDC_STATE_NOTIFY
703
704ldc_mapin LDC_MAPIN_SIZE
705 local_endpoint LDC_MI_LOCAL_ENDPOINT
706 pg_size LDC_MI_PG_SIZE
707 perms LDC_MI_PERMS
708 map_table_idx LDC_MI_MAP_TABLE_IDX
709 pa LDC_MI_PA
710 va LDC_MI_VA
711 va_ctx LDC_MI_VA_CTX
712 io_va LDC_MI_IO_VA
713 mmu_map LDC_MI_MMU_MAP
714
715\#define LDC_MI_NEXT_IDX 0 /* clobber 1st word when free */
716\#define MIE_VA_MMU_SHIFT 0
717\#define MIE_RA_MMU_SHIFT 8
718\#define MIE_IO_MMU_SHIFT 16
719\ offsets for a big-endian architecture
720\#define LDC_MI_VA_MMU_MAP (LDC_MI_MMU_MAP + 7)
721\#define LDC_MI_RA_MMU_MAP (LDC_MI_MMU_MAP + 6)
722\#define LDC_MI_IO_MMU_MAP (LDC_MI_MMU_MAP + 5)
723
724guest_console_queues GUEST_CONS_QUEUES_SIZE
725 cons_rxq GUEST_CONS_RXQ
726 cons_txq GUEST_CONS_TXQ
727
728ra2pa_segment RA2PA_SEGMENT_SIZE
729 base RA2PA_SEGMENT_BASE
730 limit RA2PA_SEGMENT_LIMIT
731 offset RA2PA_SEGMENT_OFFSET
732 flags RA2PA_SEGMENT_FLAGS
733
734guest GUEST_SIZE
735 guestid GUEST_GID
736 ra2pa_segment GUEST_RA2PA_SEGMENT
737 configp GUEST_CONFIGP
738 state GUEST_STATE
739 state_lock GUEST_STATE_LOCK
740 soft_state GUEST_SOFT_STATE
741 soft_state_str GUEST_SOFT_STATE_STR
742 soft_state_lock GUEST_SOFT_STATE_LOCK
743 real_base GUEST_REAL_BASE
744 real_limit GUEST_REAL_LIMIT
745 mem_offset GUEST_MEM_OFFSET
746 console GUEST_CONSOLE
747 tod_offset GUEST_TOD_OFFSET
748 ttrace_freeze GUEST_TTRACE_FRZ
749 cpup GUEST_CPUP
750 vcpus GUEST_VCPUS
751 cpuset GUEST_CPUSET
752 perm_mappings_lock GUEST_PERM_MAPPINGS_LOCK
753 perm_mappings_count GUEST_PERM_MAPPINGS_COUNT
754 perm_mappings GUEST_PERM_MAPPINGS GUEST_PERM_MAPPINGS_INCR
755 api_groups GUEST_API_GROUPS
756 hcall_table GUEST_HCALL_TABLE
757 dev2inst GUEST_DEV2INST
758 vino2inst GUEST_VINO2INST
759 vdev_state GUEST_VDEV_STATE
760 md_pa GUEST_MD_PA
761 md_size GUEST_MD_SIZE
762 maus GUEST_MAUS GUEST_MAUS_INCR
763 cwqs GUEST_CWQS GUEST_CWQS_INCR
764 dumpbuf_pa GUEST_DUMPBUF_PA
765 dumpbuf_ra GUEST_DUMPBUF_RA
766 dumpbuf_size GUEST_DUMPBUF_SIZE
767 entry GUEST_ENTRY
768 rom_base GUEST_ROM_BASE
769 rom_size GUEST_ROM_SIZE
770 perfreg_accessible GUEST_PERFREG_ACCESSIBLE
771 diagpriv GUEST_DIAGPRIV
772 reset_reason GUEST_RESET_REASON
773 perfreght_accessible GUEST_PERFREGHT_ACCESSIBLE
774 rng_ctl_accessible GUEST_RNG_CTL_ACCESSIBLE
775 disk GUEST_DISK
776 watchdog GUEST_WATCHDOG
777 ldc_mapin_free_idx GUEST_LDC_MAPIN_FREE_IDX
778 ldc_mapin_basera GUEST_LDC_MAPIN_BASERA
779 ldc_max_channel_idx GUEST_LDC_MAX_CHANNEL_IDX
780 ldc_mapin_size GUEST_LDC_MAPIN_SIZE
781 ldc_endpoint GUEST_LDC_ENDPOINT
782 ldc_mapin GUEST_LDC_MAPIN
783 ldc_ino2endpoint GUEST_LDC_I2E
784 start_stick GUEST_START_STICK
785 util GUEST_UTIL
786 async_busy GUEST_ASYNC_BUSY
787 async_lock GUEST_ASYNC_LOCK
788 async_buf GUEST_ASYNC_BUF
789 guest_m GUEST_MGUEST
790
791guest_util GUEST_UTIL_SIZE
792 stick_last GUTIL_STICK_LAST
793 stopped_cycles GUTIL_STOPPED_CYCLES
794
795hvctl_res_status HVCTL_RES_STATUS_SIZE
796 res HVCTL_RES_STATUS_RES
797 resid HVCTL_RES_STATUS_RESID
798 infoid HVCTL_RES_STATUS_INFOID
799 code HVCTL_RES_STATUS_CODE
800 data HVCTL_RES_STATUS_DATA
801
802rs_guest_soft_state RS_GUEST_SOFT_STATE_SIZE
803 soft_state RS_GUEST_SOFT_STATE
804 soft_state_str RS_GUEST_SOFT_STATE_STR
805
806
807devopsvec DEVOPSVEC_SIZE
808 devino2vino DEVOPSVEC_DEVINO2VINO
809 mondo_receive DEVOPSVEC_MONDO_RECEIVE
810 getvalid DEVOPSVEC_GETVALID
811 setvalid DEVOPSVEC_SETVALID
812 settarget DEVOPSVEC_SETTARGET
813 gettarget DEVOPSVEC_GETTARGET
814 getstate DEVOPSVEC_GETSTATE
815 setstate DEVOPSVEC_SETSTATE
816 map DEVOPSVEC_MAP
817 map_v2 DEVOPSVEC_MAP_V2
818 getmap DEVOPSVEC_GETMAP
819 getmap_v2 DEVOPSVEC_GETMAP_V2
820 unmap DEVOPSVEC_UNMAP
821 getbypass DEVOPSVEC_GETBYPASS
822 configget DEVOPSVEC_CONFIGGET
823 configput DEVOPSVEC_CONFIGPUT
824 peek DEVOPSVEC_IOPEEK
825 poke DEVOPSVEC_IOPOKE
826 dmasync DEVOPSVEC_DMASYNC
827 msiq_conf DEVOPSVEC_MSIQ_CONF
828 msiq_info DEVOPSVEC_MSIQ_INFO
829 msiq_getvalid DEVOPSVEC_MSIQ_GETVALID
830 msiq_setvalid DEVOPSVEC_MSIQ_SETVALID
831 msiq_getstate DEVOPSVEC_MSIQ_GETSTATE
832 msiq_setstate DEVOPSVEC_MSIQ_SETSTATE
833 msiq_gethead DEVOPSVEC_MSIQ_GETHEAD
834 msiq_sethead DEVOPSVEC_MSIQ_SETHEAD
835 msiq_gettail DEVOPSVEC_MSIQ_GETTAIL
836 msi_getvalid DEVOPSVEC_MSI_GETVALID
837 msi_setvalid DEVOPSVEC_MSI_SETVALID
838 msi_getstate DEVOPSVEC_MSI_GETSTATE
839 msi_setstate DEVOPSVEC_MSI_SETSTATE
840 msi_getmsiq DEVOPSVEC_MSI_GETMSIQ
841 msi_setmsiq DEVOPSVEC_MSI_SETMSIQ
842 msi_msg_getmsiq DEVOPSVEC_MSI_MSG_GETMSIQ
843 msi_msg_setmsiq DEVOPSVEC_MSI_MSG_SETMSIQ
844 msi_msg_getvalid DEVOPSVEC_MSI_MSG_GETVALID
845 msi_msg_setvalid DEVOPSVEC_MSI_MSG_SETVALID
846 getperfreg DEVOPSVEC_GETPERFREG
847 setperfreg DEVOPSVEC_SETPERFREG
848 vgetcookie DEVOPSVEC_VGETCOOKIE
849 vsetcookie DEVOPSVEC_VSETCOOKIE
850 vgetvalid DEVOPSVEC_VGETVALID
851 vsetvalid DEVOPSVEC_VSETVALID
852 vgettarget DEVOPSVEC_VGETTARGET
853 vsettarget DEVOPSVEC_VSETTARGET
854 vgetstate DEVOPSVEC_VGETSTATE
855 vsetstate DEVOPSVEC_VSETSTATE
856
857
858vino2inst VINO2INST_SIZE
859 vino VINO2INST_VINO
860
861piu_cookie PIU_COOKIE_SIZE
862 handle PIU_COOKIE_HANDLE
863 ncu PIU_COOKIE_NCU
864 pcie PIU_COOKIE_PCIE
865 cfg PIU_COOKIE_CFG
866 perfregs PIU_COOKIE_PERFREGS
867 iotsb0 PIU_COOKIE_IOTSB0
868 iotsb1 PIU_COOKIE_IOTSB1
869 intclr PIU_COOKIE_INTCLR
870 intmap PIU_COOKIE_INTMAP
871 virtual_intmap PIU_COOKIE_VIRTUAL_INTMAP
872 err_lock PIU_COOKIE_ERR_LOCK
873 err_lock_counter PIU_COOKIE_ERR_LOCK_COUNTER
874 tlu_oe_status PIU_COOKIE_OE_STATUS
875 inomax PIU_COOKIE_INOMAX
876 vino PIU_COOKIE_VINO
877 mmuflush PIU_COOKIE_MMUFLUSH
878 eqctlset PIU_COOKIE_EQCTLSET
879 eqctlclr PIU_COOKIE_EQCTLCLR
880 eqstate PIU_COOKIE_EQSTATE
881 eqtail PIU_COOKIE_EQTAIL
882 eqhead PIU_COOKIE_EQHEAD
883 msimap PIU_COOKIE_MSIMAP
884 msiclr PIU_COOKIE_MSICLR
885 msgmap PIU_COOKIE_MSGMAP
886 msieqbase PIU_COOKIE_MSIEQBASE
887 msieqs PIU_COOKIE_MSIEQS
888 msicookie PIU_COOKIE_MSICOOKIE
889 errcookie PIU_COOKIE_ERRCOOKIE
890 dmu_erpt PIU_COOKIE_DMU_ERPT
891 peu_erpt PIU_COOKIE_PEU_ERPT
892 blacklist PIU_COOKIE_BLACKLIST
893
894piu_msieq PIU_MSIEQ_SIZE
895 eqmask PIU_MSIEQ_EQMASK
896 base PIU_MSIEQ_BASE
897 guest PIU_MSIEQ_GUEST
898 word0 PIU_MSIEQ_WORD0
899 word1 PIU_MSIEQ_WORD1
900
901piu_msi_cookie PIU_MSI_COOKIE_SIZE
902 piu PIU_MSI_COOKIE_PIU
903 eq PIU_MSI_COOKIE_EQ
904
905piu_err_cookie PIU_ERR_COOKIE_SIZE
906 piu PIU_ERR_COOKIE_PIU
907 state PIU_ERR_COOKIE_STATE
908
909vdev_state VDEV_STATE_SIZE
910 handle VDEV_STATE_HANDLE
911 mapreg VDEV_STATE_MAPREG
912 inomax VDEV_STATE_INOMAX
913 vinobase VDEV_STATE_VINOBASE
914
915svc_link
916 size SVC_LINK_SIZE
917 pa SVC_LINK_PA
918 next SVC_LINK_NEXT
919
920svc_callback
921 rx SVC_CALLBACK_RX
922 tx SVC_CALLBACK_TX
923 cookie SVC_CALLBACK_COOKIE
924
925svc_ctrl SVC_CTRL_SIZE
926 xid SVC_CTRL_XID
927 sid SVC_CTRL_SID
928 ino SVC_CTRL_INO
929 mtu SVC_CTRL_MTU
930 config SVC_CTRL_CONFIG
931 state SVC_CTRL_STATE
932 intr_cookie SVC_CTRL_INTR_COOKIE
933 lock SVC_CTRL_LOCK
934 dcount SVC_CTRL_COUNT
935 dstate SVC_CTRL_DSTATE
936 callback SVC_CTRL_CALLBACK
937 link SVC_CTRL_LINK
938 recv SVC_CTRL_RECV
939 send SVC_CTRL_SEND
940
941hv_svc_data HV_SVC_DATA_SIZE
942 rxbase HV_SVC_DATA_RXBASE
943 txbase HV_SVC_DATA_TXBASE
944 rxchannel HV_SVC_DATA_RXCHANNEL
945 txchannel HV_SVC_DATA_TXCHANNEL
946 scr HV_SVC_DATA_SCR
947 num_svcs HV_SVC_DATA_NUM_SVCS
948 sendbusy HV_SVC_DATA_SENDBUSY
949 sendh HV_SVC_DATA_SENDH
950 sendt HV_SVC_DATA_SENDT
951 senddh HV_SVC_DATA_SENDDH
952 senddt HV_SVC_DATA_SENDDT
953 lock HV_SVC_DATA_LOCK
954 svcs HV_SVC_DATA_SVC
955
956svc_pkt SVC_PKT_SIZE
957 xid SVC_PKT_XID
958 sid SVC_PKT_SID
959 sum SVC_PKT_SUM
960
961vdev_mapreg MAPREG_SIZE MAPREG_SHIFT
962 state MAPREG_STATE
963 valid MAPREG_VALID
964 pcpu MAPREG_PCPU
965 vcpu MAPREG_VCPU
966 ino MAPREG_INO
967 data0 MAPREG_DATA0
968 devcookie MAPREG_DEVCOOKIE
969 getstate MAPREG_GETSTATE
970 setstate MAPREG_SETSTATE
971
972md_header DTHDR_SIZE
973 transport_version DTHDR_VER
974 node_blk_sz DTHDR_NODESZ
975 name_blk_sz DTHDR_NAMES
976 data_blk_sz DTHDR_DATA
977
978md_element DTNODE_SIZE
979 tag DTNODE_TAG
980 d DTNODE_DATA
981
982trapglobals TRAPGLOBALS_SIZE TRAPGLOBALS_SHIFT
983
984trapstate TRAPSTATE_SIZE
985 htstate TRAPSTATE_HTSTATE
986 tstate TRAPSTATE_TSTATE
987 tt TRAPSTATE_TT
988 tpc TRAPSTATE_TPC
989 tnpc TRAPSTATE_TNPC
990
991dbgerror_payload DBGERROR_PAYLOAD_SIZE
992 data DBGERROR_DATA
993
994dbgerror DBGERROR_SIZE
995 error_svch DBGERROR_ERROR_SVCH
996 payload DBGERROR_PAYLOAD
997
998devinst DEVINST_SIZE DEVINST_SIZE_SHIFT
999 cookie DEVINST_COOKIE
1000 ops DEVINST_OPS
1001
1002erpt_svc_pkt ERPT_SVC_PKT_SIZE
1003 addr ERPT_PKT_ADDR
1004 size ERPT_PKT_SIZE
1005
1006mau_queue MAU_QUEUE_SIZE
1007 mq_lock MQ_LOCK
1008 mq_state MQ_STATE
1009 mq_busy MQ_BUSY
1010 mq_base MQ_BASE
1011 mq_base_ra MQ_BASE_RA
1012 mq_end MQ_END
1013 mq_head MQ_HEAD
1014 mq_head_marker MQ_HEAD_MARKER
1015 mq_tail MQ_TAIL
1016 mq_nentries MQ_NENTRIES
1017 mq_cpu_pid MQ_CPU_PID
1018
1019cwq_queue CWQ_QUEUE_SIZE
1020 cq_lock CQ_LOCK
1021 cq_state CQ_STATE
1022 cq_busy CQ_BUSY
1023 cq_dr_base_ra CQ_DR_BASE_RA
1024 cq_dr_base CQ_DR_BASE
1025 cq_dr_last CQ_DR_LAST
1026 cq_dr_head CQ_DR_HEAD
1027 cq_dr_tail CQ_DR_TAIL
1028 cq_base CQ_BASE
1029 cq_last CQ_LAST
1030 cq_head CQ_HEAD
1031 cq_head_marker CQ_HEAD_MARKER
1032 cq_tail CQ_TAIL
1033 cq_nentries CQ_NENTRIES
1034 cq_cpu_pid CQ_CPU_PID
1035 cq_scr1 CQ_SCR1
1036 cq_scr2 CQ_SCR2
1037 cq_scr3 CQ_SCR3
1038 cq_dr_hv_offset CQ_DR_HV_OFFSET
1039 cq_hv_cws CQ_HV_CWS
1040
1041ncs_hvdesc NCS_HVDESC_SIZE NCS_HVDESC_SHIFT
1042 nhd_state NHD_STATE
1043 nhd_type NHD_TYPE
1044 nhd_regs NHD_REGS
1045 nhd_errstatus NHD_ERRSTATUS
1046
1047ma_regs MA_REGS_SIZE
1048 mr_ctl MR_CTL
1049 mr_mpa MR_MPA
1050 mr_ma MR_MA
1051 mr_np MR_NP
1052
1053ncs_qconf_arg NCS_QCONF_ARG_SIZE
1054 nq_mid NQ_MID
1055 nq_base NQ_BASE
1056 nq_end NQ_END
1057 nq_nentries NQ_NENTRIES
1058
1059ncs_qtail_update_arg NCS_QTAIL_UPDATE_ARG_SIZE
1060 nu_mid NU_MID
1061 nu_tail NU_TAIL
1062 nu_syncflag NU_SYNCFLAG
1063
1064cwq_cw_ret CWQ_CW_RET_SIZE
1065 cw_ret_dst_addr CW_RET_DST_ADDR
1066 cw_ret_csr CW_RET_CSR
1067
1068cwq_cw CWQ_CW_SIZE CWQ_CW_SHIFT
1069 cw_ctlbits CW_CTLBITS
1070 cw_src_addr CW_SRC_ADDR
1071 cw_auth_key_addr CW_AUTH_KEY_ADDR
1072 cw_auth_iv_addr CW_AUTH_IV_ADDR
1073 cw_final_auth_state_addr CW_FINAL_AUTH_STATE_ADDR
1074 cw_enc_key_addr CW_ENC_KEY_ADDR
1075 cw_enc_iv_addr CW_ENC_IV_ADDR
1076 cw_ret CW_RET
1077
1078\#define CW_DST_ADDR (CW_RET + CW_RET_DST_ADDR)
1079\#define CW_CSR (CW_RET + CW_RET_DST_ADDR)
1080
1081crypto_intr CRYPTO_INTR_SIZE
1082 ci_cookie CI_COOKIE
1083 ci_active CI_ACTIVE
1084 ci_data CI_DATA
1085
1086rng_ctlregs RNG_CTLREGS_SIZE
1087 reg0 RNG_CTLREGS_REG0
1088 reg1 RNG_CTLREGS_REG1
1089 reg2 RNG_CTLREGS_REG2
1090 reg3 RNG_CTLREGS_REG3
1091
1092rng_ctldata RNG_CTLDATA_SIZE
1093 rc_regs RNG_CTLDATA_REGS
1094 rc_state RNG_CTLDATA_STATE
1095 rc_guestid RNG_CTLDATA_GUESTID
1096 rc_readytime RNG_CTLDATA_READYTIME
1097
1098svccn_packet SVCCN_PKT_SIZE
1099 type SVCCN_PKT_TYPE
1100 len SVCCN_PKT_LEN
1101 data SVCCN_PKT_DATA
1102
1103vbsc_ctrl_pkt VBSC_CTRL_PKT_SIZE
1104 cmd VBSC_PKT_CMD
1105 arg0 VBSC_PKT_ARG0
1106 arg1 VBSC_PKT_ARG1
1107 arg2 VBSC_PKT_ARG2
1108
1109callback CB_SIZE
1110 tick CB_TICK
1111 handler CB_HANDLER
1112 arg0 CB_ARG0
1113 arg1 CB_ARG1
1114
1115cyclic CY_SIZE
1116 t0 CY_T0
1117 cb CY_CB
1118 tick CY_TICK
1119 handler CY_HANDLER
1120 arg0 CY_ARG0
1121 arg1 CY_ARG1
1122
1123\#define STRAND_CY_T0 (STRAND_CYCLIC + CY_T0)
1124\#define STRAND_CY_CB (STRAND_CYCLIC + CY_CB)
1125\#define STRAND_CY_TICK (STRAND_CYCLIC + CY_TICK)
1126\#define STRAND_CY_HANDLER (STRAND_CYCLIC + CY_HANDLER)
1127\#define STRAND_CY_ARG0 (STRAND_CYCLIC + CY_ARG0)
1128\#define STRAND_CY_ARG1 (STRAND_CYCLIC + CY_ARG1)
1129\#define STRAND_CY_CB_TICK (STRAND_CYCLIC + CY_CB + CB_TICK)
1130\#define STRAND_CY_CB_HANDLER (STRAND_CYCLIC + CY_CB + CB_HANDLER)
1131\#define STRAND_CY_CB_ARG0 (STRAND_CYCLIC + CY_CB + CB_ARG0)
1132\#define STRAND_CY_CB_ARG1 (STRAND_CYCLIC + CY_CB + CB_ARG1)
1133\#define CB_LAST ((N_CB - 1) * CB_SIZE)
1134\#define STRAND_CY_CB_LAST_TICK (STRAND_CY_CB_TICK + CB_LAST)
1135
1136error_table_entry ERROR_TABLE_ENTRY_SIZE
1137 err_name ERR_NAME
1138 err_report_fcn ERR_REPORT_FCN
1139 err_guest_report_fcn ERR_GUEST_REPORT_FCN
1140 err_correct_fcn ERR_CORRECT_FCN
1141 err_storm_fcn ERR_STORM_FCN
1142 err_print_fcn ERR_PRINT_FCN
1143 err_flags ERR_FLAGS
1144 err_sun4v_rprt_type ERR_SUN4V_RPRT_TYPE
1145 err_sun4v_edesc ERR_SUN4V_EDESC
1146 err_report_size ERR_REPORT_SIZE
1147
1148
1149err_way ERR_WAY_SIZE
1150 err_tag_and_ecc ERR_WAY_TAG_AND_ECC
1151 err_data_and_ecc ERR_WAY_DATA_AND_ECC
1152
1153err_l2 ERR_L2_SIZE
1154 err_vdbits ERR_L2_VDBITS
1155 err_uabits ERR_L2_UABITS
1156 err_ways ERR_L2_WAYS
1157 dram_contents ERR_DRAM_CONTENTS
1158
1159err_tlb ERR_TLB_SIZE
1160 err_tlb_tag ERR_TLB_TAG
1161 err_tlb_data ERR_TLB_DATA
1162
1163
1164err_icache_way ERR_ICACHE_WAY_SIZE
1165 err_icache_instr ERR_ICACHE_WAY_INSTR
1166 err_icache_tag ERR_ICACHE_WAY_TAG
1167
1168err_icache ERR_ICACHE_SIZE
1169 err_icache_way ERR_ICACHE_WAY
1170
1171err_dcache_way ERR_DCACHE_WAY_SIZE
1172 err_dcache_data ERR_DCACHE_WAY_DATA
1173 err_dcache_tag ERR_DCACHE_WAY_TAG
1174
1175err_dcache ERR_DCACHE_SIZE
1176 err_dcache_way ERR_DCACHE_WAY
1177
1178err_ssi ERR_SSI_SIZE
1179 err_ssi_timeout ERR_SSI_TIMEOUT
1180 err_ssi_log ERR_SSI_LOG
1181
1182err_stb ERR_STB_SIZE
1183 err_stb_data ERR_STB_DATA
1184 err_stb_data_ecc ERR_STB_DATA_ECC
1185 err_stb_parity ERR_STB_PARITY
1186 err_stb_marks ERR_STB_MARKS
1187 err_stb_curr_ptr ERR_STB_CURR_PTR
1188
1189err_scratchpad ERR_SCRATCHPAD_SIZE
1190 err_scratchpad_data ERR_SCRATCHPAD_DATA
1191 err_scratchpad_ecc ERR_SCRATCHPAD_ECC
1192
1193err_tca ERR_TCA_SIZE
1194 err_tca_data ERR_TCA_DATA
1195 err_tca_ecc ERR_TCA_ECC
1196
1197err_reg ERR_REG_SIZE
1198 err_reg_ecc ERR_REG_ECC
1199
1200err_tsa ERR_TSA_SIZE
1201 err_tsa_ecc ERR_TSA_ECC
1202 err_tsa_tl ERR_TSA_TL
1203 err_tsa_tt ERR_TSA_TT
1204 err_tsa_tstate ERR_TSA_TSTATE
1205 err_tsa_htstate ERR_TSA_HTSTATE
1206 err_tsa_tpc ERR_TSA_TPC
1207 err_tsa_tnpc ERR_TSA_TNPC
1208 err_tsa_cpu_mondo_qhead ERR_TSA_CPU_MONDO_QHEAD
1209 err_tsa_cpu_mondo_qtail ERR_TSA_CPU_MONDO_QTAIL
1210 err_tsa_dev_mondo_qhead ERR_TSA_DEV_MONDO_QHEAD
1211 err_tsa_dev_mondo_qtail ERR_TSA_DEV_MONDO_QTAIL
1212 err_tsa_res_err_qhead ERR_TSA_ERR_RES_QHEAD
1213 err_tsa_res_err_qtail ERR_TSA_ERR_RES_QTAIL
1214 err_tsa_nonres_err_qhead ERR_TSA_ERR_NONRES_QHEAD
1215 err_tsa_nonres_err_qtail ERR_TSA_ERR_NONRES_QTAIL
1216
1217err_mmu_regs ERR_MMU_ERR_REGS_SIZE
1218 err_mmu_parity ERR_MMU_PARITY
1219 err_mmu_tsb_cfg_ctx0 ERR_MMU_TSB_CFG_CTX0
1220 err_mmu_tsb_cfg_ctxnz ERR_MMU_TSB_CFG_CTXNZ
1221 err_mmu_real_range ERR_MMU_REAL_RANGE
1222 err_mmu_phys_offset ERR_MMU_PHYS_OFFSET
1223
1224err_mamu ERR_MAMU_SIZE
1225 err_ma_pa ERR_MA_PA
1226 err_ma_addr ERR_MA_ADDR
1227 err_ma_np ERR_MA_NP
1228 err_ma_ctl ERR_MA_CTL
1229 err_ma_sync ERR_MA_SYNC
1230
1231err_trap_regs ERR_TRAP_REGS_SIZE
1232 err_tt ERR_TT
1233 err_tpc ERR_TPC
1234 err_tnpc ERR_TNPC
1235 err_tstate ERR_TSTATE
1236 err_htstate ERR_HTSTATE
1237
1238err_soc ERR_SOC_SIZE
1239 err_soc_esr ERR_SOC_ESR
1240 err_soc_eler ERR_SOC_ELER
1241 err_soc_eier ERR_SOC_EIER
1242 err_soc_vcid ERR_SOC_VCID
1243 err_soc_feer ERR_SOC_FEER
1244 err_soc_pesr ERR_SOC_PESR
1245 err_soc_eir ERR_SOC_EIR
1246 err_soc_sii_synd ERR_SOC_SII_SYND
1247 err_soc_ncu_synd ERR_SOC_NCU_SYND
1248
1249err_diag_data ERR_DIAG_DATA_SIZE
1250 err_dtlb ERR_DIAG_DATA_DTLB
1251 err_itlb ERR_DIAG_DATA_ITLB
1252 err_icache ERR_DIAG_DATA_ICACHE
1253 err_dcache ERR_DIAG_DATA_DCACHE
1254 err_ssi_info ERR_DIAG_DATA_SSI_INFO
1255 err_stb ERR_DIAG_DATA_STB
1256 err_scratchpad ERR_DIAG_DATA_SCRATCHPAD
1257 err_tsa ERR_DIAG_DATA_TSA
1258 err_mmu_regs ERR_DIAG_DATA_MMU_REGS
1259 err_mamu ERR_DIAG_DATA_MAMU
1260 err_soc ERR_DIAG_DATA_SOC
1261 err_tca ERR_DIAG_DATA_TCA
1262 err_reg ERR_DIAG_DATA_REG
1263 err_l2_cache ERR_DIAG_DATA_L2_CACHE
1264 err_reg_info ERR_DIAG_DATA_REG_INFO
1265 err_trap_registers ERR_DIAG_DATA_TRAP_REGS
1266
1267err_abort_data ERR_ABORT_DATA_SIZE
1268 err_version ERR_ABORT_VERSION
1269 err_pc ERR_ABORT_PC
1270 err_cwp ERR_ABORT_CWP
1271 err_trap_registers ERR_ABORT_TRAP_REGS
1272 err_globals ERR_ABORT_GLOBAL_REGS
1273 err_registers ERR_ABORT_REG_WINDOWS
1274 err_config ERR_ABORT_CONFIG
1275
1276
1277err_diag_buf ERR_DIAG_BUF_SIZE
1278 err_sparc_isfsr ERR_DIAG_BUF_SPARC_ISFSR
1279 err_sparc_dsfsr ERR_DIAG_BUF_SPARC_DSFSR
1280 err_sparc_dsfar ERR_DIAG_BUF_SPARC_DSFAR
1281 err_sparc_desr ERR_DIAG_BUF_SPARC_DESR
1282 err_sparc_dfesr ERR_DIAG_BUF_SPARC_DFESR
1283 err_l2_cache_esr ERR_DIAG_BUF_L2_CACHE_ESR
1284 err_l2_cache_ear ERR_DIAG_BUF_L2_CACHE_EAR
1285 err_l2_cache_nd ERR_DIAG_BUF_L2_CACHE_ND
1286 err_dram_esr ERR_DIAG_BUF_DRAM_ESR
1287 err_dram_ear ERR_DIAG_BUF_DRAM_EAR
1288 err_dram_loc ERR_DIAG_BUF_DRAM_LOC
1289 err_dram_cntr ERR_DIAG_BUF_DRAM_CTR
1290 err_dram_fbd ERR_DIAG_BUF_DRAM_FBD
1291 err_dram_retry ERR_DIAG_BUF_DRAM_RETRY
1292 err_l2_bank ERR_DIAG_L2_BANK
1293 err_l2_line_state ERR_DIAG_L2_LINE_STATE
1294 err_l2_pa ERR_DIAG_L2_PA
1295 err_diag_data ERR_DIAG_BUF_DIAG_DATA
1296 err_report_in_use ERR_DIAG_BUF_RPRT_IN_USE
1297 err_report_size ERR_DIAG_BUF_RPRT_SIZE
1298
1299sun4v_cpu_erpt CPU_SUN4V_RPRT_SIZE
1300 g_ehdl CPU_SUN4V_RPRT_G_EHDL
1301 g_stick CPU_SUN4V_RPRT_G_STICK
1302 edesc CPU_SUN4V_RPRT_EDESC
1303 attr CPU_SUN4V_RPRT_ATTR
1304 addr CPU_SUN4V_RPRT_ADDR
1305 sz CPU_SUN4V_RPRT_SZ
1306 g_cpuid CPU_SUN4V_RPRT_G_CPUID
1307 g_secs CPU_SUN4V_RPRT_G_SECS
1308 asi CPU_SUN4V_RPRT_ASI
1309 reg CPU_SUN4V_RPRT_REG
1310 word5 CPU_SUN4V_RPRT_WORD5
1311 word6 CPU_SUN4V_RPRT_WORD6
1312 word7 CPU_SUN4V_RPRT_WORD7
1313 word8 CPU_SUN4V_RPRT_WORD8
1314
1315\#define ESUN4V_G_EHDL CPU_SUN4V_RPRT_G_EHDL
1316\#define ESUN4V_G_STICK CPU_SUN4V_RPRT_G_STICK
1317\#define ESUN4V_EDESC CPU_SUN4V_RPRT_EDESC
1318\#define ESUN4V_ATTR CPU_SUN4V_RPRT_ATTR
1319\#define ESUN4V_ADDR CPU_SUN4V_RPRT_ADDR
1320\#define ESUN4V_SZ CPU_SUN4V_RPRT_SZ
1321\#define ESUN4V_G_CPUID CPU_SUN4V_RPRT_G_CPUID
1322\#define ESUN4V_G_SECS CPU_SUN4V_RPRT_G_SECS
1323
1324
1325
1326err_sun4v_rprt ERR_SUN4V_RPRT_SIZE
1327 sun4v_erpt ERR_SUN4V_CPU_ERPT
1328 in_use ERR_SUN4V_RPRT_IN_USE
1329
1330\#define ERR_SUN4V_PCIE_ERPT ERR_SUN4V_CPU_ERPT
1331
1332\#define ERR_SUN4V_RPRT_G_EHDL (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_EHDL)
1333\#define ERR_SUN4V_RPRT_G_STICK (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_STICK)
1334\#define ERR_SUN4V_RPRT_EDESC (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_EDESC)
1335\#define ERR_SUN4V_RPRT_ATTR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ATTR)
1336\#define ERR_SUN4V_RPRT_ADDR (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ADDR)
1337\#define ERR_SUN4V_RPRT_SZ (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_SZ)
1338\#define ERR_SUN4V_RPRT_G_CPUID (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_CPUID)
1339\#define ERR_SUN4V_RPRT_G_SECS (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_G_SECS)
1340\#define ERR_SUN4V_RPRT_ASI (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_ASI)
1341\#define ERR_SUN4V_RPRT_REG (ERR_SUN4V_CPU_ERPT + CPU_SUN4V_RPRT_REG)
1342
1343\#define ERR_SUN4V_PCIE_SYSINO (ERR_SUN4V_PCIE_ERPT + PCIERPT_SYSINO)
1344\#define ERR_SUN4V_PCIE_EHDL (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_EHDL)
1345\#define ERR_SUN4V_PCIE_STICK (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_STICK)
1346\#define ERR_SUN4V_PCIE_DESC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_DESC)
1347\#define ERR_SUN4V_PCIE_SPECIFIC (ERR_SUN4V_PCIE_ERPT + PCIERPT_SUN4V_SPECFIC)
1348\#define ERR_SUN4V_PCIE_WORD4 (ERR_SUN4V_PCIE_ERPT + PCIERPT_WORD4)
1349\#define ERR_SUN4V_PCIE_HDR1 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR1)
1350\#define ERR_SUN4V_PCIE_HDR2 (ERR_SUN4V_PCIE_ERPT + PCIERPT_HDR2)
1351
1352err_diag_rprt ERR_DIAG_RPRT_SIZE
1353 error_type ERR_DIAG_RPRT_ERROR_TYPE
1354 report_type ERR_DIAG_RPRT_REPORT_TYPE
1355 tod ERR_DIAG_RPRT_TOD
1356 ehdl ERR_DIAG_RPRT_EHDL
1357 err_stick ERR_DIAG_RPRT_ERR_STICK
1358 cpuver ERR_DIAG_RPRT_CPUVER
1359 cpuserial ERR_DIAG_RPRT_SERIAL
1360 tstate ERR_DIAG_RPRT_TSTATE
1361 htstate ERR_DIAG_RPRT_HTSTATE
1362 tpc ERR_DIAG_RPRT_TPC
1363 cpuid ERR_DIAG_RPRT_CPUID
1364 tt ERR_DIAG_RPRT_TT
1365 tl ERR_DIAG_RPRT_TL
1366 err_diag_report_data ERR_DIAG_RPRT_ERR_DIAG
1367
1368\#define ERR_DIAG_RPRT_IN_USE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_IN_USE)
1369\#define ERR_DIAG_ABORT_DATA ERR_DIAG_RPRT_ERR_DIAG
1370\#define ERR_DIAG_DATA_OFFSET (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_DIAG_DATA)
1371\#define ERR_DIAG_RPRT_REPORT_SIZE (ERR_DIAG_RPRT_ERR_DIAG + ERR_DIAG_BUF_RPRT_SIZE)
1372
1373niu_cookie NIU_COOKIE_SIZE
1374 ldg2ldn_table NIU_LDG2LDN_TABLE
1375 vec2ldg_table NIU_VEC2LDG_TABLE
1376
1377ecc_syndrome_table_entry ECC_SYNDROME_TABLE_ENTRY_SIZE
1378
1379ecc_mask_table_entry ECC_MASK_TABLE_ENTRY_SIZE
1380
1381fpga_cookie FPGA_UART_COOKIE_SIZE
1382 status FPGA_UART_COOKIE_STATUS
1383 enable FPGA_UART_COOKIE_ENABLE
1384 disable FPGA_UART_COOKIE_DISABLE
1385 valid FPGA_UART_COOKIE_VALID
1386 state FPGA_UART_COOKIE_STATE
1387 target FPGA_UART_COOKIE_TARGET
1388
1389\ Enumerations
1390
1391hvctl_res_t
1392
1393hvctl_guest_info_t
1394
1395machconfig
1396 maus MCONFIG_MAUS
1397 cwqs MCONFIG_CWQS
1398 rng MCONFIG_RNG
1399
1400\#define CONFIG_MAUS (CONFIG_MCONFIG + MCONFIG_MAUS)
1401\#define CONFIG_CWQS (CONFIG_MCONFIG + MCONFIG_CWQS)
1402\#define CONFIG_RNG (CONFIG_MCONFIG + MCONFIG_RNG)
1403
1404machguest
1405 niu_statep MGUEST_NIU_STATEP
1406
1407\#define GUEST_NIU_STATEP (GUEST_MGUEST + MGUEST_NIU_STATEP)
1408
1409niu_mapreg NIUMAPREG_SIZE NIUMAPREG_SHIFT
1410 state NIUMAPREG_STATE
1411 valid NIUMAPREG_VALID
1412 vcpup NIUMAPREG_VCPUP
1413
1414niu_state NIUSTATE_SIZE
1415 mapreg NIUSTATE_MAPREG
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.