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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / src / vpiu_errs.s
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920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: vpiu_errs.s
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49 .ident "@(#)vpiu_errs.s 1.2 07/05/15 SMI"
50
51 .file "vpci_errs.s"
52
53#include <sys/asm_linkage.h>
54#include <sys/htypes.h>
55#include <hypervisor.h>
56#include <sparcv9/asi.h>
57#include <sun4v/asi.h>
58#include <asi.h>
59#include <mmu.h>
60
61#include <guest.h>
62#include <offsets.h>
63#include <errs_common.h>
64#include <debug.h>
65#include <vpiu_errs.h>
66#include <vcpu.h>
67#include <abort.h>
68#include <util.h>
69
70
71#define r_piu_cookie %g1
72#define r_piu_e_rpt %g2
73#define r_piu_leaf_address %g4
74
75#define r_tmp1 %g5
76#define r_tmp2 %g7
77
78#if defined(CONFIG_PIU)
79
80#define PIU_PRINT PRINT
81#define PIU_PRINTX PRINTX
82
83
84#define PIU_ERR_PRINT(s, piu, off, scr1, scr2) \
85 PIU_PRINT(s) ;\
86 set off, scr1 ;\
87 ldx [piu + PIU_COOKIE_PCIE], scr2 ;\
88 ldx [scr1 + scr2], scr1 ;\
89 PIU_PRINTX(scr1)
90
91 ! %g1 = PIU Cookie
92 ! %g2 = Mondo DATA0
93 ! %g3 = IGN
94 ! %g4 = INO
95 ENTRY_NP(error_mondo_62)
96 PRINT("HV:PCIE Error mondo\r\n")
97
98#if DEBUG
99 PIU_ERR_PRINT("\r\n631800 = ", %g1, 0x31800, %g5, %g6)
100 PIU_ERR_PRINT("\r\n631808 = ", %g1, 0x31808, %g5, %g6)
101 PIU_PRINT("\r\n")
102 ldx [%g1 + PIU_COOKIE_PCIE], %g5
103 set 0x31808, %g6
104 ldx [%g5 + %g6], %g6
105 btst 1, %g6
106 bz 1f ! No IMU Error
107 nop
108 PIU_ERR_PRINT("\r\n631000 = ", %g1, 0x31000, %g5, %g6)
109 PIU_ERR_PRINT("\r\n631008 = ", %g1, 0x31008, %g5, %g6)
110 PIU_ERR_PRINT("\r\n631010 = ", %g1, 0x31010, %g5, %g6)
111 PIU_ERR_PRINT("\r\n631018 = ", %g1, 0x31018, %g5, %g6)
112 PIU_ERR_PRINT("\r\n631020 = ", %g1, 0x31020, %g5, %g6)
113 PIU_ERR_PRINT("\r\n631028 = ", %g1, 0x31028, %g5, %g6)
114 PIU_ERR_PRINT("\r\n631030 = ", %g1, 0x31030, %g5, %g6)
115 PIU_ERR_PRINT("\r\n631038 = ", %g1, 0x31038, %g5, %g6)
116 PIU_PRINT("\r\n")
1171:
118 ldx [%g1 + PIU_COOKIE_PCIE], %g5
119 set 0x31808, %g6
120 ldx [%g5 + %g6], %g6
121 btst 2, %g6
122 bz 1f ! No MMU Error
123 nop
124
125 PIU_ERR_PRINT("\r\n641000 = ", %g1, 0x41000, %g5, %g6)
126 PIU_ERR_PRINT("\r\n641008 = ", %g1, 0x41008, %g5, %g6)
127 PIU_ERR_PRINT("\r\n641010 = ", %g1, 0x41010, %g5, %g6)
128 PIU_ERR_PRINT("\r\n641018 = ", %g1, 0x41018, %g5, %g6)
129 PIU_ERR_PRINT("\r\n641020 = ", %g1, 0x41020, %g5, %g6)
130 PIU_ERR_PRINT("\r\n641028 = ", %g1, 0x41028, %g5, %g6)
131 PIU_ERR_PRINT("\r\n641030 = ", %g1, 0x41030, %g5, %g6)
132 PIU_PRINT("\r\n")
1331:
134#endif
135
136 mov %g2, %g7 ! save DATA0 for err handle setup
137
138 !
139 ! Generate a unique error handle
140 ! enters with:
141 ! %g1 loaded with piu cookie
142 ! %g2 data0, overwritten with r_piu_e_rpt
143 ! %g3 IGN
144 ! %g4 INO
145 ! %g5 scratch
146 ! %g6 scratch
147 ! %g7 data0
148 !
149 ! returns with:
150 ! %g1 r_piu_cookie
151 ! %g2 pointing to r_piu_e_rpt
152 !
153 GEN_ERR_HNDL_SETUP_ERPTS(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
154 ldx [r_piu_cookie + PIU_COOKIE_PCIE], %g4
155 ! use alias r_piu_leaf_address for %g4 now
156 !
157 set PCI_E_DMU_CORE_BLK_ERR_STAT_ADDR, r_tmp2
158 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
159 and r_tmp1, IMU_BIT, r_tmp2
160 brnz,a r_tmp2, imu_block_processing
161 stx r_tmp2, [r_piu_e_rpt + PCIERPT_DMU_CORE_AND_BLOCK_ERR_STATUS]
162
163 and r_tmp1, MMU_BIT, r_tmp2
164 brnz,a r_tmp2, mmu_block_processing
165 stx r_tmp2, [r_piu_e_rpt + PCIERPT_DMU_CORE_AND_BLOCK_ERR_STATUS]
166 ! should not get here
167 PRINT("HV:mondo 62 fall through to retry\r\n")
168 ba,a clear_dmu_err_piu_interrupt
169 .empty
170
171
172imu_block_processing:
173 PRINT("HV:imu_block_processing\r\n")
174 set PCI_E_IMU_INT_STAT_ADDR, r_tmp2
175 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
176
177.imu_eq_not_en_group_p:
178 PRINT("HV:.imu_eq_not_en_group_p\r\n")
179 btst IMU_EQ_NOT_EN_GROUP_P, r_tmp1
180 bz %xcc, .imu_eq_over_group_p
181 and r_tmp1, IMU_EQ_NOT_EN_GROUP_P, r_tmp2
182 stx r_tmp2, [r_piu_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
183 LOG_DMC_IMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
184 r_tmp2)
185 LOG_IMU_SCS_ERROR_LOG_REGS(r_piu_e_rpt, r_piu_leaf_address, \
186 r_tmp1, r_tmp2)
187 LOG_IMU_EQ_NOT_EN_GROUP_EPKT_P(r_piu_e_rpt, \
188 r_piu_leaf_address, r_tmp1, r_tmp2)
189 CLEAR_IMU_EQ_NOT_EN_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
190 r_tmp1, r_tmp2)
191 ba,a dmu_err_mondo_ereport
192 .empty
193
194.imu_eq_over_group_p:
195 PRINT("HV:imu_eq_over_group_p\r\n")
196 btst IMU_EQ_OVER_GROUP_P, r_tmp1
197 bz %xcc, .imu_msi_mes_group_p
198 and r_tmp1, IMU_EQ_OVER_GROUP_P, r_tmp2
199 stx r_tmp2, [r_piu_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
200 LOG_DMC_IMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
201 r_tmp2)
202 LOG_IMU_EQS_ERROR_LOG_REGS(r_piu_e_rpt, r_piu_leaf_address, \
203 r_tmp1, r_tmp2)
204 LOG_IMU_EQ_OVER_GROUP_EPKT_P(r_piu_e_rpt, \
205 r_piu_leaf_address, r_tmp1, r_tmp2)
206 CLEAR_IMU_EQ_OVER_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
207 r_tmp1, r_tmp2)
208 ba,a dmu_err_mondo_ereport
209 .empty
210
211.imu_msi_mes_group_p:
212 PRINT("HV:imu_msi_mes_group_p\r\n")
213 btst IMU_MSI_MES_GROUP_P, r_tmp1
214 bz %xcc, .imu_eq_not_en_group_s
215 and r_tmp1, IMU_MSI_MES_GROUP_P, r_tmp2
216 stx r_tmp2, [r_piu_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
217 LOG_DMC_IMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
218 r_tmp2)
219 LOG_IMU_RDS_ERROR_LOG_REG(r_piu_e_rpt, r_piu_leaf_address, \
220 r_tmp1, r_tmp2)
221 LOG_IMU_MSI_MES_GROUP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
222 r_tmp1, r_tmp2)
223 CLEAR_IMU_MSI_MES_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
224 r_tmp1, r_tmp2)
225 ba,a dmu_err_mondo_ereport
226 .empty
227
228.imu_eq_not_en_group_s:
229 PRINT("HV:imu_eq_not_en_group_s\r\n")
230 set IMU_EQ_NOT_EN_GROUP_P, r_tmp2
231 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
232 btst r_tmp2, r_tmp1
233 bz %xcc, .imu_eq_over_group_s
234 and r_tmp2, r_tmp1, r_tmp2
235 stx r_tmp2, [r_piu_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
236 LOG_DMC_IMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
237 r_tmp2)
238 LOG_IMU_EQ_NOT_EN_GROUP_EPKT_S(r_piu_e_rpt, \
239 r_piu_leaf_address, r_tmp1, r_tmp2)
240 CLEAR_IMU_EQ_NOT_EN_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
241 r_tmp1, r_tmp2)
242 ba,a dmu_err_mondo_ereport
243 .empty
244
245.imu_eq_over_group_s:
246 PRINT("HV:imu_eq_over_group_s\r\n")
247 set IMU_EQ_OVER_GROUP_P, r_tmp2
248 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
249 btst r_tmp2, r_tmp1
250 bz %xcc, .imu_msi_mes_group_s
251 and r_tmp2, r_tmp1, r_tmp2
252 stx r_tmp2, [r_piu_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
253 LOG_DMC_IMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
254 LOG_IMU_EQ_OVER_GROUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
255 r_tmp1, r_tmp2)
256 CLEAR_IMU_EQ_OVER_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
257 r_tmp1, r_tmp2)
258 ba,a dmu_err_mondo_ereport
259 .empty
260
261.imu_msi_mes_group_s:
262 PRINT("HV:imu_msi_mes_group_s\r\n")
263 set IMU_MSI_MES_GROUP_P, r_tmp2
264 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
265 btst r_tmp2, r_tmp1
266 bz,pn %xcc, .imu_block_processing_nothing_to_do
267 and r_tmp2, r_tmp1, r_tmp2
268 stx r_tmp2, [r_piu_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
269 LOG_DMC_IMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
270 LOG_IMU_MSI_MES_GROUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
271 r_tmp1, r_tmp2)
272 CLEAR_IMU_MSI_MES_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
273 r_tmp1, r_tmp2)
274 ba,a dmu_err_mondo_ereport
275 .empty
276
277.imu_block_processing_nothing_to_do:
278 PRINT("HV:imu_block_processing_nothing_to_do\r\n")
279 ! we should not get here
280 ba,a clear_dmu_err_piu_interrupt
281 .empty
282
283 PRINT("HV:mondo 62 fall through to retry\r\n")
284 CLEAR_PIU_INTERRUPT(r_piu_cookie, DMU_INTERNAL_INT, r_tmp1)
285 GENERATE_FMA_REPORT;
286
287mmu_block_processing:
288 PRINT("HV:mmu_block_processing\r\n")
289 set PCI_E_MMU_INT_STAT_ADDR, r_tmp1
290 ldx [r_piu_leaf_address + r_tmp1], r_tmp1
291
292.mmu_err_group_p:
293#ifdef DEBUG
294 PRINT("HV:mmu_err_group_p\r\n")
295 PRINT("HV:PCI_E_MMU_INT_STAT_ADDR:0x")
296 PRINTX(r_tmp1)
297 PRINT("\r\n")
298#endif
299 set MMU_ERR_GROUP_P, r_tmp2
300 btst r_tmp2, r_tmp1
301 bz %xcc, .mmu_err_group_s
302 and r_tmp1, r_tmp2, r_tmp2
303 stx r_tmp2, [r_piu_e_rpt + PCIERPT_MMU_INTR_STATUS]
304 LOG_DMC_MMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
305 LOG_MMU_TRANS_FAULT_REGS(r_piu_e_rpt, r_piu_leaf_address, \
306 r_tmp1, r_tmp2)
307 LOG_MMU_ERR_GROUP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
308 r_tmp1, r_tmp2)
309 CLEAR_MMU_ERR_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
310 r_tmp1, r_tmp2)
311 ba,a dmu_err_mondo_ereport
312 .empty
313
314.mmu_err_group_s:
315 PRINT("HV:mmu_err_group_s\r\n")
316 set MMU_ERR_GROUP_P, r_tmp2
317 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
318 btst r_tmp2, r_tmp1
319 bz,pn %xcc, .mmu_block_processing_nothing_to_do
320 and r_tmp2, r_tmp1, r_tmp2
321 stx r_tmp2, [r_piu_e_rpt + PCIERPT_MMU_INTR_STATUS]
322 LOG_DMC_MMU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
323 r_tmp2)
324 LOG_MMU_ERR_GROUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
325 r_tmp1, r_tmp2)
326 CLEAR_MMU_ERR_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
327 r_tmp1, r_tmp2)
328 ba,a dmu_err_mondo_ereport
329 .empty
330
331.mmu_block_processing_nothing_to_do:
332 PRINT("HV:mmu_block_processing_nothing_to_do\r\n")
333 ! we should not get here
334 ba,a clear_dmu_err_piu_interrupt
335 .empty
336
337 SET_SIZE(error_mondo_62)
338
339 ! %g1 = PIU Cookie
340 ! %g2 = Mondo DATA0
341 ! %g3 = IGN
342 ! %g4 = INO
343 ENTRY_NP(error_mondo_63)
344 PRINT("HV:mondo 63\r\n")
345
346 mov %g2, %g7 ! save DATA0 for err handle setup
347
348 !
349 ! Generate a unique error handle
350 ! enters with:
351 ! %g1 loaded with piu cookie
352 ! %g2 data0, overwritten with r_piu_e_rpt
353 ! %g3 IGN
354 ! %g4 INO
355 ! %g5 scratch
356 ! %g6 scratch
357 ! %g7 data0
358 !
359 ! returns with:
360 ! %g1 r_piu_cookie
361 ! %g2 pointing to r_piu_e_rpt
362 !
363 GEN_ERR_HNDL_SETUP_ERPTS(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
364 ldx [r_piu_cookie + PIU_COOKIE_PCIE], %g4
365 ! use alias r_piu_leaf_address for %g4 now
366 !
367
368 set PCI_E_PEU_INT_ENB_ADDR, r_tmp2
369 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
370 stx r_tmp1, [r_piu_e_rpt + PCIERPT_PEU_CORE_AND_BLOCK_INTR_ENABLE]
371
372 /* PEU Core and Block Interrupt Status Register (0x651808) */
373 set PCI_E_PEU_INT_STAT_ADDR, r_tmp2
374
375 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
376 and r_tmp1, ILU_BIT, r_tmp2
377 brnz,a r_tmp2, .peu_ilu_processing
378 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS]
379 and r_tmp1, UE_BIT, r_tmp2
380 brnz,a r_tmp2, .peu_ue_processing
381 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS]
382 and r_tmp1, CE_BIT, r_tmp2
383 brnz,a r_tmp2, .peu_ce_processing
384 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS]
385 and r_tmp1, OE_BIT, r_tmp2
386 brnz,a,pt r_tmp2, .peu_oe_processing
387 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_CORE_AND_BLOCK_INTR_STATUS]
388 ba,a clear_peu_err_piu_interrupt
389 .empty
390
391.peu_ue_processing:
392/*
393 * All PEU Uncorrectable errors log to the same group and use the Uncorrectable
394 * Header1 and Header2 Log registers to capture data. Completion Timeout
395 * Primary Error also logs to the PEU Transmit Other Event Header1 and Header2
396 * Log Registers. If UR_P is set, Hypervisor must also see if PP_P is set, as this
397 * indicates a Ingress MsgD request (posted) with poisend data error. If only
398 * UR_P is set, then a Ingress MWr request (posted) with poisend data error
399 * occured.
400 */
401.peu_uce_recv_group_p:
402 PRINT("HV:peu_uce_recv_group_p\r\n")
403 set PCI_E_PEU_UE_INT_STAT_ADDR, r_tmp2
404 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
405 set PEU_UE_RECV_GROUP_P, r_tmp2
406 and r_tmp2, r_tmp1, r_tmp2
407 brz r_tmp2, .peu_uce_trans_group_p
408 nop
409 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
410 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
411 LOG_PEU_UE_RCV_HDR_REGS(r_piu_e_rpt, r_piu_leaf_address, \
412 r_tmp1, r_tmp2)
413 LOG_PEU_UE_RECV_GROUP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address,\
414 r_tmp1, r_tmp2)
415 CLEAR_PEU_UE_RECV_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
416 r_tmp1, r_tmp2)
417
418 ba,a peu_err_mondo_ereport
419 .empty
420
421.peu_uce_trans_group_p:
422 PRINT("HV:peu_uce_trans_group_p\r\n")
423 set PEU_UE_TRANS_GROUP_P, r_tmp2
424 and r_tmp2, r_tmp1, r_tmp2
425 brz r_tmp2, .peu_uce_dlp_p
426 nop
427 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
428 PRINT("r_tmp1 0x")
429 PRINTX(r_tmp1)
430 PRINT("\r\n")
431 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
432 LOG_PEU_UE_TRANS_HDR_REGS(r_piu_e_rpt, r_piu_leaf_address, \
433 r_tmp1, r_tmp2)
434 LOG_PEU_UE_TRANS_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
435 r_tmp1, r_tmp2)
436 CLEAR_PEU_UE_TRANS_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
437 r_tmp1, r_tmp2)
438 ba,a peu_err_mondo_ereport
439 .empty
440
441.peu_uce_dlp_p:
442 PRINT("HV:peu_uce_dlp_p\r\n")
443 set PEU_DLP_P, r_tmp2
444 and r_tmp2, r_tmp1, r_tmp2
445 brz r_tmp2, .peu_uce_fcp_p
446 nop
447 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
448 PRINT("HV:r_tmp1 0x")
449 PRINTX(r_tmp1)
450 PRINT("\r\n")
451 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
452 LOG_PEU_UE_DLP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
453 r_tmp1, r_tmp2)
454 CLEAR_PEU_UE_DLP_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
455 r_tmp1, r_tmp2)
456 ba,a peu_err_mondo_ereport
457 .empty
458
459.peu_uce_fcp_p:
460 PRINT("HV:peu_uce_fcp_p\r\n")
461 set PEU_FCP_P, r_tmp2
462 and r_tmp2, r_tmp1, r_tmp2
463 brz r_tmp2, .peu_uce_tlu_dlp_s
464 nop
465 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
466 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
467 LOG_PEU_UE_FCP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
468 r_tmp1, r_tmp2)
469 CLEAR_PEU_UE_FCP_P(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
470 r_tmp2)
471 ba,a peu_err_mondo_ereport
472 .empty
473
474.peu_uce_tlu_dlp_s:
475 PRINT("HV:peu_uce_tlu_dlp_s\r\n")
476 set PEU_DLP_P, r_tmp2
477 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
478 and r_tmp2, r_tmp1, r_tmp2
479 brz r_tmp2, .peu_uce_recv_group_s
480 nop
481 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
482 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
483 LOG_PEU_UE_DLP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
484 r_tmp1, r_tmp2)
485 CLEAR_PEU_UE_DLP_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
486 r_tmp1, r_tmp2)
487 ba,a peu_err_mondo_ereport
488 .empty
489
490
491.peu_uce_recv_group_s:
492 PRINT("HV:peu_uce_recv_group_s\r\n")
493 set PEU_UE_RECV_GROUP_P, r_tmp2
494 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
495 and r_tmp2, r_tmp1, r_tmp2
496 brz r_tmp2, .peu_uce_trans_group_s
497 nop
498 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
499 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
500 LOG_PEU_UE_RECV_GROUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address,\
501 r_tmp1, r_tmp2)
502 CLEAR_PEU_UE_RECV_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
503 r_tmp1, r_tmp2)
504 ba,a peu_err_mondo_ereport
505 .empty
506
507.peu_uce_trans_group_s:
508 PRINT("HV:peu_uce_trans_group_s\r\n")
509 set PEU_UE_TRANS_GROUP_P, r_tmp2
510 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
511 and r_tmp2, r_tmp1, r_tmp2
512 brz,pn r_tmp2, .peu_uce_fcp_s
513 nop
514 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
515 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
516 r_tmp2)
517 LOG_PEU_UE_TRANS_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
518 r_tmp1, r_tmp2)
519 CLEAR_PEU_UE_TRANS_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
520 r_tmp1, r_tmp2)
521 ba,a peu_err_mondo_ereport
522 .empty
523
524.peu_uce_fcp_s:
525 PRINT("HV:peu_uce_fcp_s\r\n")
526 set PEU_FCP_P, r_tmp2
527 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
528 and r_tmp2, r_tmp1, r_tmp2
529 brz r_tmp2, .peu_uce_nothingtodo
530 nop
531 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_UE_STATUS]
532 LOG_PEU_UE_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
533 LOG_PEU_UE_FCP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
534 r_tmp1, r_tmp2)
535 CLEAR_PEU_UE_FCP_S(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
536 r_tmp2)
537 ba,a peu_err_mondo_ereport
538 .empty
539
540.peu_uce_nothingtodo:
541 PRINT("HV:peu_uce_nothingtodo\r\n")
542 PRINT("HV:r_tmp1 0x")
543 PRINTX(r_tmp1)
544 PRINT("\r\n")
545 ba,a clear_peu_err_piu_interrupt
546 .empty
547
548.peu_ce_processing:
549.pec_ce_primary:
550 PRINT("HV:pec_ce_processing\r\n")
551 set PCI_E_PEU_CE_INT_STAT_ADDR, r_tmp2
552 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
553 PRINT("HV:PCI_E_PEU_CE_INT_STAT_ADDR = 0x")
554 PRINTX(r_tmp1)
555 PRINT("\r\n")
556 set PEU_CE_GROUP_P, r_tmp2
557 and r_tmp2, r_tmp1, r_tmp2
558 brz r_tmp2, .peu_ce_secondary
559 nop
560 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_CE_INTERRUPT_STATUS]
561 LOG_PEU_CE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
562 r_tmp2)
563 LOG_PEU_CE_GROUP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
564 r_tmp1, r_tmp2)
565 CLEAR_PEU_CE_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
566 r_tmp2)
567 ba,a peu_err_mondo_ereport
568 .empty
569
570.peu_ce_secondary:
571 PRINT("HV:peu_ce_secondary\r\n")
572 set PEU_CE_GROUP_P, r_tmp2
573 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
574 and r_tmp2, r_tmp1, r_tmp2
575 brz,pn r_tmp2, .peu_ce_nothingtodo
576 nop
577 stx r_tmp2, [r_piu_e_rpt + PCIERPT_PEU_CE_INTERRUPT_STATUS]
578 LOG_PEU_CE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
579 r_tmp2)
580 LOG_PEU_CE_GROUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
581 r_tmp1, r_tmp2)
582 CLEAR_PEU_CE_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, \
583 r_tmp2)
584 ba,a peu_err_mondo_ereport
585 .empty
586
587.peu_ce_nothingtodo:
588#ifdef DEBUG
589 PRINT("HV:peu_ce_nothingtodo\r\n")
590 set PCI_E_PEU_CE_INT_STAT_ADDR, r_tmp2
591 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
592 PRINT("HV:PCI_E_PEU_CE_INT_STAT_ADDR:0x")
593 PRINTX(r_tmp1)
594 PRINT("\r\n")
595#endif
596 ba,a clear_peu_err_piu_interrupt
597 .empty
598
599.peu_oe_processing:
600/*
601 * Only MFC, CTO, UR, MRC, CRS, WUC, and RUC log information to any
602 * registers. All other capture no data(exception LIN, see CXPL Error
603 * Processing)
604 *
605 * MFC, UR, CTO, MRC, and CRS log to the ....
606 * PEU Recieve Other Event Header1 and Header2 Log Registers.
607 *
608 *
609 * MFC, CTO, WUC, RUC, and CRS log to the ....
610 * PEU Transmit Other Event Header1 and Header2 Log Registers.
611 */
612 PRINT("HV:peu_oe_processing\r\n")
613.peu_receive_other_event_p:
614 PRINT("HV:peu_receive_other_event_p\r\n")
615 /*
616 * Also logs trans regs
617 */
618 set PCI_E_PEU_OTHER_INT_STAT_ADDR, r_tmp2
619 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
620 PRINT("HV:contents = 0x")
621 PRINTX(r_tmp1)
622 PRINT("\r\n")
623 set PEU_OE_RECEIVE_GROUP_P, r_tmp2
624 btst r_tmp2, r_tmp1
625 bz %xcc, .peu_oe_link_interrupt_group_p
626 nop
627 /*
628 * Special, this set of errors also records some in the transmit
629 * regs
630 */
631 set PEU_OE_TRANS_GROUP_P, r_tmp2
632 btst r_tmp2, r_tmp1
633 .pushlocals
634 bz %xcc, 1f
635 nop
636 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
637 r_tmp2)
638 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
639 r_tmp1, r_tmp2, PEU_OE_RECEIVE_GROUP_P)
640 LOG_PEU_OE_TRANS_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
641 r_tmp1, r_tmp2)
642 ba,a 2f
643 .empty
6441:
645 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
646 r_tmp2)
647 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
648 r_tmp1, r_tmp2, PEU_OE_RECEIVE_GROUP_P)
6492:
650 set PCI_E_PEU_OTHER_INT_STAT_ADDR, r_tmp2
651 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
652 set PEU_OE_RECV_SVVS_RPT_MSK, r_tmp2
653 btst r_tmp2, r_tmp1
654 bz %xcc, 3f
655 nop
656 LOG_PEU_OE_RECV_GROUP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
657 r_tmp1, r_tmp2)
658 LOG_PEU_OE_RECV_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
659 r_tmp1, r_tmp2)
660 CLEAR_PEU_OE_RECV_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
661 r_tmp1, r_tmp2)
662 ba,a peu_err_mondo_ereport
663 .empty
6643:
665 LOG_PEU_OE_RECV_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
666 r_tmp1, r_tmp2)
667 CLEAR_PEU_OE_RECV_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
668 r_tmp1, r_tmp2)
669 ba,a clear_peu_err_piu_interrupt
670 .empty
671 .poplocals
672
673.peu_oe_link_interrupt_group_p:
674 PRINT("HV:.peu_oe_link_interrupt_group_p\r\n")
675 PRINT("HV:r_tmp1 = 0x")
676 PRINTX(r_tmp1)
677 PRINT("\r\n")
678 set PEU_OE_LINK_INTERRUPT_GROUP_P, r_tmp2
679 btst r_tmp2, r_tmp1
680 bz %xcc, .peu_trans_other_event_p
681 nop
682 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
683 r_tmp2)
684 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
685 r_tmp1, r_tmp2, PEU_OE_LINK_INTERRUPT_GROUP_P)
686
687 set PCI_E_PEU_CXPL_INT_STAT_ADDR, r_tmp2
688 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
689 PRINT("HV:PCI_E_PEU_CXPL_INT_STAT_ADDR\r\n")
690 PRINTX(r_tmp1)
691 PRINT("\r\n")
692
693 set CXPL_EVT_RCV_EN_LB, r_tmp2
694 and r_tmp1, r_tmp2, r_tmp2
695 brnz,pn r_tmp2, .cxpl_evt_rcv_en_lb
696 nop
697 set CXPL_EVT_RCV_DIS_LINK, r_tmp2
698 and r_tmp1, r_tmp2, r_tmp2
699 brnz,pn r_tmp2, .cxpl_evt_rcv_dis_link
700 nop
701 set CXPL_EVT_RCV_HOT_RST, r_tmp2
702 and r_tmp1, r_tmp2, r_tmp2
703 brnz,pn r_tmp2, .cxpl_evt_rcv_hot_rst
704 nop
705 set CXPL_EVT_RCV_EIDLE_EXIT, r_tmp2
706 and r_tmp1, r_tmp2, r_tmp2
707 brnz,pn r_tmp2, .cxpl_evt_rcv_eidle_exit
708 nop
709 set CXPL_EVT_RCV_EIDLE, r_tmp2
710 and r_tmp1, r_tmp2, r_tmp2
711 brnz,pn r_tmp2, .cxpl_evt_rcv_eidle
712 nop
713 set CXPL_EVT_RCV_TS1, r_tmp2
714 and r_tmp1, r_tmp2, r_tmp2
715 brnz,pn r_tmp2, .cxpl_evt_rcv_ts1
716 nop
717 set CXPL_EVT_RCV_TS2, r_tmp2
718 and r_tmp1, r_tmp2, r_tmp2
719 brnz,pn r_tmp2, .cxpl_evt_rcv_ts2
720 nop
721 set CXPL_EVT_SEND_SKP_B2B, r_tmp2
722 and r_tmp1, r_tmp2, r_tmp2
723 brnz,pn r_tmp2, .cxpl_evt_send_skp_b2b
724 nop
725 set CXPL_ERR_OUTSTANDING_SKIP, r_tmp2
726 and r_tmp1, r_tmp2, r_tmp2
727 brnz,pn r_tmp2, .cxpl_err_outstanding_skip
728 nop
729 set CXPL_ERR_ELASTIC_FIFO_UNDRFLW, r_tmp2
730 and r_tmp1, r_tmp2, r_tmp2
731 brnz,pn r_tmp2, .cxpl_err_elastic_fifo_undrflw
732 nop
733 set CXPL_ERR_ELSTC_FIFO_OVRFLW, r_tmp2
734 and r_tmp1, r_tmp2, r_tmp2
735 brnz,pn r_tmp2, .cxpl_err_elstc_fifo_ovrflw
736 nop
737 set CXPL_ERR_ALIGN, r_tmp2
738 and r_tmp1, r_tmp2, r_tmp2
739 brnz,pn r_tmp2, .cxpl_err_align
740 nop
741 set CXPL_ERR_KCHAR_DLLP_TLP, r_tmp2
742 and r_tmp1, r_tmp2, r_tmp2
743 brnz,pn r_tmp2, .cxpl_err_kchar_dllp_tlp
744 nop
745 set CXPL_ERR_ILL_END_POS, r_tmp2
746 and r_tmp1, r_tmp2, r_tmp2
747 brnz,pn r_tmp2, .cxpl_err_ill_end_pos
748 nop
749 and r_tmp1, CXPL_ERR_SYNC, r_tmp2
750 brnz,pn r_tmp2, .cxpl_err_sync
751 nop
752 and r_tmp1, CXPL_ERR_END_NO_STP_SDP, r_tmp2
753 brnz,pn r_tmp2, .cxpl_err_end_no_stp_sdp
754 nop
755 and r_tmp1, CXPL_ERR_SDP_NO_END, r_tmp2
756 brnz,pn r_tmp2, .cxpl_err_sdp_no_end
757 nop
758 and r_tmp1, CXPL_ERR_STP_NO_END_EDB, r_tmp2
759 brnz,pn r_tmp2, .cxpl_err_stp_no_end_edb
760 nop
761 and r_tmp1, CXPL_ERR_ILL_PAD_POS, r_tmp2
762 brnz,pn r_tmp2, .cxpl_err_ill_pad_pos
763 nop
764 and r_tmp1, CXPL_ERR_MULTI_SDP, r_tmp2
765 brnz,pn r_tmp2, .cxpl_err_multi_sdp
766 nop
767 and r_tmp1, CXPL_ERR_MULTI_STP, r_tmp2
768 brnz,pn r_tmp2, .cxpl_err_multi_stp
769 nop
770 and r_tmp1, CXPL_ERR_ILL_SDP_POS, r_tmp2
771 brnz,pn r_tmp2, .cxpl_err_ill_sdp_pos
772 nop
773 and r_tmp1, CXPL_ERR_ILL_STP_POS, r_tmp2
774 brnz,pn r_tmp2, .cxpl_err_ill_stp_pos
775 nop
776 and r_tmp1, CXPL_ERR_UNSUP_DLLP, r_tmp2
777 brnz,pn r_tmp2, .cxpl_err_unsup_dllp
778 nop
779 and r_tmp1, CXPL_ERR_SRC_TLP, r_tmp2
780 brnz,pn r_tmp2, .cxpl_err_src_tlp
781 nop
782 and r_tmp1, CXPL_ERR_SDS_LOS, r_tmp2
783 brnz,pt r_tmp2, .cxpl_err_sds_los
784 nop
785
786.nothing_to_do_peu_oe_link_interrupt_group_p:
787 PRINT("HV:.nothing_to_do_tlu_oe_link_interrupt_group_p\r\n")
788 ba,a .all_done_peu_oe_link_interrupt_group_p
789 .empty
790
791.cxpl_evt_rcv_en_lb:
792 PRINT("HV:.cxpl_evt_rcv_en_lb\r\n")
793 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
794 CXPL_EVT_RCV_EN_LB, r_tmp1, r_tmp2)
795 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
796 CXPL_EVT_RCV_EN_LB, r_tmp1, r_tmp2)
797 ba,a .all_done_peu_oe_link_interrupt_group_p
798 .empty
799
800.cxpl_evt_rcv_dis_link:
801 PRINT("HV:.cxpl_evt_rcv_dis_link\r\n")
802 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
803 CXPL_EVT_RCV_DIS_LINK, r_tmp1, r_tmp2)
804 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
805 CXPL_EVT_RCV_DIS_LINK, r_tmp1, r_tmp2)
806 ba,a .all_done_peu_oe_link_interrupt_group_p
807 .empty
808
809.cxpl_evt_rcv_hot_rst:
810 PRINT("HV:.cxpl_evt_rcv_hot_rst\r\n")
811 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
812 CXPL_EVT_RCV_HOT_RST, r_tmp1, r_tmp2)
813 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
814 CXPL_EVT_RCV_HOT_RST, r_tmp1, r_tmp2)
815 ba,a .all_done_peu_oe_link_interrupt_group_p
816 .empty
817
818.cxpl_evt_rcv_eidle_exit:
819 PRINT("HV:.cxpl_evt_rcv_eidle_exit\r\n")
820 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
821 CXPL_EVT_RCV_EIDLE_EXIT, r_tmp1, r_tmp2)
822 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
823 CXPL_EVT_RCV_EIDLE_EXIT, r_tmp1, r_tmp2)
824 ba,a .all_done_peu_oe_link_interrupt_group_p
825 .empty
826
827.cxpl_evt_rcv_eidle:
828 PRINT("HV:.cxpl_evt_rcv_eidle\r\n")
829 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
830 CXPL_EVT_RCV_EIDLE, r_tmp1, r_tmp2)
831 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
832 CXPL_EVT_RCV_EIDLE, r_tmp1, r_tmp2)
833 ba,a .all_done_peu_oe_link_interrupt_group_p
834 .empty
835
836.cxpl_evt_rcv_ts1:
837 PRINT("HV:.cxpl_evt_rcv_ts1\r\n")
838 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
839 CXPL_EVT_RCV_TS1, r_tmp1, r_tmp2)
840 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
841 CXPL_EVT_RCV_TS1, r_tmp1, r_tmp2)
842 ba,a .all_done_peu_oe_link_interrupt_group_p
843 .empty
844
845.cxpl_evt_rcv_ts2:
846 PRINT("HV:.cxpl_evt_rcv_ts2\r\n")
847 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
848 CXPL_EVT_RCV_TS2, r_tmp1, r_tmp2)
849 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
850 CXPL_EVT_RCV_TS2, r_tmp1, r_tmp2)
851 ba,a .all_done_peu_oe_link_interrupt_group_p
852 .empty
853
854.cxpl_evt_send_skp_b2b:
855 PRINT("HV:.cxpl_evt_send_skp_b2b\r\n")
856 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
857 CXPL_EVT_SEND_SKP_B2B, r_tmp1, r_tmp2)
858 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
859 CXPL_EVT_SEND_SKP_B2B, r_tmp1, r_tmp2)
860 ba,a .all_done_peu_oe_link_interrupt_group_p
861 .empty
862
863.cxpl_err_outstanding_skip:
864 PRINT("HV:.cxpl_err_outstanding_skip\r\n")
865 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
866 CXPL_ERR_OUTSTANDING_SKIP, r_tmp1, r_tmp2)
867 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
868 CXPL_ERR_OUTSTANDING_SKIP, r_tmp1, r_tmp2)
869 ba,a .all_done_peu_oe_link_interrupt_group_p
870 .empty
871
872.cxpl_err_elastic_fifo_undrflw:
873 PRINT("HV:.cxpl_err_elastic_fifo_undrflw\r\n")
874 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
875 CXPL_ERR_ELASTIC_FIFO_UNDRFLW, r_tmp1, \
876 r_tmp2)
877 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
878 CXPL_ERR_ELASTIC_FIFO_UNDRFLW, r_tmp1, \
879 r_tmp2)
880 ba,a .all_done_peu_oe_link_interrupt_group_p
881 .empty
882
883.cxpl_err_elstc_fifo_ovrflw:
884 PRINT("HV:.cxpl_err_elstc_fifo_ovrflw\r\n")
885 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
886 CXPL_ERR_ELSTC_FIFO_OVRFLW, r_tmp1, \
887 r_tmp2)
888 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
889 CXPL_ERR_ELSTC_FIFO_OVRFLW, r_tmp1, \
890 r_tmp2)
891 ba,a .all_done_peu_oe_link_interrupt_group_p
892 .empty
893
894.cxpl_err_align:
895 PRINT("HV:.cxpl_err_align\r\n")
896 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
897 CXPL_ERR_ALIGN, r_tmp1, r_tmp2)
898 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
899 CXPL_ERR_ALIGN, r_tmp1, r_tmp2)
900 ba,a .all_done_peu_oe_link_interrupt_group_p
901 .empty
902
903.cxpl_err_kchar_dllp_tlp:
904 PRINT("HV:.cxpl_err_kchar_dllp_tlp\r\n")
905 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
906 CXPL_ERR_KCHAR_DLLP_TLP, r_tmp1, r_tmp2)
907 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
908 CXPL_ERR_KCHAR_DLLP_TLP, r_tmp1, r_tmp2)
909 ba,a .all_done_peu_oe_link_interrupt_group_p
910 .empty
911
912.cxpl_err_ill_end_pos:
913 PRINT("HV:.cxpl_err_ill_end_pos\r\n")
914 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
915 CXPL_ERR_ILL_END_POS, r_tmp1, r_tmp2)
916 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
917 CXPL_ERR_ILL_END_POS, r_tmp1, r_tmp2)
918 ba,a .all_done_peu_oe_link_interrupt_group_p
919 .empty
920
921.cxpl_err_sync:
922 PRINT("HV:.cxpl_err_sync\r\n")
923 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
924 CXPL_ERR_SYNC, r_tmp1, r_tmp2)
925 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
926 CXPL_ERR_SYNC, r_tmp1, r_tmp2)
927 ba,a .all_done_peu_oe_link_interrupt_group_p
928 .empty
929
930.cxpl_err_end_no_stp_sdp:
931 PRINT("HV:.cxpl_err_end_no_stp_sdp\r\n")
932 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
933 CXPL_ERR_END_NO_STP_SDP, r_tmp1, r_tmp2)
934 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
935 CXPL_ERR_END_NO_STP_SDP, r_tmp1, r_tmp2)
936 ba,a .all_done_peu_oe_link_interrupt_group_p
937 .empty
938
939.cxpl_err_sdp_no_end:
940 PRINT("HV:.cxpl_err_sdp_no_end\r\n")
941 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
942 CXPL_ERR_SDP_NO_END, r_tmp1, r_tmp2)
943 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
944 CXPL_ERR_SDP_NO_END, r_tmp1, r_tmp2)
945 ba,a .all_done_peu_oe_link_interrupt_group_p
946 .empty
947
948.cxpl_err_stp_no_end_edb:
949 PRINT("HV:.cxpl_err_stp_no_end_edb\r\n")
950 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
951 CXPL_ERR_STP_NO_END_EDB, r_tmp1, r_tmp2)
952 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
953 CXPL_ERR_STP_NO_END_EDB, r_tmp1, r_tmp2)
954 ba,a .all_done_peu_oe_link_interrupt_group_p
955 .empty
956
957.cxpl_err_ill_pad_pos:
958 PRINT("HV:.cxpl_err_ill_pad_pos\r\n")
959 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
960 CXPL_ERR_ILL_PAD_POS, r_tmp1, r_tmp2)
961 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
962 CXPL_ERR_ILL_PAD_POS, r_tmp1, r_tmp2)
963 ba,a .all_done_peu_oe_link_interrupt_group_p
964 .empty
965
966.cxpl_err_multi_sdp:
967 PRINT("HV:.cxpl_err_multi_sdp\r\n")
968 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
969 CXPL_ERR_MULTI_SDP, r_tmp1, r_tmp2)
970 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
971 CXPL_ERR_MULTI_SDP, r_tmp1, r_tmp2)
972 ba,a .all_done_peu_oe_link_interrupt_group_p
973 .empty
974
975.cxpl_err_multi_stp:
976 PRINT("HV:.cxpl_err_multi_stp\r\n")
977 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
978 CXPL_ERR_MULTI_STP, r_tmp1, r_tmp2)
979 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
980 CXPL_ERR_MULTI_STP, r_tmp1, r_tmp2)
981 ba,a .all_done_peu_oe_link_interrupt_group_p
982 .empty
983
984.cxpl_err_ill_sdp_pos:
985 PRINT("HV:.cxpl_err_ill_sdp_pos\r\n")
986 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
987 CXPL_ERR_ILL_SDP_POS, r_tmp1, r_tmp2)
988 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
989 CXPL_ERR_ILL_SDP_POS, r_tmp1, r_tmp2)
990 ba,a .all_done_peu_oe_link_interrupt_group_p
991 .empty
992
993.cxpl_err_ill_stp_pos:
994 PRINT("HV:.cxpl_err_ill_stp_pos\r\n")
995 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
996 CXPL_ERR_ILL_STP_POS, r_tmp1, r_tmp2)
997 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
998 CXPL_ERR_ILL_STP_POS, r_tmp1, r_tmp2)
999 ba,a .all_done_peu_oe_link_interrupt_group_p
1000 .empty
1001
1002.cxpl_err_unsup_dllp:
1003 PRINT("HV:.cxpl_err_unsup_dllp\r\n")
1004 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
1005 CXPL_ERR_UNSUP_DLLP, r_tmp1, r_tmp2)
1006 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
1007 CXPL_ERR_UNSUP_DLLP, r_tmp1, r_tmp2)
1008 ba,a .all_done_peu_oe_link_interrupt_group_p
1009 .empty
1010
1011.cxpl_err_src_tlp:
1012 PRINT("HV:.cxpl_err_src_tlp\r\n")
1013 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
1014 CXPL_ERR_SRC_TLP, r_tmp1, r_tmp2)
1015 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
1016 CXPL_ERR_SRC_TLP, r_tmp1, r_tmp2)
1017 ba,a .all_done_peu_oe_link_interrupt_group_p
1018 .empty
1019
1020.cxpl_err_sds_los:
1021 PRINT("HV:.cxpl_err_sds_los\r\n")
1022 LOG_PCIERPT_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
1023 CXPL_ERR_SDS_LOS, r_tmp1, r_tmp2)
1024 CLEAR_CXPL_INTR_STATUS(r_piu_e_rpt, r_piu_leaf_address, \
1025 CXPL_ERR_SDS_LOS, r_tmp1, r_tmp2)
1026
1027
1028.all_done_peu_oe_link_interrupt_group_p:
1029 PRINT("HV:all_done_peu_oe_link_interrupt_group_p\r\n")
1030 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, r_tmp2
1031 set PEU_OE_LINK_INTERRUPT_GROUP_P, r_tmp1
1032 stx r_tmp1, [r_piu_leaf_address + r_tmp2]
1033
1034#ifdef DEBUG
1035 set PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, r_tmp2
1036 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
1037 PRINT("HV:PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR 0x")
1038 PRINTX(r_tmp1)
1039 PRINT("\r\n")
1040#endif
1041 ba,a clear_peu_err_piu_interrupt
1042 .empty
1043
1044.peu_trans_other_event_p:
1045 PRINT("HV:peu_trans_other_event_p\r\n")
1046 /*
1047 * Bits 22:21, 17, 16, and 15
1048 * this test must happen after the recieve other event test
1049 * as both the transmit and recieve groups have overlap and
1050 * post info to both trans and receive regs. Since we tested
1051 * the overlap in the receive we won't need to test it here
1052 * in theory the only bit we should see is the one that only
1053 * posts to the trans reg
1054 */
1055 set PEU_OE_TRANS_GROUP_P, r_tmp2
1056 btst r_tmp2, r_tmp1
1057 bz %xcc, .peu_oe_no_dup_group_p
1058 nop
1059 set PEU_OE_TRANS_SVVS_RPT_MSK, r_tmp2
1060 btst r_tmp2, r_tmp1
1061 .pushlocals
1062 bz %xcc, 1f
1063 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1064 r_tmp2)
1065 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
1066 r_tmp1, r_tmp2, PEU_OE_TRANS_GROUP_P)
1067 LOG_PEU_OE_TRANS_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
1068 r_tmp1, r_tmp2)
1069 LOG_PEU_OE_TRANS_GROUP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address,\
1070 r_tmp1, r_tmp2)
1071 CLEAR_PEU_OE_TRANS_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
1072 r_tmp1, r_tmp2)
1073 ba,a peu_err_mondo_ereport
1074 .empty
10751:
1076 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1077 r_tmp2)
1078 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
1079 r_tmp1, r_tmp2, PEU_OE_TRANS_GROUP_P)
1080 LOG_PEU_OE_TRANS_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
1081 r_tmp1, r_tmp2)
1082 CLEAR_PEU_OE_TRANS_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
1083 r_tmp1, r_tmp2)
1084 ba,a clear_peu_err_piu_interrupt
1085 .empty
1086 .poplocals
1087
1088.peu_oe_no_dup_group_p:
1089 PRINT("HV:peu_oe_no_dup_group_p\r\n")
1090 set PEU_OE_NO_DUP_GROUP_P, r_tmp2
1091 btst r_tmp2, r_tmp1
1092 bz,pn %xcc, .peu_oe_dup_lli_p
1093 nop
1094 set PEU_OE_NO_DUP_SVVS_RPT_MSK, r_tmp2
1095 btst r_tmp2, r_tmp1
1096 .pushlocals
1097 bz %xcc, 1f
1098 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1099 r_tmp2)
1100 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
1101 r_tmp1, r_tmp2, PEU_OE_NO_DUP_GROUP_P)
1102 LOG_PEU_OE_NO_DUP_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, \
1103 r_tmp1, r_tmp2)
1104 CLEAR_PEU_OE_NO_DUP_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
1105 r_tmp1, r_tmp2)
1106 ba,a peu_err_mondo_ereport
1107 .empty
11081:
1109 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1110 r_tmp2)
1111 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
1112 r_tmp1, r_tmp2, PEU_OE_NO_DUP_GROUP_P)
1113 CLEAR_PEU_OE_NO_DUP_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
1114 r_tmp1, r_tmp2)
1115 ba,a clear_peu_err_piu_interrupt
1116 .empty
1117 .poplocals
1118
1119.peu_oe_dup_lli_p:
1120 PRINT("HV:peu_oe_dup_lli_p\r\n")
1121 set PEU_OE_DUP_LLI_P, r_tmp2
1122 btst r_tmp2, r_tmp1
1123 bz,pn %xcc, .peu_oe_no_dup_group_s
1124 nop
1125 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1126 r_tmp2)
1127 LOG_PEU_OE_INTR_STATUS_P(r_piu_e_rpt, r_piu_leaf_address, \
1128 r_tmp1, r_tmp2, PEU_OE_DUP_LLI_P)
1129 LOG_ILU_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1130 CLEAR_PEU_OE_DUP_LLI_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, \
1131 r_tmp1, r_tmp2)
1132 ba,a peu_err_mondo_ereport
1133 .empty
1134
1135.peu_oe_no_dup_group_s:
1136 PRINT("HV:peu_oe_no_dup_group_s\r\n")
1137 set PEU_OE_NO_DUP_GROUP_P, r_tmp2
1138 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1139 btst r_tmp2, r_tmp1
1140 bz,pn %xcc, .peu_trans_other_event_s
1141 nop
1142 set PEU_OE_NO_DUP_SVVS_RPT_MSK, r_tmp2
1143 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1144 btst r_tmp2, r_tmp1
1145 .pushlocals
1146 bz %xcc, 1f
1147 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
1148 r_tmp1, r_tmp2)
1149 LOG_PEU_OE_INTR_STATUS_S(r_piu_e_rpt, r_piu_leaf_address, \
1150 r_tmp1, r_tmp2, PEU_OE_NO_DUP_GROUP_P)
1151 LOG_PEU_OE_NO_DUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
1152 r_tmp1, r_tmp2)
1153 CLEAR_PEU_OE_NO_DUP_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
1154 r_tmp1, r_tmp2)
1155 ba,a peu_err_mondo_ereport
1156 .empty
11571:
1158 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
1159 r_tmp1, r_tmp2)
1160 LOG_PEU_OE_INTR_STATUS_S(r_piu_e_rpt, r_piu_leaf_address, \
1161 r_tmp1, r_tmp2, PEU_OE_NO_DUP_GROUP_P)
1162 CLEAR_PEU_OE_NO_DUP_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
1163 r_tmp1, r_tmp2)
1164 ba,a clear_peu_err_piu_interrupt
1165 .empty
1166 .poplocals
1167
1168.peu_trans_other_event_s:
1169 PRINT("HV:peu_trans_other_event_s\r\n")
1170 set PEU_OE_TRANS_GROUP_P, r_tmp2
1171 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1172 btst r_tmp2, r_tmp1
1173 bz,pn %xcc, .peu_receive_other_event_s
1174 nop
1175 set PEU_OE_TRANS_SVVS_RPT_MSK, r_tmp2
1176 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1177 btst r_tmp2, r_tmp1
1178 .pushlocals
1179 bz %xcc, 1f
1180 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1181 r_tmp2)
1182 LOG_PEU_OE_INTR_STATUS_S(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1183 r_tmp2, PEU_OE_TRANS_GROUP_P)
1184 LOG_PEU_OE_TRANS_GROUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address,\
1185 r_tmp1, r_tmp2)
1186 CLEAR_PEU_OE_TRANS_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
1187 r_tmp1, r_tmp2)
1188 ba,a peu_err_mondo_ereport
1189 .empty
1190
11911:
1192 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, \
1193 r_tmp1, r_tmp2)
1194 LOG_PEU_OE_INTR_STATUS_S(r_piu_e_rpt, r_piu_leaf_address, \
1195 r_tmp1, r_tmp2, PEU_OE_TRANS_GROUP_P)
1196 CLEAR_PEU_OE_TRANS_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
1197 r_tmp1, r_tmp2)
1198 ba,a clear_peu_err_piu_interrupt
1199 .empty
1200 .poplocals
1201
1202.peu_receive_other_event_s:
1203 PRINT("HV:peu_receive_other_event_s\r\n")
1204 set PEU_OE_RECEIVE_GROUP_P, r_tmp2
1205 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1206 btst r_tmp2, r_tmp1
1207 bz %xcc, .peu_oe_dup_lli_s
1208 nop
1209 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1210 r_tmp2)
1211 LOG_PEU_OE_INTR_STATUS_S(r_piu_e_rpt, r_piu_leaf_address, \
1212 r_tmp1, r_tmp2, PEU_OE_RECEIVE_GROUP_P)
1213 set PCI_E_PEU_OTHER_INT_STAT_ADDR, r_tmp2
1214 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
1215 set PEU_OE_RECV_SVVS_RPT_MSK, r_tmp2
1216 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1217 btst r_tmp2, r_tmp1
1218 bz %xcc, 1f
1219 nop
1220 LOG_PEU_OE_RECV_GROUP_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, \
1221 r_tmp1, r_tmp2)
1222 CLEAR_PEU_OE_RECV_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
1223 r_tmp1, r_tmp2)
1224 ba,a peu_err_mondo_ereport
1225 .empty
12261:
1227 CLEAR_PEU_OE_RECV_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
1228 r_tmp1, r_tmp2)
1229 ba,a clear_peu_err_piu_interrupt
1230 .empty
1231
1232.peu_oe_dup_lli_s:
1233 PRINT("HV:peu_oe_dup_lli_s\r\n")
1234 set PEU_OE_DUP_LLI_P, r_tmp2
1235 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1236 btst r_tmp2, r_tmp1
1237 bz,pn %xcc, .peu_oe_processing_nothingtodo
1238 nop
1239 LOG_PEU_OE_GROUP_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1,\
1240 r_tmp2)
1241 LOG_PEU_OE_INTR_STATUS_S(r_piu_e_rpt, r_piu_leaf_address, \
1242 r_tmp1, r_tmp2, PEU_OE_DUP_LLI_P)
1243 LOG_ILU_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1244 CLEAR_PEU_OE_DUP_LLI_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, \
1245 r_tmp1, r_tmp2)
1246 ba,a peu_err_mondo_ereport
1247 .empty
1248
1249.peu_ilu_processing:
1250.ilu_interrupt_status_p:
1251 PRINT("HV:ilu_interrupt_status_p\r\n")
1252 set PCI_E_ILU_INT_STAT_ADDR, r_tmp2
1253 ldx [r_piu_leaf_address + r_tmp2], r_tmp1
1254 btst ILU_GROUP_P, r_tmp1
1255 bz %xcc, .ilu_interrupt_status_s
1256 and r_tmp1, ILU_GROUP_P, r_tmp2
1257 stx r_tmp2, [r_piu_e_rpt + PCIERPT_ILU_INTR_STATUS]
1258 LOG_ILU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1259 LOG_ILU_EPKT_P(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1260 CLEAR_ILU_GROUP_P(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1261 ba,a peu_err_mondo_ereport
1262 .empty
1263
1264
1265.ilu_interrupt_status_s:
1266 PRINT("HV:ilu_interrupt_status_s\r\n")
1267 set ILU_GROUP_P, r_tmp2
1268 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1269 btst r_tmp2, r_tmp1
1270 bz,pn %xcc, .ilu_nothing_todo
1271 and r_tmp2, r_tmp1, r_tmp2
1272 stx r_tmp2, [r_piu_e_rpt + PCIERPT_ILU_INTR_STATUS]
1273 LOG_ILU_REGS(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1274 LOG_ILU_EPKT_S(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1275 CLEAR_ILU_GROUP_S(r_piu_e_rpt, r_piu_leaf_address, r_tmp1, r_tmp2)
1276 ba,a peu_err_mondo_ereport
1277 .empty
1278
1279.ilu_nothing_todo:
1280 PRINT("HV:ilu_nothing_todo\r\n")
1281 ba,a clear_peu_err_piu_interrupt
1282 .empty
1283
1284 SET_SIZE(error_mondo_63)
1285
1286dmu_err_mondo_ereport:
1287 DMU_ERR_MONDO_EREPORT(r_piu_cookie, r_piu_e_rpt, r_tmp1, r_tmp2)
1288clear_dmu_err_piu_interrupt:
1289 CLEAR_PIU_INTERRUPT(r_piu_cookie, DMU_INTERNAL_INT, r_tmp1)
1290 GENERATE_FMA_REPORT; /* never returns */
1291
1292
1293peu_err_mondo_ereport:
1294 PEU_ERR_MONDO_EREPORT(r_piu_cookie, r_piu_e_rpt, r_tmp1, r_tmp2)
1295clear_peu_err_piu_interrupt:
1296 CLEAR_PIU_INTERRUPT(r_piu_cookie, PEU_INTERNAL_INT, r_tmp1)
1297 GENERATE_FMA_REPORT; /* never returns */
1298
1299.peu_oe_processing_nothingtodo:
1300 PRINT("HV:peu_oe_processing_nothingtodo\r\n")
1301 ba,a clear_peu_err_piu_interrupt
1302 .empty
1303
1304/*
1305 * %g2 pointing to ereport buffer, i.e. r_piu_e_rpt
1306 */
1307 ENTRY_NP(generate_guest_report)
1308 add r_piu_e_rpt, PCIERPT_SYSINO, %g1
1309#ifdef DEBUG
1310 PRINT("HV:generate_guest_report\r\n")
1311 PRINT("\r\n")
1312 ldx [%g1 + 0x00], %g3
1313 PRINT("HV:word0:0x")
1314 PRINTX(%g3)
1315 PRINT("\r\n")
1316 ldx [%g1 + 0x08], %g3
1317 PRINT("HV:word1:0x")
1318 PRINTX(%g3)
1319 PRINT("\r\n")
1320 ldx [%g1 + 0x10], %g3
1321 PRINT("HV:word2:0x")
1322 PRINTX(%g3)
1323 PRINT("\r\n")
1324 ldx [%g1 + 0x18], %g3
1325 PRINT("HV:word3:0x")
1326 PRINTX(%g3)
1327 PRINT("\r\n")
1328 ldx [%g1 + 0x20], %g3
1329 PRINT("HV:word4:0x")
1330 PRINTX(%g3)
1331 PRINT("\r\n")
1332 ldx [%g1 + 0x28], %g3
1333 PRINT("HV:word5:0x")
1334 PRINTX(%g3)
1335 PRINT("\r\n")
1336 ldx [%g1 + 0x30], %g3
1337 PRINT("HV:word6:0x")
1338 PRINTX(%g3)
1339 PRINT("\r\n")
1340 ldx [%g1 + 0x38], %g3
1341 PRINT("HV:word7:0x")
1342 PRINTX(%g3)
1343 PRINT("\r\n")
1344 PRINT("HV:calling:insert_device_mondo_p\r\n")
1345#endif
1346 STRAND_PUSH(%g1, %g2, %g3)
1347 ba insert_device_mondo_p
1348 rd %pc, %g7
1349 STRAND_POP(%g1, %g2)
1350 PRINT("HV:calling:generate_fma_report\r\n")
1351 /*
1352 * %g1 already points to the r_piu_e_rpt, no fixup, so don't use macro
1353 */
1354 ba,a generate_fma_report
1355 .empty
1356
1357 SET_SIZE(generate_guest_report)
1358/*
1359 * %g1 pointing to piu error buffer
1360 */
1361 ENTRY_NP(generate_fma_report)
1362
1363 ! set %g2 to point to unsent flag
1364 add %g1, PCI_UNSENT_PKT, %g2
1365
1366 ! set %g1 to point to vbsc err report
1367 add %g1, PCI_ERPT_U, %g1
1368
1369 ! set %g3 to contain the size of the buf
1370 mov PCIERPT_SIZE - EPKTSIZE, %g3
1371
1372 HVCALL(send_diag_erpt)
1373
1374 PRINT("HV:all done with piu error processing, fma report sent\r\n")
1375 retry
1376 SET_SIZE(generate_fma_report)
1377
1378! piu_err_mondo_receive
1379!
1380! %g1 = PIU Cookie
1381! %g2 = Mondo DATA0
1382! %g3 = IGN
1383! %g4 = INO
1384!
1385 ENTRY_NP(piu_err_mondo_receive)
1386 /*
1387 * is it mondo 62 or 63
1388 */
1389 cmp %g4, PEU_INTERNAL_INT ! 63
1390 beq,pt %xcc, error_mondo_63
1391 cmp %g4, DMU_INTERNAL_INT ! 62
1392 beq,pt %xcc, error_mondo_62
1393 nop
1394 ba insert_device_mondo_r
1395 rd %pc, %g7
1396 retry
1397 SET_SIZE(piu_err_mondo_receive)
1398
1399!
1400! piu_err_intr_getvalid
1401!
1402! %g1 PIU Cookie Pointer
1403! arg0 Virtual INO (%o0)
1404! --
1405! ret0 status (%o0)
1406! ret1 intr valid state (%o1)
1407!
1408 ENTRY_NP(piu_err_intr_getvalid)
1409 ba,a piu_intr_getvalid
1410 .empty
1411 SET_SIZE(piu_err_intr_getvalid)
1412
1413!
1414! piu_err_intr_setvalid
1415!
1416! %g1 PIU Cookie Pointer
1417! arg0 Virtual INO (%o0)
1418! arg1 intr valid state (%o1) 1: Valid 0: Invalid
1419! --
1420! ret0 status (%o0)
1421!
1422
1423 ENTRY_NP(piu_err_intr_setvalid)
1424 mov %o0, %g2
1425 mov %o1, %g3
1426 HVCALL(_piu_err_intr_setvalid)
1427
1428 ! _piu_err_intr_setvalid doesn't have any failure cases
1429 ! so it is safe to just return EOK
1430 HCALL_RET(EOK)
1431 SET_SIZE(piu_err_intr_setvalid)
1432
1433!
1434! _piu_err_intr_setvalid
1435! %g1 PIU Cookie Pointer
1436! %g2 device ino
1437! %g3 Valid/Invalid
1438!
1439 ENTRY_NP(_piu_err_intr_setvalid)
1440 and %g2, PIU_DEVINO_MASK, %g5
1441 cmp %g5, PEU_INTERNAL_INT ! is it mondo 63
1442 mov DMU_ERR_MONDO_OFFSET, %g4
1443 movne %xcc, PEU_ERR_MONDO_OFFSET, %g4
1444 ldx [%g1 + PIU_COOKIE_VIRTUAL_INTMAP], %g6
1445 add %g6, %g4, %g6 ! virtual intmap + mondo offset
1446 stb %g3, [%g6]
1447
1448 HVRET
1449 SET_SIZE(_piu_err_intr_setvalid)
1450
1451!
1452! piu_err_intr_getstate
1453!
1454! %g1 PIU Cookie Pointer
1455! arg0 Virtual INO (%o0)
1456! --
1457! ret0 status (%o0)
1458! ret1 (%o1) 1: Pending / 0: Idle
1459!
1460 ENTRY_NP(piu_err_intr_getstate)
1461 ba,a piu_intr_getstate
1462 .empty
1463 SET_SIZE(piu_err_intr_getstate)
1464
1465!
1466! piu_err_intr_setstate
1467!
1468! %g1 PIU Cookie Pointer
1469! arg0 Virtual INO (%o0)
1470! arg1 (%o1) 1: Pending / 0: Idle
1471! --
1472! ret0 status (%o0)
1473!
1474 ENTRY_NP(piu_err_intr_setstate)
1475 ba,a piu_intr_setstate
1476 .empty
1477 SET_SIZE(piu_err_intr_setstate)
1478
1479!
1480! piu_err_intr_gettarget
1481!
1482! %g1 PIU Cookie Pointer
1483! arg0 Virtual INO (%o0)
1484! --
1485! ret0 status (%o0)
1486! ret1 cpuid (%o1)
1487!
1488 ENTRY_NP(piu_err_intr_gettarget)
1489 ba,a piu_intr_gettarget
1490 .empty
1491 SET_SIZE(piu_err_intr_gettarget)
1492
1493!
1494! piu_err_intr_settarget
1495!
1496! %g1 PIU Cookie Pointer
1497! arg0 Virtual INO (%o0)
1498! arg1 cpuid (%o1)
1499! --
1500! ret0 status (%o0)
1501!
1502 ENTRY_NP(piu_err_intr_settarget)
1503 ba,a piu_intr_settarget
1504 .empty
1505 SET_SIZE(piu_err_intr_settarget)
1506
1507
1508!
1509! piu_err_intr_redistribution
1510! %g1 - this cpu
1511! %g2 - tgt cpu
1512!
1513! Generates each INO and calls the function that actually
1514! does the work
1515!
1516 ENTRY_NP(piu_err_intr_redistribution)
1517 CPU_PUSH(%g7, %g3, %g4, %g5)
1518
1519 mov %g2, %g1
1520 CPU_PUSH(%g1, %g3, %g4, %g5)
1521 mov PIU_AID << PIU_DEVINO_SHIFT, %g4
1522 or %g4, DMU_INTERNAL_INT, %g3
1523 HVCALL(_piu_err_intr_redistribution)
1524
1525 CPU_POP(%g1, %g3, %g4, %g5)
1526 CPU_PUSH(%g1, %g3, %g4, %g5)
1527 mov PIU_AID << PIU_DEVINO_SHIFT, %g4
1528 or %g4, PEU_INTERNAL_INT, %g3
1529 HVCALL(_piu_err_intr_redistribution)
1530
1531 CPU_POP(%g7, %g3, %g4, %g5)
1532 HVRET
1533 SET_SIZE(piu_err_intr_redistribution)
1534
1535 /*
1536 * _piu_err_intr_redistribution
1537 *
1538 * %g1 - tgt cpu
1539 * %g3 - INO
1540 */
1541 ENTRY_NP(_piu_err_intr_redistribution)
1542 CPU_PUSH(%g7, %g4, %g5, %g6)
1543 CPU_PUSH(%g1, %g4, %g5, %g6) ! save tgt cpu
1544 CPU_PUSH(%g3, %g4, %g5, %g6) ! save INO
1545
1546 GUEST_STRUCT(%g4)
1547 ! get dev
1548 srlx %g3, PIU_DEVINO_SHIFT, %g6
1549 DEVINST2INDEX(%g4, %g6, %g6, %g5, ._piu_err_intr_redistribution_fail)
1550 DEVINST2COOKIE(%g4, %g6, %g1, %g5, ._piu_err_intr_redistribution_fail)
1551
1552 and %g3, PIU_DEVINO_MASK, %g2
1553
1554 ! %g1 = PIU Cookie
1555 ! %g2 = device ino
1556 HVCALL(_piu_intr_gettarget)
1557 ! %g3 phys cpuid for this ino
1558
1559 STRAND_STRUCT(%g4)
1560 ldub [%g4 + STRAND_ID], %g2
1561 ! %g2 this cpu id
1562 cmp %g3, %g2
1563 bne %xcc, ._piu_err_intr_redistribution_done
1564 nop
1565
1566 ! deal with virtual portion
1567 CPU_POP(%g2, %g4, %g6, %g7)
1568 mov INTR_DISABLED, %g3
1569 ! %g1 = PIU cookie
1570 ! %g2 = vino
1571 ! %g3 = Disable
1572 HVCALL(_piu_err_intr_setvalid)
1573
1574 ! set new target
1575 and %g2, PIU_DEVINO_MASK, %g2
1576 CPU_POP(%g3, %g4, %g6, %g7)
1577 ! %g1 = PIU Cookie Ptr
1578 ! %g2 = device ino
1579 ! %g3 = Physical target CPU id
1580 HVCALL(_piu_intr_settarget)
1581
1582 ! clear state machine
1583 mov INTR_IDLE, %g3
1584 ! %g1 = PIU cookie
1585 ! %g2 = device ino
1586 ! %g3 = Idle
1587 HVCALL(_piu_intr_setstate)
1588
1589 ba,a ._piu_err_intr_redistribution_exit
1590
1591._piu_err_intr_redistribution_done:
1592 CPU_POP(%g3, %g4, %g5, %g6)
1593 CPU_POP(%g1, %g3, %g4, %g5)
1594._piu_err_intr_redistribution_exit:
1595 CPU_POP(%g7, %g3, %g4, %g5)
1596 HVRET
1597._piu_err_intr_redistribution_fail:
1598 CPU_POP(%g3, %g4, %g5, %g6)
1599 CPU_POP(%g1, %g3, %g4, %g5)
1600 ba hvabort
1601 rd %pc, %g1
1602
1603 SET_SIZE(_piu_err_intr_redistribution)
1604#endif /* CONFIG_PIU */
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