projects / OpenSPARC-T2-SAM / blame
| Commit | Line | Data |
|---|---|---|
| 920dae64 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * Hypervisor Software File: fire_regs.h | |
| 5 | * | |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 7 | * | |
| 8 | * - Do no alter or remove copyright notices | |
| 9 | * | |
| 10 | * - Redistribution and use of this software in source and binary forms, with | |
| 11 | * or without modification, are permitted provided that the following | |
| 12 | * conditions are met: | |
| 13 | * | |
| 14 | * - Redistribution of source code must retain the above copyright notice, | |
| 15 | * this list of conditions and the following disclaimer. | |
| 16 | * | |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
| 18 | * this list of conditions and the following disclaimer in the | |
| 19 | * documentation and/or other materials provided with the distribution. | |
| 20 | * | |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
| 22 | * may be used to endorse or promote products derived from this software | |
| 23 | * without specific prior written permission. | |
| 24 | * | |
| 25 | * This software is provided "AS IS," without a warranty of any kind. | |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
| 37 | * | |
| 38 | * You acknowledge that this software is not designed, licensed or | |
| 39 | * intended for use in the design, construction, operation or maintenance of | |
| 40 | * any nuclear facility. | |
| 41 | * | |
| 42 | * ========== Copyright Header End ============================================ | |
| 43 | */ | |
| 44 | /* | |
| 45 | * Copyright 2005 Sun Microsystems, Inc. All rights reserved. | |
| 46 | * Use is subject to license terms. | |
| 47 | */ | |
| 48 | ||
| 49 | #ifndef _FIRE_REGS_H | |
| 50 | #define _FIRE_REGS_H | |
| 51 | ||
| 52 | #pragma ident "@(#)fire_regs.h 1.1 05/03/01 SMI" | |
| 53 | ||
| 54 | #ifdef __cplusplus | |
| 55 | extern "C" { | |
| 56 | #endif | |
| 57 | ||
| 58 | /* BEGIN CSTYLED */ | |
| 59 | #define FIRE_JBUS_DEVICE_ID 0x00000000 | |
| 60 | #define FIRE_EBUS_OFFSET_BASE 0x00400020 | |
| 61 | #define FIRE_EBUS_OFFSET_MASK 0x00400028 | |
| 62 | #define FIRE_PCIE_A_MEM32_OFFSET_BASE 0x00400040 | |
| 63 | #define FIRE_PCIE_A_MEM32_OFFSET_MASK 0x00400048 | |
| 64 | #define FIRE_PCIE_A_IOCON_OFFSET_BASE 0x00400050 | |
| 65 | #define FIRE_PCIE_A_IOCON_OFFSET_MASK 0x00400058 | |
| 66 | #define FIRE_PCIE_B_MEM32_OFFSET_BASE 0x00400060 | |
| 67 | #define FIRE_PCIE_B_MEM32_OFFSET_MASK 0x00400068 | |
| 68 | #define FIRE_PCIE_B_IOCON_OFFSET_BASE 0x00400070 | |
| 69 | #define FIRE_PCIE_B_IOCON_OFFSET_MASK 0x00400078 | |
| 70 | #define FIRE_PCIE_A_MEM64_OFFSET_BASE 0x00400080 | |
| 71 | #define FIRE_PCIE_A_MEM64_OFFSET_MASK 0x00400088 | |
| 72 | #define FIRE_PCIE_B_MEM64_OFFSET_BASE 0x00400090 | |
| 73 | #define FIRE_PCIE_B_MEM64_OFFSET_MASK 0x00400098 | |
| 74 | #define FIRE_FIRE_CONTROL_STATUS 0x00410000 | |
| 75 | #define FIRE_JBUS_PLL 0x00410050 | |
| 76 | #define FIRE_RESET_GENERATION 0x00417010 | |
| 77 | #define FIRE_RESET_SOURCE 0x00417018 | |
| 78 | #define FIRE_GPIO_0_DATA_0 0x00460000 | |
| 79 | #define FIRE_GPIO_0_DATA_1 0x00460008 | |
| 80 | #define FIRE_GPIO_0_DATA_2 0x00460010 | |
| 81 | #define FIRE_GPIO_0_DATA_3 0x00460018 | |
| 82 | #define FIRE_GPIO_0_DATA 0x00460020 | |
| 83 | #define FIRE_GPIO_0_CONTROL 0x00460028 | |
| 84 | #define FIRE_GPIO_1_DATA_0 0x00462000 | |
| 85 | #define FIRE_GPIO_1_DATA_1 0x00462008 | |
| 86 | #define FIRE_GPIO_1_DATA_2 0x00462010 | |
| 87 | #define FIRE_GPIO_1_DATA_3 0x00462018 | |
| 88 | #define FIRE_GPIO_1_DATA 0x00462020 | |
| 89 | #define FIRE_GPIO_1_CONTROL 0x00462028 | |
| 90 | #define FIRE_EBUS_EPROM_TIMING 0x00464000 | |
| 91 | #define FIRE_EBUS_CS1_TIMING 0x00464008 | |
| 92 | #define FIRE_EBUS_CS2_TIMING 0x00464010 | |
| 93 | #define FIRE_EBUS_CS3_TIMING 0x00464018 | |
| 94 | #define FIRE_I2C0_MONITOR_REGISTER 0x00466000 | |
| 95 | #define FIRE_I2C0_DATA_DRIVE_REGISTER 0x00466008 | |
| 96 | #define FIRE_I2C0_CLK_DRIVE_REGISTER 0x00466010 | |
| 97 | #define FIRE_I2C1_MONITOR_REGISTER 0x00468000 | |
| 98 | #define FIRE_I2C1_DATA_DRIVE_REGISTER 0x00468008 | |
| 99 | #define FIRE_I2C1_CLK_DRIVE_REGISTER 0x00468010 | |
| 100 | #define FIRE_A_RING_SLOW_ONLY 0x00470000 | |
| 101 | #define FIRE_B_RING_SLOW_ONLY 0x00470008 | |
| 102 | #define FIRE_JBUS_PAR_CTL 0x00470010 | |
| 103 | #define FIRE_JBUS_SCRATCH_1 0x00470018 | |
| 104 | #define FIRE_JBUS_SCRATCH_2 0x00470020 | |
| 105 | #define FIRE_JBUS_J_ERR_EN 0x00470028 | |
| 106 | #define FIRE_JBC_ERROR_LOG_EN_REG 0x00471000 | |
| 107 | #define FIRE_JBC_ERROR_INT_EN_REG 0x00471008 | |
| 108 | #define FIRE_JBC_ENABLED_ERROR_STATUS_REG 0x00471010 | |
| 109 | #define FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS 0x00471018 | |
| 110 | #define FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS 0x00471020 | |
| 111 | #define FIRE_JBC_FATAL_RESET_ENABLE_REG 0x00471028 | |
| 112 | #define FIRE_JBCINT_IN_TRAN_ERROR_LOG_REG 0x00471030 | |
| 113 | #define FIRE_JBCINT_IN_STATE_ERROR_LOG_REG 0x00471038 | |
| 114 | #define FIRE_JBCINT_OUT_TRAN_ERROR_LOG_REG 0x00471040 | |
| 115 | #define FIRE_JBCINT_OUT_STATE_ERROR_LOG_REG 0x00471048 | |
| 116 | #define FIRE_FATAL_ERROR_LOG_REG_1 0x00471050 | |
| 117 | #define FIRE_FATAL_STATE_ERROR_LOG_REG 0x00471058 | |
| 118 | #define FIRE_MERGE_TRAN_ERROR_LOG_REG 0x00471060 | |
| 119 | #define FIRE_DMCINT_ODCD_ERROR_LOG_REG 0x00471068 | |
| 120 | #define FIRE_DMCINT_IDC_ERROR_LOG_REG 0x00471070 | |
| 121 | #define FIRE_CSR_ERROR_LOG_REG 0x00471078 | |
| 122 | #define FIRE_JBC_INTERRUPT_MASK_REG 0x00471800 | |
| 123 | #define FIRE_JBC_INTERRUPT_STATUS_REG 0x00471808 | |
| 124 | #define FIRE_JBC_PERF_CNTRL 0x00472000 | |
| 125 | #define FIRE_JBC_PERF_CNT0 0x00472008 | |
| 126 | #define FIRE_JBC_PERF_CNT1 0x00472010 | |
| 127 | #define FIRE_JBC_DBG_SEL_A_REG 0x00473000 | |
| 128 | #define FIRE_JBC_DBG_SEL_B_REG 0x00473008 | |
| 129 | #define FIRE_JBUS_DEVICE_ID_RESET_VALUE 0xfc00000000390000 | |
| 130 | #define FIRE_EBUS_OFFSET_BASE_RESET_VALUE 0x8000000ff0000000 | |
| 131 | #define FIRE_EBUS_OFFSET_MASK_RESET_VALUE 0x000007fff8000000 | |
| 132 | #define FIRE_PCIE_A_MEM32_OFFSET_BASE_RESET_VALUE 0x0000000000000000 | |
| 133 | #define FIRE_PCIE_A_MEM32_OFFSET_MASK_RESET_VALUE 0x000007f000000000 | |
| 134 | #define FIRE_PCIE_A_IOCON_OFFSET_BASE_RESET_VALUE 0x0000000000000000 | |
| 135 | #define FIRE_PCIE_A_IOCON_OFFSET_MASK_RESET_VALUE 0x000007f000000000 | |
| 136 | #define FIRE_PCIE_B_MEM32_OFFSET_BASE_RESET_VALUE 0x0000000000000000 | |
| 137 | #define FIRE_PCIE_B_MEM32_OFFSET_MASK_RESET_VALUE 0x000007f000000000 | |
| 138 | #define FIRE_PCIE_B_IOCON_OFFSET_BASE_RESET_VALUE 0x0000000000000000 | |
| 139 | #define FIRE_PCIE_B_IOCON_OFFSET_MASK_RESET_VALUE 0x000007f000000000 | |
| 140 | #define FIRE_PCIE_A_MEM64_OFFSET_BASE_RESET_VALUE 0x0000000000000000 | |
| 141 | #define FIRE_PCIE_A_MEM64_OFFSET_MASK_RESET_VALUE 0x000007f000000000 | |
| 142 | #define FIRE_PCIE_B_MEM64_OFFSET_BASE_RESET_VALUE 0x0000000000000000 | |
| 143 | #define FIRE_PCIE_B_MEM64_OFFSET_MASK_RESET_VALUE 0x000007f000000000 | |
| 144 | #define FIRE_FIRE_CONTROL_STATUS_RESET_VALUE 0x000007f0038d6000 | |
| 145 | #define FIRE_JBUS_PLL_RESET_VALUE 0x0000000000000006 | |
| 146 | #define FIRE_RESET_GENERATION_RESET_VALUE 0x0000000000000000 | |
| 147 | #define FIRE_RESET_SOURCE_RESET_VALUE 0x0000000000000000 | |
| 148 | #define FIRE_GPIO_0_DATA_0_RESET_VALUE 0x0000000000000000 | |
| 149 | #define FIRE_GPIO_0_DATA_1_RESET_VALUE 0x0000000000000000 | |
| 150 | #define FIRE_GPIO_0_DATA_2_RESET_VALUE 0x0000000000000000 | |
| 151 | #define FIRE_GPIO_0_DATA_3_RESET_VALUE 0x0000000000000000 | |
| 152 | #define FIRE_GPIO_0_DATA_RESET_VALUE 0x0000000000000000 | |
| 153 | #define FIRE_GPIO_0_CONTROL_RESET_VALUE 0x0000000000000000 | |
| 154 | #define FIRE_GPIO_1_DATA_0_RESET_VALUE 0x0000000000000000 | |
| 155 | #define FIRE_GPIO_1_DATA_1_RESET_VALUE 0x0000000000000000 | |
| 156 | #define FIRE_GPIO_1_DATA_2_RESET_VALUE 0x0000000000000000 | |
| 157 | #define FIRE_GPIO_1_DATA_3_RESET_VALUE 0x0000000000000000 | |
| 158 | #define FIRE_GPIO_1_DATA_RESET_VALUE 0x0000000000000000 | |
| 159 | #define FIRE_GPIO_1_CONTROL_RESET_VALUE 0x0000000000000000 | |
| 160 | #define FIRE_EBUS_EPROM_TIMING_RESET_VALUE 0x000000fad5abf5f7 | |
| 161 | #define FIRE_EBUS_CS1_TIMING_RESET_VALUE 0x000000fad5abf5f7 | |
| 162 | #define FIRE_EBUS_CS2_TIMING_RESET_VALUE 0x000000fad5abf5f7 | |
| 163 | #define FIRE_EBUS_CS3_TIMING_RESET_VALUE 0x000000fad5abf5f7 | |
| 164 | #define FIRE_I2C0_MONITOR_REGISTER_RESET_VALUE 0x0000000000000000 | |
| 165 | #define FIRE_I2C0_DATA_DRIVE_REGISTER_RESET_VALUE 0x0000000000000001 | |
| 166 | #define FIRE_I2C0_CLK_DRIVE_REGISTER_RESET_VALUE 0x0000000000000001 | |
| 167 | #define FIRE_I2C1_MONITOR_REGISTER_RESET_VALUE 0x0000000000000000 | |
| 168 | #define FIRE_I2C1_DATA_DRIVE_REGISTER_RESET_VALUE 0x0000000000000001 | |
| 169 | #define FIRE_I2C1_CLK_DRIVE_REGISTER_RESET_VALUE 0x0000000000000001 | |
| 170 | #define FIRE_A_RING_SLOW_ONLY_RESET_VALUE 0x0000000000000000 | |
| 171 | #define FIRE_B_RING_SLOW_ONLY_RESET_VALUE 0x0000000000000000 | |
| 172 | #define FIRE_JBUS_PAR_CTL_RESET_VALUE 0x0000000000000000 | |
| 173 | #define FIRE_JBUS_SCRATCH_1_RESET_VALUE 0x0000000000000000 | |
| 174 | #define FIRE_JBUS_SCRATCH_2_RESET_VALUE 0x0000000000000000 | |
| 175 | #define FIRE_JBUS_J_ERR_EN_RESET_VALUE 0x3fffffff1fffffff | |
| 176 | #define FIRE_JBC_ERROR_LOG_EN_REG_RESET_VALUE 0x000000003fffffff | |
| 177 | #define FIRE_JBC_ERROR_INT_EN_REG_RESET_VALUE 0x0000000000000000 | |
| 178 | #define FIRE_JBC_ENABLED_ERROR_STATUS_REG_RESET_VALUE 0x0000000000000000 | |
| 179 | #define FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 180 | #define FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 181 | #define FIRE_JBC_FATAL_RESET_ENABLE_REG_RESET_VALUE 0x0000000000000000 | |
| 182 | #define FIRE_JBCINT_IN_TRAN_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 183 | #define FIRE_JBCINT_IN_STATE_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 184 | #define FIRE_JBCINT_OUT_TRAN_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 185 | #define FIRE_JBCINT_OUT_STATE_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 186 | #define FIRE_FATAL_ERROR_LOG_REG_1_RESET_VALUE 0x0000000000000000 | |
| 187 | #define FIRE_FATAL_STATE_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 188 | #define FIRE_MERGE_TRAN_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 189 | #define FIRE_DMCINT_ODCD_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 190 | #define FIRE_DMCINT_IDC_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 191 | #define FIRE_CSR_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 192 | #define FIRE_JBC_INTERRUPT_MASK_REG_RESET_VALUE 0x0000000000000000 | |
| 193 | #define FIRE_JBC_INTERRUPT_STATUS_REG_RESET_VALUE 0x0000000000000000 | |
| 194 | #define FIRE_JBC_PERF_CNTRL_RESET_VALUE 0x0000000000000000 | |
| 195 | #define FIRE_JBC_PERF_CNT0_RESET_VALUE 0x0000000000000000 | |
| 196 | #define FIRE_JBC_PERF_CNT1_RESET_VALUE 0x0000000000000000 | |
| 197 | #define FIRE_JBC_DBG_SEL_A_REG_RESET_VALUE 0x0000000000000000 | |
| 198 | #define FIRE_JBC_DBG_SEL_B_REG_RESET_VALUE 0x0000000000000000 | |
| 199 | #define FIRE_DLC_IMU_ISS_INTERRUPT_MAPPING(n) (0x00001000+(8*n)) | |
| 200 | #define FIRE_DLC_IMU_ISS_CLR_INT_REG(n) (0x00001400+(8*n)) | |
| 201 | #define FIRE_DLC_IMU_ISS_INTERRUPT_RETRY_TIMER 0x00001a00 | |
| 202 | #define FIRE_DLC_IMU_ISS_INTERRUPT_STATE_STATUS_1 0x00001a10 | |
| 203 | #define FIRE_DLC_IMU_ISS_INTERRUPT_STATE_STATUS_2 0x00001a18 | |
| 204 | #define FIRE_DLC_IMU_RDS_INTX_INTX_STATUS_REG 0x0000b000 | |
| 205 | #define FIRE_DLC_IMU_RDS_INTX_INT_A_INT_CLR_REG 0x0000b008 | |
| 206 | #define FIRE_DLC_IMU_RDS_INTX_INT_B_INT_CLR_REG 0x0000b010 | |
| 207 | #define FIRE_DLC_IMU_RDS_INTX_INT_C_INT_CLR_REG 0x0000b018 | |
| 208 | #define FIRE_DLC_IMU_RDS_INTX_INT_D_INT_CLR_REG 0x0000b020 | |
| 209 | #define FIRE_DLC_IMU_EQS_EQ_BASE_ADDRESS 0x00010000 | |
| 210 | #define FIRE_DLC_IMU_EQS_EQ_CTRL_SET(n) (0x00011000+(8*n)) | |
| 211 | #define FIRE_DLC_IMU_EQS_EQ_CTRL_CLR(n) (0x00011200+(8*n)) | |
| 212 | #define FIRE_DLC_IMU_EQS_EQ_STATE(n) (0x00011400+(8*n)) | |
| 213 | #define FIRE_DLC_IMU_EQS_EQ_TAIL(n) (0x00011600+(8*n)) | |
| 214 | #define FIRE_DLC_IMU_EQS_EQ_HEAD(n) (0x00011800+(8*n)) | |
| 215 | #define FIRE_DLC_IMU_RDS_MSI_MSI_MAPPING(n) (0x00020000+(8*n)) | |
| 216 | #define FIRE_DLC_IMU_RDS_MSI_MSI_CLEAR_REG(n) (0x00028000+(8*n)) | |
| 217 | #define FIRE_DLC_IMU_RDS_MSI_INT_MONDO_DATA_0_REG 0x0002c000 | |
| 218 | #define FIRE_DLC_IMU_RDS_MSI_INT_MONDO_DATA_1_REG 0x0002c008 | |
| 219 | #define FIRE_DLC_IMU_RDS_MESS_ERR_COR_MAPPING 0x00030000 | |
| 220 | #define FIRE_DLC_IMU_RDS_MESS_ERR_NONFATAL_MAPPING 0x00030008 | |
| 221 | #define FIRE_DLC_IMU_RDS_MESS_ERR_FATAL_MAPPING 0x00030010 | |
| 222 | #define FIRE_DLC_IMU_RDS_MESS_PM_PME_MAPPING 0x00030018 | |
| 223 | #define FIRE_DLC_IMU_RDS_MESS_PME_TO_ACK_MAPPING 0x00030020 | |
| 224 | #define FIRE_DLC_IMU_ICS_IMU_ERROR_LOG_EN_REG 0x00031000 | |
| 225 | #define FIRE_DLC_IMU_ICS_IMU_INT_EN_REG 0x00031008 | |
| 226 | #define FIRE_DLC_IMU_ICS_IMU_ENABLED_ERROR_STATUS_REG 0x00031010 | |
| 227 | #define FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS 0x00031018 | |
| 228 | #define FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS 0x00031020 | |
| 229 | #define FIRE_DLC_IMU_ICS_IMU_RDS_ERROR_LOG_REG 0x00031028 | |
| 230 | #define FIRE_DLC_IMU_ICS_IMU_SCS_ERROR_LOG_REG 0x00031030 | |
| 231 | #define FIRE_DLC_IMU_ICS_IMU_EQS_ERROR_LOG_REG 0x00031038 | |
| 232 | #define FIRE_DLC_IMU_ICS_DMC_INTERRUPT_MASK_REG 0x00031800 | |
| 233 | #define FIRE_DLC_IMU_ICS_DMC_INTERRUPT_STATUS_REG 0x00031808 | |
| 234 | #define FIRE_DLC_IMU_ICS_MULTI_CORE_ERROR_STATUS_REG 0x00031810 | |
| 235 | #define FIRE_DLC_IMU_ICS_IMU_PERF_CNTRL 0x00032000 | |
| 236 | #define FIRE_DLC_IMU_ICS_IMU_PERF_CNT0 0x00032008 | |
| 237 | #define FIRE_DLC_IMU_ICS_IMU_PERF_CNT1 0x00032010 | |
| 238 | #define FIRE_DLC_IMU_ICS_MSI_32_ADDR_REG 0x00034000 | |
| 239 | #define FIRE_DLC_IMU_ICS_MSI_64_ADDR_REG 0x00034008 | |
| 240 | #define FIRE_DLC_IMU_ICS_MEM_64_PCIE_OFFSET_REG 0x00034018 | |
| 241 | #define FIRE_DLC_MMU_CTL 0x00040000 | |
| 242 | #define FIRE_DLC_MMU_TSB 0x00040008 | |
| 243 | #define FIRE_DLC_MMU_FSH 0x00040100 | |
| 244 | #define FIRE_DLC_MMU_INV 0x00040108 | |
| 245 | #define FIRE_DLC_MMU_LOG 0x00041000 | |
| 246 | #define FIRE_DLC_MMU_INT_EN 0x00041008 | |
| 247 | #define FIRE_DLC_MMU_EN_ERR 0x00041010 | |
| 248 | #define FIRE_DLC_MMU_ERR_RW1C_ALIAS 0x00041018 | |
| 249 | #define FIRE_DLC_MMU_ERR_RW1S_ALIAS 0x00041020 | |
| 250 | #define FIRE_DLC_MMU_FLTA 0x00041028 | |
| 251 | #define FIRE_DLC_MMU_FLTS 0x00041030 | |
| 252 | #define FIRE_DLC_MMU_PRFC 0x00042000 | |
| 253 | #define FIRE_DLC_MMU_PRF0 0x00042008 | |
| 254 | #define FIRE_DLC_MMU_PRF1 0x00042010 | |
| 255 | #define FIRE_DLC_MMU_VTB(n) (0x00046000+(8*n)) | |
| 256 | #define FIRE_DLC_MMU_PTB(n) (0x00047000+(8*n)) | |
| 257 | #define FIRE_DLC_MMU_TDB(n) (0x00048000+(8*n)) | |
| 258 | #define FIRE_DLC_ILU_CIB_ILU_LOG_EN 0x00051000 | |
| 259 | #define FIRE_DLC_ILU_CIB_ILU_INT_EN 0x00051008 | |
| 260 | #define FIRE_DLC_ILU_CIB_ILU_EN_ERR 0x00051010 | |
| 261 | #define FIRE_DLC_ILU_CIB_ILU_LOG_ERR_RW1C_ALIAS 0x00051018 | |
| 262 | #define FIRE_DLC_ILU_CIB_ILU_LOG_ERR_RW1S_ALIAS 0x00051020 | |
| 263 | #define FIRE_DLC_ILU_CIB_PEC_INT_EN 0x00051800 | |
| 264 | #define FIRE_DLC_ILU_CIB_PEC_EN_ERR 0x00051808 | |
| 265 | #define FIRE_DLC_CRU_DMC_DBG_SEL_A_REG 0x00053000 | |
| 266 | #define FIRE_DLC_CRU_DMC_DBG_SEL_B_REG 0x00053008 | |
| 267 | #define FIRE_DLC_CRU_DMC_PCIE_CFG 0x00053100 | |
| 268 | #define FIRE_DLC_PSB_PSB_DMA(n) (0x00060000+(8*n)) | |
| 269 | #define FIRE_DLC_PSB_PSB_PIO(n) (0x00064000+(8*n)) | |
| 270 | #define FIRE_DLC_TSB_TSB_DMA(n) (0x00070000+(8*n)) | |
| 271 | #define FIRE_PLC_TLU_CTB_TLR_TLU_CTL 0x00080000 | |
| 272 | #define FIRE_PLC_TLU_CTB_TLR_TLU_STS 0x00080008 | |
| 273 | #define FIRE_PLC_TLU_CTB_TLR_TRN_OFF 0x00080010 | |
| 274 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ICI 0x00080018 | |
| 275 | #define FIRE_PLC_TLU_CTB_TLR_TLU_DIAG 0x00080100 | |
| 276 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ECC 0x00080200 | |
| 277 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ECL 0x00080208 | |
| 278 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ERB 0x00080210 | |
| 279 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ICA 0x00080218 | |
| 280 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ICR 0x00080220 | |
| 281 | #define FIRE_PLC_TLU_CTB_TLR_OE_LOG 0x00081000 | |
| 282 | #define FIRE_PLC_TLU_CTB_TLR_OE_INT_EN 0x00081008 | |
| 283 | #define FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR 0x00081010 | |
| 284 | #define FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS 0x00081018 | |
| 285 | #define FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1S_ALIAS 0x00081020 | |
| 286 | #define FIRE_PLC_TLU_CTB_TLR_ROE_HDR1 0x00081028 | |
| 287 | #define FIRE_PLC_TLU_CTB_TLR_ROE_HDR2 0x00081030 | |
| 288 | #define FIRE_PLC_TLU_CTB_TLR_TOE_HDR1 0x00081038 | |
| 289 | #define FIRE_PLC_TLU_CTB_TLR_TOE_HDR2 0x00081040 | |
| 290 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRFC 0x00082000 | |
| 291 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRF0 0x00082008 | |
| 292 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRF1 0x00082010 | |
| 293 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRF2 0x00082018 | |
| 294 | #define FIRE_PLC_TLU_CTB_TLR_TLU_DBG_SEL_A 0x00083000 | |
| 295 | #define FIRE_PLC_TLU_CTB_TLR_TLU_DBG_SEL_B 0x00083008 | |
| 296 | #define FIRE_PLC_TLU_CTB_TLR_DEV_CAP 0x00090000 | |
| 297 | #define FIRE_PLC_TLU_CTB_TLR_DEV_CTL 0x00090008 | |
| 298 | #define FIRE_PLC_TLU_CTB_TLR_DEV_STS 0x00090010 | |
| 299 | #define FIRE_PLC_TLU_CTB_TLR_LNK_CAP 0x00090018 | |
| 300 | #define FIRE_PLC_TLU_CTB_TLR_LNK_CTL 0x00090020 | |
| 301 | #define FIRE_PLC_TLU_CTB_TLR_LNK_STS 0x00090028 | |
| 302 | #define FIRE_PLC_TLU_CTB_TLR_SLT_CAP 0x00090030 | |
| 303 | #define FIRE_PLC_TLU_CTB_TLR_UE_LOG 0x00091000 | |
| 304 | #define FIRE_PLC_TLU_CTB_TLR_UE_INT_EN 0x00091008 | |
| 305 | #define FIRE_PLC_TLU_CTB_TLR_UE_EN_ERR 0x00091010 | |
| 306 | #define FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS 0x00091018 | |
| 307 | #define FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1S_ALIAS 0x00091020 | |
| 308 | #define FIRE_PLC_TLU_CTB_TLR_RUE_HDR1 0x00091028 | |
| 309 | #define FIRE_PLC_TLU_CTB_TLR_RUE_HDR2 0x00091030 | |
| 310 | #define FIRE_PLC_TLU_CTB_TLR_TUE_HDR1 0x00091038 | |
| 311 | #define FIRE_PLC_TLU_CTB_TLR_TUE_HDR2 0x00091040 | |
| 312 | #define FIRE_PLC_TLU_CTB_TLR_CE_LOG 0x000a1000 | |
| 313 | #define FIRE_PLC_TLU_CTB_TLR_CE_INT_EN 0x000a1008 | |
| 314 | #define FIRE_PLC_TLU_CTB_TLR_CE_EN_ERR 0x000a1010 | |
| 315 | #define FIRE_PLC_TLU_CTB_TLR_CE_ERR_RW1C_ALIAS 0x000a1018 | |
| 316 | #define FIRE_PLC_TLU_CTB_TLR_CE_ERR_RW1S_ALIAS 0x000a1020 | |
| 317 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ID 0x000e2000 | |
| 318 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RST 0x000e2008 | |
| 319 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_DBG_STAT 0x000e2010 | |
| 320 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_DBG_CONFIG 0x000e2018 | |
| 321 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CNTL 0x000e2020 | |
| 322 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_STATUS 0x000e2028 | |
| 323 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_INTERRUPT_STATUS 0x000e2040 | |
| 324 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_INTERRUPT_MASK 0x000e2048 | |
| 325 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1_SEL 0x000e2100 | |
| 326 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR_CTL 0x000e2110 | |
| 327 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1 0x000e2120 | |
| 328 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1_TEST 0x000e2128 | |
| 329 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR2 0x000e2130 | |
| 330 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR2_TEST 0x000e2138 | |
| 331 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_CONFIG 0x000e2200 | |
| 332 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_STAT 0x000e2208 | |
| 333 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT 0x000e2210 | |
| 334 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_TST 0x000e2218 | |
| 335 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_MSK 0x000e2220 | |
| 336 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_FC_UP_CNTL 0x000e2240 | |
| 337 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_FC_UP_TO_VAL 0x000e2260 | |
| 338 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_VCO_FC_CNTL_UP_TMR0 0x000e2268 | |
| 339 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_VCO_FC_CNTL_UP_TMR1 0x000e2270 | |
| 340 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ACKNAK_LATENCY 0x000e2400 | |
| 341 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ACKNAK_LATENCY_TMR 0x000e2408 | |
| 342 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RPLAY_TMR_THHOLD 0x000e2410 | |
| 343 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RPLAY_TMR 0x000e2418 | |
| 344 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RPLAY_NUM_STAT 0x000e2420 | |
| 345 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_BUFF_MAX_ADDR 0x000e2428 | |
| 346 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_FIFO_PTR 0x000e2430 | |
| 347 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_FIFO_RW_PTR 0x000e2438 | |
| 348 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_FIFO_CRDT 0x000e2440 | |
| 349 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNTR 0x000e2448 | |
| 350 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ACK_SND_SEQ_NUM 0x000e2450 | |
| 351 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR 0x000e2458 | |
| 352 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNT_FIFO_PTR 0x000e2460 | |
| 353 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNT_RW_PTR 0x000e2468 | |
| 354 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_TST_CNTL 0x000e2470 | |
| 355 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_ADDR_CNTL 0x000e2480 | |
| 356 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD0 0x000e2488 | |
| 357 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD1 0x000e2490 | |
| 358 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD2 0x000e2498 | |
| 359 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD3 0x000e24a0 | |
| 360 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD4 0x000e24a8 | |
| 361 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_CNT 0x000e24c0 | |
| 362 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_BUFF_CNT 0x000e24c8 | |
| 363 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_BUFF_BTM 0x000e24d0 | |
| 364 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_NXT_RCV_SEQ_CNTR 0x000e2500 | |
| 365 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_DLLP_RCVD 0x000e2508 | |
| 366 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_LINK_TEST_CNTL 0x000e2510 | |
| 367 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_CNFG 0x000e2600 | |
| 368 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_STAT 0x000e2608 | |
| 369 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT 0x000e2610 | |
| 370 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_TST 0x000e2618 | |
| 371 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_MSK 0x000e2620 | |
| 372 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_CNFG 0x000e2680 | |
| 373 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_STAT1 0x000e2688 | |
| 374 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_STAT2 0x000e2690 | |
| 375 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_STAT3 0x000e2698 | |
| 376 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT 0x000e26a0 | |
| 377 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_TST 0x000e26a8 | |
| 378 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_MSK 0x000e26b0 | |
| 379 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_CONFIG 0x000e2700 | |
| 380 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_STAT 0x000e2708 | |
| 381 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT 0x000e2710 | |
| 382 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_TST 0x000e2718 | |
| 383 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_MSK 0x000e2720 | |
| 384 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_STS_2 0x000e2728 | |
| 385 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG1 0x000e2780 | |
| 386 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG2 0x000e2788 | |
| 387 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG3 0x000e2790 | |
| 388 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG4 0x000e2798 | |
| 389 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG5 0x000e27a0 | |
| 390 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_STAT1 0x000e27a8 | |
| 391 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_STAT2 0x000e27b0 | |
| 392 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_INT 0x000e27b8 | |
| 393 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_TST 0x000e27c0 | |
| 394 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_MSK 0x000e27c8 | |
| 395 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_STAT_WR_EN 0x000e27d0 | |
| 396 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG1 0x000e2800 | |
| 397 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG2 0x000e2808 | |
| 398 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG3 0x000e2810 | |
| 399 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG4 0x000e2818 | |
| 400 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_STAT 0x000e2820 | |
| 401 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_INT 0x000e2828 | |
| 402 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_TST 0x000e2830 | |
| 403 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_MSK 0x000e2838 | |
| 404 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_PDWN1 0x000e2840 | |
| 405 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_PDWN2 0x000e2848 | |
| 406 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG5 0x000e2850 | |
| 407 | #define FIRE_DLC_IMU_ISS_INTERRUPT_MAPPING_RESET_VALUE 0x0000000000000000 | |
| 408 | #define FIRE_DLC_IMU_ISS_CLR_INT_REG_RESET_VALUE 0x0000000000000000 | |
| 409 | #define FIRE_DLC_IMU_ISS_INTERRUPT_RETRY_TIMER_RESET_VALUE 0x0000000000000000 | |
| 410 | #define FIRE_DLC_IMU_ISS_INTERRUPT_STATE_STATUS_1_RESET_VALUE 0x0000000000000000 | |
| 411 | #define FIRE_DLC_IMU_ISS_INTERRUPT_STATE_STATUS_2_RESET_VALUE 0x0000000000000000 | |
| 412 | #define FIRE_DLC_IMU_RDS_INTX_INTX_STATUS_REG_RESET_VALUE 0x0000000000000000 | |
| 413 | #define FIRE_DLC_IMU_RDS_INTX_INT_A_INT_CLR_REG_RESET_VALUE 0x0000000000000000 | |
| 414 | #define FIRE_DLC_IMU_RDS_INTX_INT_B_INT_CLR_REG_RESET_VALUE 0x0000000000000000 | |
| 415 | #define FIRE_DLC_IMU_RDS_INTX_INT_C_INT_CLR_REG_RESET_VALUE 0x0000000000000000 | |
| 416 | #define FIRE_DLC_IMU_RDS_INTX_INT_D_INT_CLR_REG_RESET_VALUE 0x0000000000000000 | |
| 417 | #define FIRE_DLC_IMU_EQS_EQ_BASE_ADDRESS_RESET_VALUE 0x0000000000000000 | |
| 418 | #define FIRE_DLC_IMU_EQS_EQ_CTRL_SET_RESET_VALUE 0x0000000000000000 | |
| 419 | #define FIRE_DLC_IMU_EQS_EQ_CTRL_CLR_RESET_VALUE 0x0000000000000000 | |
| 420 | #define FIRE_DLC_IMU_EQS_EQ_STATE_RESET_VALUE 0x0000000000000001 | |
| 421 | #define FIRE_DLC_IMU_EQS_EQ_TAIL_RESET_VALUE 0x0000000000000000 | |
| 422 | #define FIRE_DLC_IMU_EQS_EQ_HEAD_RESET_VALUE 0x0000000000000000 | |
| 423 | #define FIRE_DLC_IMU_RDS_MSI_MSI_MAPPING_RESET_VALUE 0x0000000000000000 | |
| 424 | #define FIRE_DLC_IMU_RDS_MSI_MSI_CLEAR_REG_RESET_VALUE 0x0000000000000000 | |
| 425 | #define FIRE_DLC_IMU_RDS_MSI_INT_MONDO_DATA_0_REG_RESET_VALUE 0x0000000000000000 | |
| 426 | #define FIRE_DLC_IMU_RDS_MSI_INT_MONDO_DATA_1_REG_RESET_VALUE 0x0000000000000000 | |
| 427 | #define FIRE_DLC_IMU_RDS_MESS_ERR_COR_MAPPING_RESET_VALUE 0x0000000000000000 | |
| 428 | #define FIRE_DLC_IMU_RDS_MESS_ERR_NONFATAL_MAPPING_RESET_VALUE 0x0000000000000000 | |
| 429 | #define FIRE_DLC_IMU_RDS_MESS_ERR_FATAL_MAPPING_RESET_VALUE 0x0000000000000000 | |
| 430 | #define FIRE_DLC_IMU_RDS_MESS_PM_PME_MAPPING_RESET_VALUE 0x0000000000000000 | |
| 431 | #define FIRE_DLC_IMU_RDS_MESS_PME_TO_ACK_MAPPING_RESET_VALUE 0x0000000000000000 | |
| 432 | #define FIRE_DLC_IMU_ICS_IMU_ERROR_LOG_EN_REG_RESET_VALUE 0x00000000000007ff | |
| 433 | #define FIRE_DLC_IMU_ICS_IMU_INT_EN_REG_RESET_VALUE 0x0000000000000000 | |
| 434 | #define FIRE_DLC_IMU_ICS_IMU_ENABLED_ERROR_STATUS_REG_RESET_VALUE 0x0000000000000000 | |
| 435 | #define FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 436 | #define FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 437 | #define FIRE_DLC_IMU_ICS_IMU_RDS_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 438 | #define FIRE_DLC_IMU_ICS_IMU_SCS_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 439 | #define FIRE_DLC_IMU_ICS_IMU_EQS_ERROR_LOG_REG_RESET_VALUE 0x0000000000000000 | |
| 440 | #define FIRE_DLC_IMU_ICS_DMC_INTERRUPT_MASK_REG_RESET_VALUE 0x0000000000000000 | |
| 441 | #define FIRE_DLC_IMU_ICS_DMC_INTERRUPT_STATUS_REG_RESET_VALUE 0x0000000000000000 | |
| 442 | #define FIRE_DLC_IMU_ICS_MULTI_CORE_ERROR_STATUS_REG_RESET_VALUE 0x0000000000000000 | |
| 443 | #define FIRE_DLC_IMU_ICS_IMU_PERF_CNTRL_RESET_VALUE 0x0000000000000000 | |
| 444 | #define FIRE_DLC_IMU_ICS_IMU_PERF_CNT0_RESET_VALUE 0x0000000000000000 | |
| 445 | #define FIRE_DLC_IMU_ICS_IMU_PERF_CNT1_RESET_VALUE 0x0000000000000000 | |
| 446 | #define FIRE_DLC_IMU_ICS_MSI_32_ADDR_REG_RESET_VALUE 0x0000000000000000 | |
| 447 | #define FIRE_DLC_IMU_ICS_MSI_64_ADDR_REG_RESET_VALUE 0x0000000000000000 | |
| 448 | #define FIRE_DLC_IMU_ICS_MEM_64_PCIE_OFFSET_REG_RESET_VALUE 0x0000000000000000 | |
| 449 | #define FIRE_DLC_MMU_CTL_RESET_VALUE 0x0000000000000000 | |
| 450 | #define FIRE_DLC_MMU_TSB_RESET_VALUE 0x0000000000000000 | |
| 451 | #define FIRE_DLC_MMU_FSH_RESET_VALUE 0x0000000000000000 | |
| 452 | #define FIRE_DLC_MMU_INV_RESET_VALUE 0x0000000000000000 | |
| 453 | #define FIRE_DLC_MMU_LOG_RESET_VALUE 0x000000000000ffff | |
| 454 | #define FIRE_DLC_MMU_INT_EN_RESET_VALUE 0x0000000000000000 | |
| 455 | #define FIRE_DLC_MMU_EN_ERR_RESET_VALUE 0x0000000000000000 | |
| 456 | #define FIRE_DLC_MMU_ERR_RW1C_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 457 | #define FIRE_DLC_MMU_ERR_RW1S_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 458 | #define FIRE_DLC_MMU_FLTA_RESET_VALUE 0x0000000000000000 | |
| 459 | #define FIRE_DLC_MMU_FLTS_RESET_VALUE 0x0000000000000000 | |
| 460 | #define FIRE_DLC_MMU_PRFC_RESET_VALUE 0x0000000000000000 | |
| 461 | #define FIRE_DLC_MMU_PRF0_RESET_VALUE 0x0000000000000000 | |
| 462 | #define FIRE_DLC_MMU_PRF1_RESET_VALUE 0x0000000000000000 | |
| 463 | #define FIRE_DLC_MMU_VTB_RESET_VALUE 0x0000000000000000 | |
| 464 | #define FIRE_DLC_MMU_PTB_RESET_VALUE 0x0000000000000000 | |
| 465 | #define FIRE_DLC_MMU_TDB_RESET_VALUE 0x0000000000000000 | |
| 466 | #define FIRE_DLC_ILU_CIB_ILU_LOG_EN_RESET_VALUE 0x00000000000000f0 | |
| 467 | #define FIRE_DLC_ILU_CIB_ILU_INT_EN_RESET_VALUE 0x0000000000000000 | |
| 468 | #define FIRE_DLC_ILU_CIB_ILU_EN_ERR_RESET_VALUE 0x0000000000000000 | |
| 469 | #define FIRE_DLC_ILU_CIB_ILU_LOG_ERR_RW1C_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 470 | #define FIRE_DLC_ILU_CIB_ILU_LOG_ERR_RW1S_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 471 | #define FIRE_DLC_ILU_CIB_PEC_INT_EN_RESET_VALUE 0x0000000000000000 | |
| 472 | #define FIRE_DLC_ILU_CIB_PEC_EN_ERR_RESET_VALUE 0x0000000000000000 | |
| 473 | #define FIRE_DLC_CRU_DMC_DBG_SEL_A_REG_RESET_VALUE 0x0000000000000000 | |
| 474 | #define FIRE_DLC_CRU_DMC_DBG_SEL_B_REG_RESET_VALUE 0x0000000000000000 | |
| 475 | #define FIRE_DLC_CRU_DMC_PCIE_CFG_RESET_VALUE 0x0000000000000000 | |
| 476 | #define FIRE_DLC_PSB_PSB_DMA_RESET_VALUE 0x0000000000000000 | |
| 477 | #define FIRE_DLC_PSB_PSB_PIO_RESET_VALUE 0x0000000000000000 | |
| 478 | #define FIRE_DLC_TSB_TSB_DMA_RESET_VALUE 0x0000000000000000 | |
| 479 | #define FIRE_PLC_TLU_CTB_TLR_TLU_CTL_RESET_VALUE 0x0000000000000001 | |
| 480 | #define FIRE_PLC_TLU_CTB_TLR_TLU_STS_RESET_VALUE 0x0000000000000000 | |
| 481 | #define FIRE_PLC_TLU_CTB_TLR_TRN_OFF_RESET_VALUE 0x0000000000000000 | |
| 482 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ICI_RESET_VALUE 0x00000010000200c0 | |
| 483 | #define FIRE_PLC_TLU_CTB_TLR_TLU_DIAG_RESET_VALUE 0x0000000000000000 | |
| 484 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ECC_RESET_VALUE 0x0000000000000000 | |
| 485 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ECL_RESET_VALUE 0x0000000000000000 | |
| 486 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ERB_RESET_VALUE 0x0000000000000000 | |
| 487 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ICA_RESET_VALUE 0x0000000000000000 | |
| 488 | #define FIRE_PLC_TLU_CTB_TLR_TLU_ICR_RESET_VALUE 0x0000000000000000 | |
| 489 | #define FIRE_PLC_TLU_CTB_TLR_OE_LOG_RESET_VALUE 0x0000000000ffffff | |
| 490 | #define FIRE_PLC_TLU_CTB_TLR_OE_INT_EN_RESET_VALUE 0x0000000000000000 | |
| 491 | #define FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR_RESET_VALUE 0x0000000000000000 | |
| 492 | #define FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 493 | #define FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1S_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 494 | #define FIRE_PLC_TLU_CTB_TLR_ROE_HDR1_RESET_VALUE 0x0000000000000000 | |
| 495 | #define FIRE_PLC_TLU_CTB_TLR_ROE_HDR2_RESET_VALUE 0x0000000000000000 | |
| 496 | #define FIRE_PLC_TLU_CTB_TLR_TOE_HDR1_RESET_VALUE 0x0000000000000000 | |
| 497 | #define FIRE_PLC_TLU_CTB_TLR_TOE_HDR2_RESET_VALUE 0x0000000000000000 | |
| 498 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRFC_RESET_VALUE 0x0000000000000000 | |
| 499 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRF0_RESET_VALUE 0x0000000000000000 | |
| 500 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRF1_RESET_VALUE 0x0000000000000000 | |
| 501 | #define FIRE_PLC_TLU_CTB_TLR_TLU_PRF2_RESET_VALUE 0x0000000000000000 | |
| 502 | #define FIRE_PLC_TLU_CTB_TLR_TLU_DBG_SEL_A_RESET_VALUE 0x0000000000000000 | |
| 503 | #define FIRE_PLC_TLU_CTB_TLR_TLU_DBG_SEL_B_RESET_VALUE 0x0000000000000000 | |
| 504 | #define FIRE_PLC_TLU_CTB_TLR_DEV_CAP_RESET_VALUE 0x0000000000000fc2 | |
| 505 | #define FIRE_PLC_TLU_CTB_TLR_DEV_CTL_RESET_VALUE 0x0000000000000000 | |
| 506 | #define FIRE_PLC_TLU_CTB_TLR_DEV_STS_RESET_VALUE 0x0000000000000000 | |
| 507 | #define FIRE_PLC_TLU_CTB_TLR_LNK_CAP_RESET_VALUE 0x0000000000015c81 | |
| 508 | #define FIRE_PLC_TLU_CTB_TLR_LNK_CTL_RESET_VALUE 0x0000000000000000 | |
| 509 | #define FIRE_PLC_TLU_CTB_TLR_LNK_STS_RESET_VALUE 0x0000000000000000 | |
| 510 | #define FIRE_PLC_TLU_CTB_TLR_SLT_CAP_RESET_VALUE 0x0000000000000000 | |
| 511 | #define FIRE_PLC_TLU_CTB_TLR_UE_LOG_RESET_VALUE 0x000000000017f011 | |
| 512 | #define FIRE_PLC_TLU_CTB_TLR_UE_INT_EN_RESET_VALUE 0x0000000000000000 | |
| 513 | #define FIRE_PLC_TLU_CTB_TLR_UE_EN_ERR_RESET_VALUE 0x0000000000000000 | |
| 514 | #define FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 515 | #define FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1S_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 516 | #define FIRE_PLC_TLU_CTB_TLR_RUE_HDR1_RESET_VALUE 0x0000000000000000 | |
| 517 | #define FIRE_PLC_TLU_CTB_TLR_RUE_HDR2_RESET_VALUE 0x0000000000000000 | |
| 518 | #define FIRE_PLC_TLU_CTB_TLR_TUE_HDR1_RESET_VALUE 0x0000000000000000 | |
| 519 | #define FIRE_PLC_TLU_CTB_TLR_TUE_HDR2_RESET_VALUE 0x0000000000000000 | |
| 520 | #define FIRE_PLC_TLU_CTB_TLR_CE_LOG_RESET_VALUE 0x00000000000011c1 | |
| 521 | #define FIRE_PLC_TLU_CTB_TLR_CE_INT_EN_RESET_VALUE 0x0000000000000000 | |
| 522 | #define FIRE_PLC_TLU_CTB_TLR_CE_EN_ERR_RESET_VALUE 0x0000000000000000 | |
| 523 | #define FIRE_PLC_TLU_CTB_TLR_CE_ERR_RW1C_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 524 | #define FIRE_PLC_TLU_CTB_TLR_CE_ERR_RW1S_ALIAS_RESET_VALUE 0x0000000000000000 | |
| 525 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ID_RESET_VALUE 0x0000000000000000 | |
| 526 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RST_RESET_VALUE 0x0000000000000000 | |
| 527 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_DBG_STAT_RESET_VALUE 0x0000000000000000 | |
| 528 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_DBG_CONFIG_RESET_VALUE 0x0000000000000000 | |
| 529 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CNTL_RESET_VALUE 0x0000000000000000 | |
| 530 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_STATUS_RESET_VALUE 0x0000000000000101 | |
| 531 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_INTERRUPT_STATUS_RESET_VALUE 0x0000000000000000 | |
| 532 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_INTERRUPT_MASK_RESET_VALUE 0x0000000000000000 | |
| 533 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1_SEL_RESET_VALUE 0x0000000000000000 | |
| 534 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR_CTL_RESET_VALUE 0x0000000000000000 | |
| 535 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1_RESET_VALUE 0x0000000000000000 | |
| 536 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1_TEST_RESET_VALUE 0x0000000000000000 | |
| 537 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR2_RESET_VALUE 0x0000000000000000 | |
| 538 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR2_TEST_RESET_VALUE 0x0000000000000000 | |
| 539 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_CONFIG_RESET_VALUE 0x0000000000000100 | |
| 540 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_STAT_RESET_VALUE 0x0000000000000001 | |
| 541 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT_RESET_VALUE 0x0000000000000000 | |
| 542 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_TST_RESET_VALUE 0x0000000000000000 | |
| 543 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_MSK_RESET_VALUE 0x0000000000000000 | |
| 544 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_FC_UP_CNTL_RESET_VALUE 0x0000000000000003 | |
| 545 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_FC_UP_TO_VAL_RESET_VALUE 0x0000000000001d4c | |
| 546 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_RESET_VALUE 0x0000000000000000 | |
| 547 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_RESET_VALUE 0x0000000000000000 | |
| 548 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ACKNAK_LATENCY_RESET_VALUE 0x0000000000000030 | |
| 549 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ACKNAK_LATENCY_TMR_RESET_VALUE 0x0000000000000000 | |
| 550 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RPLAY_TMR_THHOLD_RESET_VALUE 0x0000000000000090 | |
| 551 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RPLAY_TMR_RESET_VALUE 0x0000000000000090 | |
| 552 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RPLAY_NUM_STAT_RESET_VALUE 0x0000000000000000 | |
| 553 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RESET_VALUE 0x000000000000157f | |
| 554 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_FIFO_PTR_RESET_VALUE 0x00000000ffff0000 | |
| 555 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_FIFO_RW_PTR_RESET_VALUE 0x0000000000000000 | |
| 556 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_FIFO_CRDT_RESET_VALUE 0x0000000000001580 | |
| 557 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNTR_RESET_VALUE 0x000000000fff0000 | |
| 558 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_ACK_SND_SEQ_NUM_RESET_VALUE 0x0000000000000fff | |
| 559 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_RESET_VALUE 0x0000000000000157 | |
| 560 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNT_FIFO_PTR_RESET_VALUE 0x000000000fff0000 | |
| 561 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_CNT_RW_PTR_RESET_VALUE 0x0000000000000000 | |
| 562 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_TST_CNTL_RESET_VALUE 0x0000000000000000 | |
| 563 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_ADDR_CNTL_RESET_VALUE 0x0000000000000000 | |
| 564 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD0_RESET_VALUE 0x0000000000000000 | |
| 565 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD1_RESET_VALUE 0x0000000000000000 | |
| 566 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD2_RESET_VALUE 0x0000000000000000 | |
| 567 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD3_RESET_VALUE 0x0000000000000000 | |
| 568 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_MEM_LD4_RESET_VALUE 0x0000000000000000 | |
| 569 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RTRY_CNT_RESET_VALUE 0x0000000000000000 | |
| 570 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_BUFF_CNT_RESET_VALUE 0x0000000000000000 | |
| 571 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_SEQ_BUFF_BTM_RESET_VALUE 0x0000000000000000 | |
| 572 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_NXT_RCV_SEQ_CNTR_RESET_VALUE 0x0000000000000001 | |
| 573 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_DLLP_RCVD_RESET_VALUE 0x0000000000000000 | |
| 574 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_LINK_TEST_CNTL_RESET_VALUE 0x0000000000000000 | |
| 575 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_CNFG_RESET_VALUE 0x0000000000000010 | |
| 576 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_STAT_RESET_VALUE 0x0000000000000000 | |
| 577 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT_RESET_VALUE 0x0000000000000000 | |
| 578 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_TST_RESET_VALUE 0x0000000000000000 | |
| 579 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_MSK_RESET_VALUE 0x0000000000000000 | |
| 580 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_CNFG_RESET_VALUE 0x0000000000000000 | |
| 581 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_STAT1_RESET_VALUE 0x0000000000000000 | |
| 582 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_STAT2_RESET_VALUE 0x0000000000000000 | |
| 583 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_STAT3_RESET_VALUE 0x0000000000000000 | |
| 584 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT_RESET_VALUE 0x0000000000000000 | |
| 585 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_TST_RESET_VALUE 0x0000000000000000 | |
| 586 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_MSK_RESET_VALUE 0x000000008000000f | |
| 587 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_CONFIG_RESET_VALUE 0x0000000000000000 | |
| 588 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_STAT_RESET_VALUE 0x0000000073000010 | |
| 589 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT_RESET_VALUE 0x0000000000000000 | |
| 590 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_TST_RESET_VALUE 0x0000000000000000 | |
| 591 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_MSK_RESET_VALUE 0x0000000080000fff | |
| 592 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_STS_2_RESET_VALUE 0x0000000000000000 | |
| 593 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG1_RESET_VALUE 0x0000000000001905 | |
| 594 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG2_RESET_VALUE 0x00000000002dc6c0 | |
| 595 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG3_RESET_VALUE 0x000000000007a120 | |
| 596 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG4_RESET_VALUE 0x0000000000028c00 | |
| 597 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CONFIG5_RESET_VALUE 0x0000000000000000 | |
| 598 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_STAT1_RESET_VALUE 0x0000000000000000 | |
| 599 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_STAT2_RESET_VALUE 0x0000000000000000 | |
| 600 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_INT_RESET_VALUE 0x0000000000000000 | |
| 601 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_TST_RESET_VALUE 0x0000000000000000 | |
| 602 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_MSK_RESET_VALUE 0x000000008000ffff | |
| 603 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_STAT_WR_EN_RESET_VALUE 0x0000000000000000 | |
| 604 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG1_RESET_VALUE 0x0000000000089019 | |
| 605 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG2_RESET_VALUE 0x00000000a1a3e175 | |
| 606 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG3_RESET_VALUE 0x00000000004401f4 | |
| 607 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG4_RESET_VALUE 0x000000000001e848 | |
| 608 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_STAT_RESET_VALUE 0x00000000ffff0000 | |
| 609 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_INT_RESET_VALUE 0x0000000000000000 | |
| 610 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_TST_RESET_VALUE 0x0000000000000000 | |
| 611 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_MSK_RESET_VALUE 0x0000000080ffffff | |
| 612 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_PDWN1_RESET_VALUE 0x0000000000000000 | |
| 613 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_PDWN2_RESET_VALUE 0x0000000000000000 | |
| 614 | #define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_CONFIG5_RESET_VALUE 0x0000000000000000 | |
| 615 | /* END CSTYLED */ | |
| 616 | ||
| 617 | #ifdef __cplusplus | |
| 618 | } | |
| 619 | #endif | |
| 620 | ||
| 621 | #endif /* _FIRE_REGS_H */ |