projects / OpenSPARC-T2-SAM / blame
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| 920dae64 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * Hypervisor Software File: ldc.h | |
| 5 | * | |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 7 | * | |
| 8 | * - Do no alter or remove copyright notices | |
| 9 | * | |
| 10 | * - Redistribution and use of this software in source and binary forms, with | |
| 11 | * or without modification, are permitted provided that the following | |
| 12 | * conditions are met: | |
| 13 | * | |
| 14 | * - Redistribution of source code must retain the above copyright notice, | |
| 15 | * this list of conditions and the following disclaimer. | |
| 16 | * | |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
| 18 | * this list of conditions and the following disclaimer in the | |
| 19 | * documentation and/or other materials provided with the distribution. | |
| 20 | * | |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
| 22 | * may be used to endorse or promote products derived from this software | |
| 23 | * without specific prior written permission. | |
| 24 | * | |
| 25 | * This software is provided "AS IS," without a warranty of any kind. | |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
| 37 | * | |
| 38 | * You acknowledge that this software is not designed, licensed or | |
| 39 | * intended for use in the design, construction, operation or maintenance of | |
| 40 | * any nuclear facility. | |
| 41 | * | |
| 42 | * ========== Copyright Header End ============================================ | |
| 43 | */ | |
| 44 | /* | |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
| 46 | * Use is subject to license terms. | |
| 47 | */ | |
| 48 | ||
| 49 | #ifndef _PLATFORM_LDC_H | |
| 50 | #define _PLATFORM_LDC_H | |
| 51 | ||
| 52 | #pragma ident "@(#)ldc.h 1.2 07/05/04 SMI" | |
| 53 | ||
| 54 | #ifdef __cplusplus | |
| 55 | extern "C" { | |
| 56 | #endif | |
| 57 | ||
| 58 | /* | |
| 59 | * Location of the SRAM queues | |
| 60 | * XXX - Eventually, we probably want to read this out of the SRAM. | |
| 61 | * For now it is hardcoded between HV and vbsc. | |
| 62 | */ | |
| 63 | #define LDC_SRAM_CHANNEL_TXBASE FPGA_BASE + FPGA_SRAM_BASE + 0x4e0 | |
| 64 | #define LDC_SRAM_CHANNEL_RXBASE FPGA_BASE + FPGA_SRAM_BASE + 0x1c40 | |
| 65 | ||
| 66 | /* | |
| 67 | * FPGA mailbox for LDC | |
| 68 | */ | |
| 69 | #define FPGA_LDCIN_BASE FPGA_Q1IN_BASE | |
| 70 | #define FPGA_LDCOUT_BASE FPGA_Q1OUT_BASE | |
| 71 | ||
| 72 | /* | |
| 73 | * FPGA Interrupts for LDC | |
| 74 | */ | |
| 75 | #define IRQ_LDC_IN IRQ1_QUEUE_IN | |
| 76 | #define IRQ_LDC_OUT IRQ1_QUEUE_OUT | |
| 77 | ||
| 78 | /* | |
| 79 | * Send the SP an interrupt on the LDC IN channel. | |
| 80 | * | |
| 81 | * target_endpt target endpoint, preserved (unused) | |
| 82 | * tmp1, tmp2 clobbered | |
| 83 | * status_bit interrupt type | |
| 84 | */ | |
| 85 | /* BEGIN CSTYLED */ | |
| 86 | #define LDC_SEND_SP_INTR(target_endpt, tmp1, tmp2, status_bit) \ | |
| 87 | .pushlocals; \ | |
| 88 | ROOT_STRUCT(tmp1); \ | |
| 89 | mov CONFIG_FPGA_STATUS_LOCK, tmp2; \ | |
| 90 | add tmp1, tmp2, tmp1; /* address of lock */ \ | |
| 91 | 1: mov 1, tmp2; \ | |
| 92 | casx [tmp1], %g0, tmp2; /* if zero, take lock */ \ | |
| 93 | brnz,pn tmp2, 1b; \ | |
| 94 | nop; \ | |
| 95 | MEMBAR_ENTER; /* we own the lock here */ \ | |
| 96 | setx FPGA_LDCIN_BASE, tmp1, tmp2; \ | |
| 97 | ldub [tmp2 + FPGA_Q_STATUS], tmp1; /* read... */ \ | |
| 98 | or tmp1, status_bit, tmp1; /* modify.. */ \ | |
| 99 | stub tmp1, [tmp2 + FPGA_Q_STATUS]; /* write */ \ | |
| 100 | ROOT_STRUCT(tmp1); \ | |
| 101 | mov CONFIG_FPGA_STATUS_LOCK, tmp2; \ | |
| 102 | add tmp1, tmp2, tmp1; /* address of lock */ \ | |
| 103 | MEMBAR_EXIT; \ | |
| 104 | stx %g0, [tmp1]; /* release the lock */ \ | |
| 105 | .poplocals | |
| 106 | /* END CSTYLED */ | |
| 107 | ||
| 108 | #ifdef __cplusplus | |
| 109 | } | |
| 110 | #endif | |
| 111 | ||
| 112 | #endif /* _PLATFORM_LDC_H */ |